_hw_sdhc_irqstaten Union Reference

HW_SDHC_IRQSTATEN - Interrupt Status Enable register (RW) More...

#include <MK64F12_sdhc.h>

Detailed Description

HW_SDHC_IRQSTATEN - Interrupt Status Enable register (RW)

Reset value: 0x117F013FU

Setting the bits in this register to 1 enables the corresponding interrupt status to be set by the specified event. If any bit is cleared, the corresponding interrupt status bit is also cleared, that is, when the bit in this register is cleared, the corresponding bit in interrupt status register is always 0. Depending on PROCTL[IABG] bit setting, SDHC may be programmed to sample the card interrupt signal during the interrupt period and hold its value in the flip-flop. There will be some delays on the card interrupt, asserted from the card, to the time the host system is informed. To detect a CMD line conflict, the host driver must set both IRQSTATEN[CTOESEN] and IRQSTATEN[CCESEN] to 1.

Definition at line 2925 of file MK64F12_sdhc.h.