Wilson Tang / max14724

8:4 Matrix Multiplexer

Fork of max14661 by Maxim Integrated

This is an untested driver for the MAX14724.

max14661.h@9:27cfbbce3094, 2015-03-17 (annotated)

Committer:
j3
Date:
Tue Mar 17 00:05:40 2015 +0000
Revision:
9:27cfbbce3094
Parent:
8:44257d87fa9e 
moved enums into class

Who changed what in which revision?

UserRevisionLine numberNew contents of line
j3 0:c770ad7363c8 1 /******************************************************************//**
j3 0:c770ad7363c8 2 * @file max14661.h
j3 0:c770ad7363c8 3 *
j3 0:c770ad7363c8 4 * @author Justin Jordan
j3 0:c770ad7363c8 5 *
j3 7:1d4e59ec0fba 6 * @version 1.0
j3 0:c770ad7363c8 7 *
j3 0:c770ad7363c8 8 * Started: 11NOV14
j3 0:c770ad7363c8 9 *
j3 0:c770ad7363c8 10 * Updated:
j3 0:c770ad7363c8 11 *
j3 0:c770ad7363c8 12 * @brief Header file for MAX14661 class
j3 0:c770ad7363c8 13 *
j3 0:c770ad7363c8 14 ***********************************************************************
j3 0:c770ad7363c8 15 *
j3 0:c770ad7363c8 16 * @copyright
j3 8:44257d87fa9e 17 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
j3 0:c770ad7363c8 18 *
j3 0:c770ad7363c8 19 * Permission is hereby granted, free of charge, to any person obtaining a
j3 0:c770ad7363c8 20 * copy of this software and associated documentation files (the "Software"),
j3 0:c770ad7363c8 21 * to deal in the Software without restriction, including without limitation
j3 0:c770ad7363c8 22 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
j3 0:c770ad7363c8 23 * and/or sell copies of the Software, and to permit persons to whom the
j3 0:c770ad7363c8 24 * Software is furnished to do so, subject to the following conditions:
j3 0:c770ad7363c8 25 *
j3 0:c770ad7363c8 26 * The above copyright notice and this permission notice shall be included
j3 0:c770ad7363c8 27 * in all copies or substantial portions of the Software.
j3 0:c770ad7363c8 28 *
j3 0:c770ad7363c8 29 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
j3 0:c770ad7363c8 30 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
j3 0:c770ad7363c8 31 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
j3 0:c770ad7363c8 32 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
j3 0:c770ad7363c8 33 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
j3 0:c770ad7363c8 34 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
j3 0:c770ad7363c8 35 * OTHER DEALINGS IN THE SOFTWARE.
j3 0:c770ad7363c8 36 *
j3 0:c770ad7363c8 37 * Except as contained in this notice, the name of Maxim Integrated
j3 0:c770ad7363c8 38 * Products, Inc. shall not be used except as stated in the Maxim Integrated
j3 0:c770ad7363c8 39 * Products, Inc. Branding Policy.
j3 0:c770ad7363c8 40 *
j3 0:c770ad7363c8 41 * The mere transfer of this software does not imply any licenses
j3 0:c770ad7363c8 42 * of trade secrets, proprietary technology, copyrights, patents,
j3 0:c770ad7363c8 43 * trademarks, maskwork rights, or any other form of intellectual
j3 0:c770ad7363c8 44 * property whatsoever. Maxim Integrated Products, Inc. retains all
j3 0:c770ad7363c8 45 * ownership rights.
j3 0:c770ad7363c8 46 **********************************************************************/
j3 0:c770ad7363c8 47
j3 0:c770ad7363c8 48
j3 0:c770ad7363c8 49 #ifndef MAX14661_H
j3 0:c770ad7363c8 50 #define MAX14661_H
j3 0:c770ad7363c8 51
j3 0:c770ad7363c8 52
j3 0:c770ad7363c8 53 #include "mbed.h"
j3 0:c770ad7363c8 54
j3 0:c770ad7363c8 55
j3 0:c770ad7363c8 56 /******************************************************************//**
j3 0:c770ad7363c8 57 * Max14661 Class
j3 0:c770ad7363c8 58 **********************************************************************/
j3 2:88c168ddc145 59 class Max14661 : public I2C
j3 0:c770ad7363c8 60 {
j3 0:c770ad7363c8 61 uint8_t w_adrs, r_adrs;
j3 0:c770ad7363c8 62
j3 0:c770ad7363c8 63 public:
j3 9:27cfbbce3094 64
j3 9:27cfbbce3094 65 /**
j3 9:27cfbbce3094 66 * max14661_i2c_adrs_t - enumerated MAX14661 I2C Addresses
j3 9:27cfbbce3094 67 */
j3 9:27cfbbce3094 68 typedef enum
j3 9:27cfbbce3094 69 {
j3 9:27cfbbce3094 70 MAX14661_I2C_ADRS0 = 0x4C,
j3 9:27cfbbce3094 71 MAX14661_I2C_ADRS1,
j3 9:27cfbbce3094 72 MAX14661_I2C_ADRS2,
j3 9:27cfbbce3094 73 MAX14661_I2C_ADRS3
j3 9:27cfbbce3094 74 }max14661_i2c_adrs_t;
j3 9:27cfbbce3094 75
j3 9:27cfbbce3094 76
j3 9:27cfbbce3094 77 /**
j3 9:27cfbbce3094 78 * max14661_regs_t - enumerated MAX14661 register addresses
j3 9:27cfbbce3094 79 */
j3 9:27cfbbce3094 80 typedef enum
j3 9:27cfbbce3094 81 {
j3 9:27cfbbce3094 82 DIR0, //Switches 8A–1A direct read/write access
j3 9:27cfbbce3094 83 DIR1, //Switches 16A–9A direct read/write access
j3 9:27cfbbce3094 84 DIR2, //Switches 8B–1B direct read/write access
j3 9:27cfbbce3094 85 DIR3, //Switches 16B–9B direct read/write access
j3 9:27cfbbce3094 86 SHDW0 = 0x10, //Switches 8A–1A shadow read/write access
j3 9:27cfbbce3094 87 SHDW1, //Switches 16A–9A shadow read/write access
j3 9:27cfbbce3094 88 SHDW2, //Switches 8B–1B shadow read/write access
j3 9:27cfbbce3094 89 SHDW3, //Switches 16B–9B shadow read/write access
j3 9:27cfbbce3094 90 CMD_A, //Set mux A command (reads 0x00)
j3 9:27cfbbce3094 91 CMD_B //Set mux B command (reads 0x00)
j3 9:27cfbbce3094 92 }max14661_regs_t;
j3 9:27cfbbce3094 93
j3 9:27cfbbce3094 94
j3 9:27cfbbce3094 95 /**
j3 9:27cfbbce3094 96 * max14661_cmds_t - enumerated MAX14661 commands
j3 9:27cfbbce3094 97 */
j3 9:27cfbbce3094 98 typedef enum
j3 9:27cfbbce3094 99 {
j3 9:27cfbbce3094 100 ENABLE_SW01, //enables sw1 on bank only
j3 9:27cfbbce3094 101 ENABLE_SW02, //enables sw2 on bank only
j3 9:27cfbbce3094 102 ENABLE_SW03, //enables sw3 on bank only
j3 9:27cfbbce3094 103 ENABLE_SW04, //enables sw4 on bank only
j3 9:27cfbbce3094 104 ENABLE_SW05, //enables sw5 on bank only
j3 9:27cfbbce3094 105 ENABLE_SW06, //enables sw6 on bank only
j3 9:27cfbbce3094 106 ENABLE_SW07, //enables sw7 on bank only
j3 9:27cfbbce3094 107 ENABLE_SW08, //enables sw8 on bank only
j3 9:27cfbbce3094 108 ENABLE_SW09, //enables sw9 on bank only
j3 9:27cfbbce3094 109 ENABLE_SW10, //enables sw10 on bank only
j3 9:27cfbbce3094 110 ENABLE_SW11, //enables sw11 on bank only
j3 9:27cfbbce3094 111 ENABLE_SW12, //enables sw12 on bank only
j3 9:27cfbbce3094 112 ENABLE_SW13, //enables sw13 on bank only
j3 9:27cfbbce3094 113 ENABLE_SW14, //enables sw14 on bank only
j3 9:27cfbbce3094 114 ENABLE_SW15, //enables sw15 on bank only
j3 9:27cfbbce3094 115 ENABLE_SW16, //enables sw16 on bank only
j3 9:27cfbbce3094 116 DISABLE_BANK, //opens all switches on bank
j3 9:27cfbbce3094 117 COPY_SHADOW, //copies both shadow registers for bank
j3 9:27cfbbce3094 118 NO_CHANGE,
j3 9:27cfbbce3094 119 }max14661_cmds_t;
j3 9:27cfbbce3094 120
j3 9:27cfbbce3094 121
j3 9:27cfbbce3094 122 /**
j3 9:27cfbbce3094 123 * max14661_sw_t - enumerated MAX14661 switch bitmasks
j3 9:27cfbbce3094 124 */
j3 9:27cfbbce3094 125 typedef enum
j3 9:27cfbbce3094 126 {
j3 9:27cfbbce3094 127 SW01 = (1 << 0),
j3 9:27cfbbce3094 128 SW02 = (1 << 1),
j3 9:27cfbbce3094 129 SW03 = (1 << 2),
j3 9:27cfbbce3094 130 SW04 = (1 << 3),
j3 9:27cfbbce3094 131 SW05 = (1 << 4),
j3 9:27cfbbce3094 132 SW06 = (1 << 5),
j3 9:27cfbbce3094 133 SW07 = (1 << 6),
j3 9:27cfbbce3094 134 SW08 = (1 << 7),
j3 9:27cfbbce3094 135 SW09 = (1 << 8),
j3 9:27cfbbce3094 136 SW10 = (1 << 9),
j3 9:27cfbbce3094 137 SW11 = (1 << 10),
j3 9:27cfbbce3094 138 SW12 = (1 << 11),
j3 9:27cfbbce3094 139 SW13 = (1 << 12),
j3 9:27cfbbce3094 140 SW14 = (1 << 13),
j3 9:27cfbbce3094 141 SW15 = (1 << 14),
j3 9:27cfbbce3094 142 SW16 = (1 << 15)
j3 9:27cfbbce3094 143 }max14661_sw_t;
j3 9:27cfbbce3094 144
j3 9:27cfbbce3094 145
j3 0:c770ad7363c8 146 /**********************************************************//**
j3 1:c1fdfe4c2354 147 * Constructor for Max14661 Class
j3 0:c770ad7363c8 148 *
j3 0:c770ad7363c8 149 * On Entry:
j3 2:88c168ddc145 150 * @param[in] sda - sda pin of I2C bus
j3 2:88c168ddc145 151 * @param[in] scl - scl pin of I2C bus
j3 0:c770ad7363c8 152 * @param[in] i2c_adrs - 7-bit slave address of MAX14661
j3 0:c770ad7363c8 153 *
j3 0:c770ad7363c8 154 * On Exit:
j3 0:c770ad7363c8 155 * @return none
j3 0:c770ad7363c8 156 *
j3 0:c770ad7363c8 157 * Example:
j3 0:c770ad7363c8 158 * @code
j3 0:c770ad7363c8 159 *
j3 2:88c168ddc145 160 * //declare mux object
j3 2:88c168ddc145 161 * Max14661 mux(D14, D15, MAX14661_I2C_ADRS0);
j3 0:c770ad7363c8 162 *
j3 0:c770ad7363c8 163 * @endcode
j3 0:c770ad7363c8 164 **************************************************************/
j3 2:88c168ddc145 165 Max14661(PinName sda, PinName scl, max14661_i2c_adrs_t i2c_adrs);
j3 0:c770ad7363c8 166
j3 4:45fa0192f66d 167
j3 0:c770ad7363c8 168 /******************************************************************//**
j3 0:c770ad7363c8 169 * Writes given commands to CMD_A and CMD_B
j3 0:c770ad7363c8 170 *
j3 0:c770ad7363c8 171 * On Entry:
j3 0:c770ad7363c8 172 * @param[in] cmdA - command for CMD_A
j3 0:c770ad7363c8 173 * @param[in] cmdB - command for CMD_B
j3 0:c770ad7363c8 174 *
j3 0:c770ad7363c8 175 * On Exit:
j3 0:c770ad7363c8 176 * @return return value = 0 on success, non-0 on failure
j3 0:c770ad7363c8 177 *
j3 0:c770ad7363c8 178 * Example:
j3 0:c770ad7363c8 179 * @code
j3 0:c770ad7363c8 180 *
j3 2:88c168ddc145 181 * //declare mux object
j3 2:88c168ddc145 182 * Max14661 mux(D14, D15, MAX14661_I2C_ADRS0);
j3 0:c770ad7363c8 183 *
j3 0:c770ad7363c8 184 * uint16_t rtn_val;
j3 0:c770ad7363c8 185 *
j3 0:c770ad7363c8 186 * rtn_val = mux.wrt_cmd_registers(DISABLE_BANK, DISABLE_BANK);
j3 0:c770ad7363c8 187 *
j3 0:c770ad7363c8 188 * @endcode
j3 0:c770ad7363c8 189 **********************************************************************/
j3 4:45fa0192f66d 190 uint16_t wrt_cmd_registers(max14661_cmds_t cmdA, max14661_cmds_t cmdB);
j3 4:45fa0192f66d 191
j3 4:45fa0192f66d 192
j3 0:c770ad7363c8 193 /******************************************************************//**
j3 4:45fa0192f66d 194 * Writes bankA and bankB to coresponding shadow registers
j3 0:c770ad7363c8 195 *
j3 0:c770ad7363c8 196 * On Entry:
j3 4:45fa0192f66d 197 * @param[in] bankA - binary representation of switch states
j3 4:45fa0192f66d 198 * @param[in] bankB - binary representation of switch states
j3 0:c770ad7363c8 199 *
j3 0:c770ad7363c8 200 * On Exit:
j3 0:c770ad7363c8 201 * @return return value = 0 on success, non-0 on failure
j3 0:c770ad7363c8 202 *
j3 0:c770ad7363c8 203 * Example:
j3 0:c770ad7363c8 204 * @code
j3 0:c770ad7363c8 205 *
j3 2:88c168ddc145 206 * //declare mux object
j3 2:88c168ddc145 207 * Max14661 mux(D14, D15, MAX14661_I2C_ADRS0);
j3 0:c770ad7363c8 208 *
j3 4:45fa0192f66d 209 * uint16_t bankA = (SW12 | SW02); //example only
j3 4:45fa0192f66d 210 * uint16_t bankB = (SW11 | SW01);
j3 0:c770ad7363c8 211 * uint16_t rtn_val;
j3 0:c770ad7363c8 212 *
j3 0:c770ad7363c8 213 * //wite shadow registers
j3 4:45fa0192f66d 214 * rtn_val = mux.wrt_shadow_registers(bankA, bankB);
j3 0:c770ad7363c8 215 *
j3 0:c770ad7363c8 216 * @endcode
j3 0:c770ad7363c8 217 **********************************************************************/
j3 4:45fa0192f66d 218 uint16_t wrt_shadow_registers(uint16_t bankA, uint16_t bankB);
j3 4:45fa0192f66d 219
j3 4:45fa0192f66d 220
j3 0:c770ad7363c8 221 /******************************************************************//**
j3 4:45fa0192f66d 222 * Writes bankA and bankB to coresponding direct access registers
j3 0:c770ad7363c8 223 *
j3 0:c770ad7363c8 224 * On Entry:
j3 4:45fa0192f66d 225 * @param[in] bankA - binary representation of switch states
j3 4:45fa0192f66d 226 * @param[in] bankB - binary representation of switch states
j3 0:c770ad7363c8 227 *
j3 0:c770ad7363c8 228 * On Exit:
j3 0:c770ad7363c8 229 * @return return value = 0 on success, non-0 on failure
j3 0:c770ad7363c8 230 *
j3 0:c770ad7363c8 231 * Example:
j3 1:c1fdfe4c2354 232 * @code
j3 0:c770ad7363c8 233 *
j3 2:88c168ddc145 234 * //declare mux object
j3 2:88c168ddc145 235 * Max14661 mux(D14, D15, MAX14661_I2C_ADRS0);
j3 0:c770ad7363c8 236 *
j3 4:45fa0192f66d 237 * uint16_t bankA = (SW12 | SW02); //example only
j3 4:45fa0192f66d 238 * uint16_t bankB = (SW11 | SW01);
j3 0:c770ad7363c8 239 * uint16_t rtn_val;
j3 0:c770ad7363c8 240 *
j3 0:c770ad7363c8 241 * //wite shadow registers
j3 4:45fa0192f66d 242 * rtn_val = mux.wrt_dir_registers(bankA, bankB);
j3 0:c770ad7363c8 243 *
j3 0:c770ad7363c8 244 * @endcode
j3 0:c770ad7363c8 245 **********************************************************************/
j3 4:45fa0192f66d 246 uint16_t wrt_dir_registers(uint16_t bankA, uint16_t bankB);
j3 4:45fa0192f66d 247
j3 4:45fa0192f66d 248
j3 4:45fa0192f66d 249 /******************************************************************//**
j3 4:45fa0192f66d 250 * Writes bankA and bankB to coresponding shadow register and then
j3 4:45fa0192f66d 251 * issues copy command for both banks
j3 4:45fa0192f66d 252 *
j3 4:45fa0192f66d 253 * On Entry:
j3 4:45fa0192f66d 254 * @param[in] bankA - binary representation of switch states
j3 4:45fa0192f66d 255 * @param[in] bankB - binary representation of switch states
j3 4:45fa0192f66d 256 *
j3 4:45fa0192f66d 257 * On Exit:
j3 4:45fa0192f66d 258 * @return return value = 0 on success, non-0 on failure
j3 4:45fa0192f66d 259 *
j3 4:45fa0192f66d 260 * Example:
j3 4:45fa0192f66d 261 * @code
j3 4:45fa0192f66d 262 *
j3 4:45fa0192f66d 263 * //declare mux object
j3 4:45fa0192f66d 264 * Max14661 mux(D14, D15, MAX14661_I2C_ADRS0);
j3 4:45fa0192f66d 265 *
j3 4:45fa0192f66d 266 * uint16_t bankA = (SW12 | SW02); //example only
j3 4:45fa0192f66d 267 * uint16_t bankB = (SW11 | SW01);
j3 4:45fa0192f66d 268 * uint16_t rtn_val;
j3 4:45fa0192f66d 269 *
j3 4:45fa0192f66d 270 * //wite shadow registers
j3 4:45fa0192f66d 271 * rtn_val = mux.set_switches(bankA, bankB);
j3 4:45fa0192f66d 272 *
j3 4:45fa0192f66d 273 * @endcode
j3 4:45fa0192f66d 274 **********************************************************************/
j3 4:45fa0192f66d 275 uint16_t set_switches(uint16_t bankA, uint16_t bankB);
j3 4:45fa0192f66d 276
j3 4:45fa0192f66d 277
j3 0:c770ad7363c8 278 /**********************************************************//**
j3 0:c770ad7363c8 279 * Reads data from direct access registers starting at DIR0 and
j3 0:c770ad7363c8 280 * stores it in byte array pointed at by 'data'
j3 0:c770ad7363c8 281 *
j3 0:c770ad7363c8 282 * On Entry:
j3 0:c770ad7363c8 283 * @param[in] data - pointer to byte array for storing data
j3 0:c770ad7363c8 284 *
j3 0:c770ad7363c8 285 * On Exit:
j3 0:c770ad7363c8 286 * @param[out] data - data buffer now contains data read
j3 0:c770ad7363c8 287 * from dir registers
j3 0:c770ad7363c8 288 * @return return value = 0 on success, non-0 on failure
j3 0:c770ad7363c8 289 *
j3 0:c770ad7363c8 290 * Example:
j3 0:c770ad7363c8 291 * @code
j3 0:c770ad7363c8 292 *
j3 2:88c168ddc145 293 * //declare mux object
j3 2:88c168ddc145 294 * Max14661 mux(D14, D15, MAX14661_I2C_ADRS0);
j3 0:c770ad7363c8 295 *
j3 0:c770ad7363c8 296 * uint16_t rtn_val;
j3 0:c770ad7363c8 297 * uint8_t data[4];
j3 0:c770ad7363c8 298 *
j3 0:c770ad7363c8 299 * //read direct access registers
j3 0:c770ad7363c8 300 * rtn_val = mux.rd_dir_registers(data);
j3 0:c770ad7363c8 301 *
j3 0:c770ad7363c8 302 * @endcode
j3 0:c770ad7363c8 303 **********************************************************************/
j3 0:c770ad7363c8 304 uint16_t rd_dir_registers(uint8_t* data);
j3 4:45fa0192f66d 305
j3 4:45fa0192f66d 306
j3 0:c770ad7363c8 307 /**********************************************************//**
j3 0:c770ad7363c8 308 * Reads data from shadow registers starting at SHDW0 and stores
j3 0:c770ad7363c8 309 * it in byte array pointed at by 'data'
j3 0:c770ad7363c8 310 *
j3 0:c770ad7363c8 311 * On Entry:
j3 0:c770ad7363c8 312 * @param[in] data - pointer to byte array for storing data
j3 0:c770ad7363c8 313 *
j3 0:c770ad7363c8 314 * On Exit:
j3 0:c770ad7363c8 315 * @param[out] data - data buffer now contains data read
j3 0:c770ad7363c8 316 * from shadow registers
j3 0:c770ad7363c8 317 * @return return value = 0 on success, non-0 on failure
j3 0:c770ad7363c8 318 *
j3 0:c770ad7363c8 319 * Example:
j3 0:c770ad7363c8 320 * @code
j3 0:c770ad7363c8 321 *
j3 2:88c168ddc145 322 * //declare mux object
j3 2:88c168ddc145 323 * Max14661 mux(D14, D15, MAX14661_I2C_ADRS0);
j3 0:c770ad7363c8 324 *
j3 0:c770ad7363c8 325 * uint16_t rtn_val;
j3 0:c770ad7363c8 326 * uint8_t data[4];
j3 0:c770ad7363c8 327 *
j3 0:c770ad7363c8 328 * //read shadow registers
j3 0:c770ad7363c8 329 * rtn_val = mux.rd_shadow_registers(data);
j3 0:c770ad7363c8 330 *
j3 0:c770ad7363c8 331 * @endcode
j3 4:45fa0192f66d 332 **************************************************************/
j3 0:c770ad7363c8 333 uint16_t rd_shadow_registers(uint8_t* data);
j3 0:c770ad7363c8 334 };
j3 0:c770ad7363c8 335
j3 0:c770ad7363c8 336
j3 0:c770ad7363c8 337 #endif /* MAX14661_H*/