Wilson Tang / max14724

8:4 Matrix Multiplexer

Fork of max14661 by Maxim Integrated

This is an untested driver for the MAX14724.

max14661.h@4:45fa0192f66d, 2014-11-21 (annotated)

Committer:
j3
Date:
Fri Nov 21 04:31:05 2014 +0000
Revision:
4:45fa0192f66d
Parent:
3:638bf72e3a00
Child:
5:58f3bbd30777
changed input args to write fx from an array to two 16 bit ints that represent switch states for each bank.  Fixed C0PY_SHADOW to COPY_SHADOW

Who changed what in which revision?

UserRevisionLine numberNew contents of line
j3 0:c770ad7363c8 1 /******************************************************************//**
j3 0:c770ad7363c8 2 * @file max14661.h
j3 0:c770ad7363c8 3 *
j3 0:c770ad7363c8 4 * @author Justin Jordan
j3 0:c770ad7363c8 5 *
j3 0:c770ad7363c8 6 * @version 0.0
j3 0:c770ad7363c8 7 *
j3 0:c770ad7363c8 8 * Started: 11NOV14
j3 0:c770ad7363c8 9 *
j3 0:c770ad7363c8 10 * Updated:
j3 0:c770ad7363c8 11 *
j3 0:c770ad7363c8 12 * @brief Header file for MAX14661 class
j3 0:c770ad7363c8 13 *
j3 0:c770ad7363c8 14 ***********************************************************************
j3 0:c770ad7363c8 15 *
j3 0:c770ad7363c8 16 * @copyright
j3 0:c770ad7363c8 17 * Copyright (C) 2013 Maxim Integrated Products, Inc., All Rights Reserved.
j3 0:c770ad7363c8 18 *
j3 0:c770ad7363c8 19 * Permission is hereby granted, free of charge, to any person obtaining a
j3 0:c770ad7363c8 20 * copy of this software and associated documentation files (the "Software"),
j3 0:c770ad7363c8 21 * to deal in the Software without restriction, including without limitation
j3 0:c770ad7363c8 22 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
j3 0:c770ad7363c8 23 * and/or sell copies of the Software, and to permit persons to whom the
j3 0:c770ad7363c8 24 * Software is furnished to do so, subject to the following conditions:
j3 0:c770ad7363c8 25 *
j3 0:c770ad7363c8 26 * The above copyright notice and this permission notice shall be included
j3 0:c770ad7363c8 27 * in all copies or substantial portions of the Software.
j3 0:c770ad7363c8 28 *
j3 0:c770ad7363c8 29 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
j3 0:c770ad7363c8 30 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
j3 0:c770ad7363c8 31 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
j3 0:c770ad7363c8 32 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
j3 0:c770ad7363c8 33 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
j3 0:c770ad7363c8 34 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
j3 0:c770ad7363c8 35 * OTHER DEALINGS IN THE SOFTWARE.
j3 0:c770ad7363c8 36 *
j3 0:c770ad7363c8 37 * Except as contained in this notice, the name of Maxim Integrated
j3 0:c770ad7363c8 38 * Products, Inc. shall not be used except as stated in the Maxim Integrated
j3 0:c770ad7363c8 39 * Products, Inc. Branding Policy.
j3 0:c770ad7363c8 40 *
j3 0:c770ad7363c8 41 * The mere transfer of this software does not imply any licenses
j3 0:c770ad7363c8 42 * of trade secrets, proprietary technology, copyrights, patents,
j3 0:c770ad7363c8 43 * trademarks, maskwork rights, or any other form of intellectual
j3 0:c770ad7363c8 44 * property whatsoever. Maxim Integrated Products, Inc. retains all
j3 0:c770ad7363c8 45 * ownership rights.
j3 0:c770ad7363c8 46 **********************************************************************/
j3 0:c770ad7363c8 47
j3 0:c770ad7363c8 48
j3 0:c770ad7363c8 49 #ifndef MAX14661_H
j3 0:c770ad7363c8 50 #define MAX14661_H
j3 0:c770ad7363c8 51
j3 0:c770ad7363c8 52
j3 0:c770ad7363c8 53 #include "mbed.h"
j3 0:c770ad7363c8 54
j3 0:c770ad7363c8 55
j3 0:c770ad7363c8 56 //MAX14661 I2C Addresses
j3 0:c770ad7363c8 57 typedef enum
j3 0:c770ad7363c8 58 {
j3 0:c770ad7363c8 59 MAX14661_I2C_ADRS0 = 0x4C,
j3 0:c770ad7363c8 60 MAX14661_I2C_ADRS1,
j3 0:c770ad7363c8 61 MAX14661_I2C_ADRS2,
j3 0:c770ad7363c8 62 MAX14661_I2C_ADRS3
j3 0:c770ad7363c8 63 }max14661_i2c_adrs_t;
j3 0:c770ad7363c8 64
j3 0:c770ad7363c8 65
j3 0:c770ad7363c8 66 //MAX14661 I2C register addresses
j3 0:c770ad7363c8 67 typedef enum
j3 0:c770ad7363c8 68 {
j3 0:c770ad7363c8 69 DIR0, //Switches 8A–1A direct read/write access
j3 0:c770ad7363c8 70 DIR1, //Switches 16A–9A direct read/write access
j3 0:c770ad7363c8 71 DIR2, //Switches 8B–1B direct read/write access
j3 0:c770ad7363c8 72 DIR3, //Switches 16B–9B direct read/write access
j3 0:c770ad7363c8 73 SHDW0 = 0x10, //Switches 8A–1A shadow read/write access
j3 0:c770ad7363c8 74 SHDW1, //Switches 16A–9A shadow read/write access
j3 0:c770ad7363c8 75 SHDW2, //Switches 8B–1B shadow read/write access
j3 0:c770ad7363c8 76 SHDW3, //Switches 16B–9B shadow read/write access
j3 0:c770ad7363c8 77 CMD_A, //Set mux A command (reads 0x00)
j3 0:c770ad7363c8 78 CMD_B //Set mux B command (reads 0x00)
j3 0:c770ad7363c8 79 }max14661_regs_t;
j3 0:c770ad7363c8 80
j3 0:c770ad7363c8 81
j3 0:c770ad7363c8 82 //MAX14661 I2C commands
j3 0:c770ad7363c8 83 typedef enum
j3 0:c770ad7363c8 84 {
j3 0:c770ad7363c8 85 ENABLE_SW01, //enables sw1 on bank only
j3 0:c770ad7363c8 86 ENABLE_SW02, //enables sw2 on bank only
j3 0:c770ad7363c8 87 ENABLE_SW03, //enables sw3 on bank only
j3 0:c770ad7363c8 88 ENABLE_SW04, //enables sw4 on bank only
j3 0:c770ad7363c8 89 ENABLE_SW05, //enables sw5 on bank only
j3 0:c770ad7363c8 90 ENABLE_SW06, //enables sw6 on bank only
j3 0:c770ad7363c8 91 ENABLE_SW07, //enables sw7 on bank only
j3 0:c770ad7363c8 92 ENABLE_SW08, //enables sw8 on bank only
j3 0:c770ad7363c8 93 ENABLE_SW09, //enables sw9 on bank only
j3 0:c770ad7363c8 94 ENABLE_SW10, //enables sw10 on bank only
j3 0:c770ad7363c8 95 ENABLE_SW11, //enables sw11 on bank only
j3 0:c770ad7363c8 96 ENABLE_SW12, //enables sw12 on bank only
j3 0:c770ad7363c8 97 ENABLE_SW13, //enables sw13 on bank only
j3 0:c770ad7363c8 98 ENABLE_SW14, //enables sw14 on bank only
j3 0:c770ad7363c8 99 ENABLE_SW15, //enables sw15 on bank only
j3 0:c770ad7363c8 100 ENABLE_SW16, //enables sw16 on bank only
j3 0:c770ad7363c8 101 DISABLE_BANK, //opens all switches on bank
j3 4:45fa0192f66d 102 COPY_SHADOW, //copies both shadow registers for bank
j3 0:c770ad7363c8 103 NO_CHANGE,
j3 0:c770ad7363c8 104 }max14661_cmds_t;
j3 0:c770ad7363c8 105
j3 0:c770ad7363c8 106
j3 0:c770ad7363c8 107 //MAX14661 I2C switch bitmasks
j3 0:c770ad7363c8 108 typedef enum
j3 0:c770ad7363c8 109 {
j3 0:c770ad7363c8 110 SW01 = (1 << 0),
j3 0:c770ad7363c8 111 SW02 = (1 << 1),
j3 0:c770ad7363c8 112 SW03 = (1 << 2),
j3 0:c770ad7363c8 113 SW04 = (1 << 3),
j3 0:c770ad7363c8 114 SW05 = (1 << 4),
j3 0:c770ad7363c8 115 SW06 = (1 << 5),
j3 0:c770ad7363c8 116 SW07 = (1 << 6),
j3 0:c770ad7363c8 117 SW08 = (1 << 7),
j3 0:c770ad7363c8 118 SW09 = (1 << 8),
j3 0:c770ad7363c8 119 SW10 = (1 << 9),
j3 0:c770ad7363c8 120 SW11 = (1 << 10),
j3 0:c770ad7363c8 121 SW12 = (1 << 11),
j3 0:c770ad7363c8 122 SW13 = (1 << 12),
j3 0:c770ad7363c8 123 SW14 = (1 << 13),
j3 0:c770ad7363c8 124 SW15 = (1 << 14),
j3 0:c770ad7363c8 125 SW16 = (1 << 15)
j3 0:c770ad7363c8 126 }max14661_sw_t;
j3 0:c770ad7363c8 127
j3 0:c770ad7363c8 128
j3 0:c770ad7363c8 129 /******************************************************************//**
j3 0:c770ad7363c8 130 * Max14661 Class
j3 0:c770ad7363c8 131 **********************************************************************/
j3 2:88c168ddc145 132 class Max14661 : public I2C
j3 0:c770ad7363c8 133 {
j3 0:c770ad7363c8 134 uint8_t w_adrs, r_adrs;
j3 0:c770ad7363c8 135
j3 0:c770ad7363c8 136 public:
j3 0:c770ad7363c8 137 /**********************************************************//**
j3 1:c1fdfe4c2354 138 * Constructor for Max14661 Class
j3 0:c770ad7363c8 139 *
j3 0:c770ad7363c8 140 * On Entry:
j3 2:88c168ddc145 141 * @param[in] sda - sda pin of I2C bus
j3 2:88c168ddc145 142 * @param[in] scl - scl pin of I2C bus
j3 0:c770ad7363c8 143 * @param[in] i2c_adrs - 7-bit slave address of MAX14661
j3 0:c770ad7363c8 144 *
j3 0:c770ad7363c8 145 * On Exit:
j3 0:c770ad7363c8 146 * @return none
j3 0:c770ad7363c8 147 *
j3 0:c770ad7363c8 148 * Example:
j3 0:c770ad7363c8 149 * @code
j3 0:c770ad7363c8 150 *
j3 2:88c168ddc145 151 * //declare mux object
j3 2:88c168ddc145 152 * Max14661 mux(D14, D15, MAX14661_I2C_ADRS0);
j3 0:c770ad7363c8 153 *
j3 0:c770ad7363c8 154 * @endcode
j3 0:c770ad7363c8 155 **************************************************************/
j3 2:88c168ddc145 156 Max14661(PinName sda, PinName scl, max14661_i2c_adrs_t i2c_adrs);
j3 0:c770ad7363c8 157
j3 4:45fa0192f66d 158
j3 0:c770ad7363c8 159 /******************************************************************//**
j3 0:c770ad7363c8 160 * Writes given commands to CMD_A and CMD_B
j3 0:c770ad7363c8 161 *
j3 0:c770ad7363c8 162 * On Entry:
j3 0:c770ad7363c8 163 * @param[in] cmdA - command for CMD_A
j3 0:c770ad7363c8 164 * @param[in] cmdB - command for CMD_B
j3 0:c770ad7363c8 165 *
j3 0:c770ad7363c8 166 * On Exit:
j3 0:c770ad7363c8 167 * @return return value = 0 on success, non-0 on failure
j3 0:c770ad7363c8 168 *
j3 0:c770ad7363c8 169 * Example:
j3 0:c770ad7363c8 170 * @code
j3 0:c770ad7363c8 171 *
j3 2:88c168ddc145 172 * //declare mux object
j3 2:88c168ddc145 173 * Max14661 mux(D14, D15, MAX14661_I2C_ADRS0);
j3 0:c770ad7363c8 174 *
j3 0:c770ad7363c8 175 * uint16_t rtn_val;
j3 0:c770ad7363c8 176 *
j3 0:c770ad7363c8 177 * rtn_val = mux.wrt_cmd_registers(DISABLE_BANK, DISABLE_BANK);
j3 0:c770ad7363c8 178 *
j3 0:c770ad7363c8 179 * @endcode
j3 0:c770ad7363c8 180 **********************************************************************/
j3 4:45fa0192f66d 181 uint16_t wrt_cmd_registers(max14661_cmds_t cmdA, max14661_cmds_t cmdB);
j3 4:45fa0192f66d 182
j3 4:45fa0192f66d 183
j3 0:c770ad7363c8 184 /******************************************************************//**
j3 4:45fa0192f66d 185 * Writes bankA and bankB to coresponding shadow registers
j3 0:c770ad7363c8 186 *
j3 0:c770ad7363c8 187 * On Entry:
j3 4:45fa0192f66d 188 * @param[in] bankA - binary representation of switch states
j3 4:45fa0192f66d 189 * @param[in] bankB - binary representation of switch states
j3 0:c770ad7363c8 190 *
j3 0:c770ad7363c8 191 * On Exit:
j3 0:c770ad7363c8 192 * @return return value = 0 on success, non-0 on failure
j3 0:c770ad7363c8 193 *
j3 0:c770ad7363c8 194 * Example:
j3 0:c770ad7363c8 195 * @code
j3 0:c770ad7363c8 196 *
j3 2:88c168ddc145 197 * //declare mux object
j3 2:88c168ddc145 198 * Max14661 mux(D14, D15, MAX14661_I2C_ADRS0);
j3 0:c770ad7363c8 199 *
j3 4:45fa0192f66d 200 * uint16_t bankA = (SW12 | SW02); //example only
j3 4:45fa0192f66d 201 * uint16_t bankB = (SW11 | SW01);
j3 0:c770ad7363c8 202 * uint16_t rtn_val;
j3 0:c770ad7363c8 203 *
j3 0:c770ad7363c8 204 * //wite shadow registers
j3 4:45fa0192f66d 205 * rtn_val = mux.wrt_shadow_registers(bankA, bankB);
j3 0:c770ad7363c8 206 *
j3 0:c770ad7363c8 207 * @endcode
j3 0:c770ad7363c8 208 **********************************************************************/
j3 4:45fa0192f66d 209 uint16_t wrt_shadow_registers(uint16_t bankA, uint16_t bankB);
j3 4:45fa0192f66d 210
j3 4:45fa0192f66d 211
j3 0:c770ad7363c8 212 /******************************************************************//**
j3 4:45fa0192f66d 213 * Writes bankA and bankB to coresponding direct access registers
j3 0:c770ad7363c8 214 *
j3 0:c770ad7363c8 215 * On Entry:
j3 4:45fa0192f66d 216 * @param[in] bankA - binary representation of switch states
j3 4:45fa0192f66d 217 * @param[in] bankB - binary representation of switch states
j3 0:c770ad7363c8 218 *
j3 0:c770ad7363c8 219 * On Exit:
j3 0:c770ad7363c8 220 * @return return value = 0 on success, non-0 on failure
j3 0:c770ad7363c8 221 *
j3 0:c770ad7363c8 222 * Example:
j3 1:c1fdfe4c2354 223 * @code
j3 0:c770ad7363c8 224 *
j3 2:88c168ddc145 225 * //declare mux object
j3 2:88c168ddc145 226 * Max14661 mux(D14, D15, MAX14661_I2C_ADRS0);
j3 0:c770ad7363c8 227 *
j3 4:45fa0192f66d 228 * uint16_t bankA = (SW12 | SW02); //example only
j3 4:45fa0192f66d 229 * uint16_t bankB = (SW11 | SW01);
j3 0:c770ad7363c8 230 * uint16_t rtn_val;
j3 0:c770ad7363c8 231 *
j3 0:c770ad7363c8 232 * //wite shadow registers
j3 4:45fa0192f66d 233 * rtn_val = mux.wrt_dir_registers(bankA, bankB);
j3 0:c770ad7363c8 234 *
j3 0:c770ad7363c8 235 * @endcode
j3 0:c770ad7363c8 236 **********************************************************************/
j3 4:45fa0192f66d 237 uint16_t wrt_dir_registers(uint16_t bankA, uint16_t bankB);
j3 4:45fa0192f66d 238
j3 4:45fa0192f66d 239
j3 4:45fa0192f66d 240 /******************************************************************//**
j3 4:45fa0192f66d 241 * Writes bankA and bankB to coresponding shadow register and then
j3 4:45fa0192f66d 242 * issues copy command for both banks
j3 4:45fa0192f66d 243 *
j3 4:45fa0192f66d 244 * On Entry:
j3 4:45fa0192f66d 245 * @param[in] bankA - binary representation of switch states
j3 4:45fa0192f66d 246 * @param[in] bankB - binary representation of switch states
j3 4:45fa0192f66d 247 *
j3 4:45fa0192f66d 248 * On Exit:
j3 4:45fa0192f66d 249 * @return return value = 0 on success, non-0 on failure
j3 4:45fa0192f66d 250 *
j3 4:45fa0192f66d 251 * Example:
j3 4:45fa0192f66d 252 * @code
j3 4:45fa0192f66d 253 *
j3 4:45fa0192f66d 254 * //declare mux object
j3 4:45fa0192f66d 255 * Max14661 mux(D14, D15, MAX14661_I2C_ADRS0);
j3 4:45fa0192f66d 256 *
j3 4:45fa0192f66d 257 * uint16_t bankA = (SW12 | SW02); //example only
j3 4:45fa0192f66d 258 * uint16_t bankB = (SW11 | SW01);
j3 4:45fa0192f66d 259 * uint16_t rtn_val;
j3 4:45fa0192f66d 260 *
j3 4:45fa0192f66d 261 * //wite shadow registers
j3 4:45fa0192f66d 262 * rtn_val = mux.set_switches(bankA, bankB);
j3 4:45fa0192f66d 263 *
j3 4:45fa0192f66d 264 * @endcode
j3 4:45fa0192f66d 265 **********************************************************************/
j3 4:45fa0192f66d 266 uint16_t set_switches(uint16_t bankA, uint16_t bankB);
j3 4:45fa0192f66d 267
j3 4:45fa0192f66d 268
j3 0:c770ad7363c8 269 /**********************************************************//**
j3 0:c770ad7363c8 270 * Reads data from direct access registers starting at DIR0 and
j3 0:c770ad7363c8 271 * stores it in byte array pointed at by 'data'
j3 0:c770ad7363c8 272 *
j3 0:c770ad7363c8 273 * On Entry:
j3 0:c770ad7363c8 274 * @param[in] data - pointer to byte array for storing data
j3 0:c770ad7363c8 275 *
j3 0:c770ad7363c8 276 * On Exit:
j3 0:c770ad7363c8 277 * @param[out] data - data buffer now contains data read
j3 0:c770ad7363c8 278 * from dir registers
j3 0:c770ad7363c8 279 * @return return value = 0 on success, non-0 on failure
j3 0:c770ad7363c8 280 *
j3 0:c770ad7363c8 281 * Example:
j3 0:c770ad7363c8 282 * @code
j3 0:c770ad7363c8 283 *
j3 2:88c168ddc145 284 * //declare mux object
j3 2:88c168ddc145 285 * Max14661 mux(D14, D15, MAX14661_I2C_ADRS0);
j3 0:c770ad7363c8 286 *
j3 0:c770ad7363c8 287 * uint16_t rtn_val;
j3 0:c770ad7363c8 288 * uint8_t data[4];
j3 0:c770ad7363c8 289 *
j3 0:c770ad7363c8 290 * //read direct access registers
j3 0:c770ad7363c8 291 * rtn_val = mux.rd_dir_registers(data);
j3 0:c770ad7363c8 292 *
j3 0:c770ad7363c8 293 * @endcode
j3 0:c770ad7363c8 294 **********************************************************************/
j3 0:c770ad7363c8 295 uint16_t rd_dir_registers(uint8_t* data);
j3 4:45fa0192f66d 296
j3 4:45fa0192f66d 297
j3 0:c770ad7363c8 298 /**********************************************************//**
j3 0:c770ad7363c8 299 * Reads data from shadow registers starting at SHDW0 and stores
j3 0:c770ad7363c8 300 * it in byte array pointed at by 'data'
j3 0:c770ad7363c8 301 *
j3 0:c770ad7363c8 302 * On Entry:
j3 0:c770ad7363c8 303 * @param[in] data - pointer to byte array for storing data
j3 0:c770ad7363c8 304 *
j3 0:c770ad7363c8 305 * On Exit:
j3 0:c770ad7363c8 306 * @param[out] data - data buffer now contains data read
j3 0:c770ad7363c8 307 * from shadow registers
j3 0:c770ad7363c8 308 * @return return value = 0 on success, non-0 on failure
j3 0:c770ad7363c8 309 *
j3 0:c770ad7363c8 310 * Example:
j3 0:c770ad7363c8 311 * @code
j3 0:c770ad7363c8 312 *
j3 2:88c168ddc145 313 * //declare mux object
j3 2:88c168ddc145 314 * Max14661 mux(D14, D15, MAX14661_I2C_ADRS0);
j3 0:c770ad7363c8 315 *
j3 0:c770ad7363c8 316 * uint16_t rtn_val;
j3 0:c770ad7363c8 317 * uint8_t data[4];
j3 0:c770ad7363c8 318 *
j3 0:c770ad7363c8 319 * //read shadow registers
j3 0:c770ad7363c8 320 * rtn_val = mux.rd_shadow_registers(data);
j3 0:c770ad7363c8 321 *
j3 0:c770ad7363c8 322 * @endcode
j3 4:45fa0192f66d 323 **************************************************************/
j3 0:c770ad7363c8 324 uint16_t rd_shadow_registers(uint8_t* data);
j3 0:c770ad7363c8 325 };
j3 0:c770ad7363c8 326
j3 0:c770ad7363c8 327
j3 0:c770ad7363c8 328 #endif /* MAX14661_H*/