Wilson Tang / max14724

8:4 Matrix Multiplexer

Fork of max14661 by Maxim Integrated

This is an untested driver for the MAX14724.

max14661.h@7:1d4e59ec0fba, 2015-03-12 (annotated)

Committer:
j3
Date:
Thu Mar 12 19:15:22 2015 +0000
Revision:
7:1d4e59ec0fba
Parent:
5:58f3bbd30777
Child:
8:44257d87fa9e
Updated to version 1.0 for initial release

Who changed what in which revision?

UserRevisionLine numberNew contents of line
j3 0:c770ad7363c8 1 /******************************************************************//**
j3 0:c770ad7363c8 2 * @file max14661.h
j3 0:c770ad7363c8 3 *
j3 0:c770ad7363c8 4 * @author Justin Jordan
j3 0:c770ad7363c8 5 *
j3 7:1d4e59ec0fba 6 * @version 1.0
j3 0:c770ad7363c8 7 *
j3 0:c770ad7363c8 8 * Started: 11NOV14
j3 0:c770ad7363c8 9 *
j3 0:c770ad7363c8 10 * Updated:
j3 0:c770ad7363c8 11 *
j3 0:c770ad7363c8 12 * @brief Header file for MAX14661 class
j3 0:c770ad7363c8 13 *
j3 0:c770ad7363c8 14 ***********************************************************************
j3 0:c770ad7363c8 15 *
j3 0:c770ad7363c8 16 * @copyright
j3 0:c770ad7363c8 17 * Copyright (C) 2013 Maxim Integrated Products, Inc., All Rights Reserved.
j3 0:c770ad7363c8 18 *
j3 0:c770ad7363c8 19 * Permission is hereby granted, free of charge, to any person obtaining a
j3 0:c770ad7363c8 20 * copy of this software and associated documentation files (the "Software"),
j3 0:c770ad7363c8 21 * to deal in the Software without restriction, including without limitation
j3 0:c770ad7363c8 22 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
j3 0:c770ad7363c8 23 * and/or sell copies of the Software, and to permit persons to whom the
j3 0:c770ad7363c8 24 * Software is furnished to do so, subject to the following conditions:
j3 0:c770ad7363c8 25 *
j3 0:c770ad7363c8 26 * The above copyright notice and this permission notice shall be included
j3 0:c770ad7363c8 27 * in all copies or substantial portions of the Software.
j3 0:c770ad7363c8 28 *
j3 0:c770ad7363c8 29 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
j3 0:c770ad7363c8 30 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
j3 0:c770ad7363c8 31 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
j3 0:c770ad7363c8 32 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
j3 0:c770ad7363c8 33 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
j3 0:c770ad7363c8 34 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
j3 0:c770ad7363c8 35 * OTHER DEALINGS IN THE SOFTWARE.
j3 0:c770ad7363c8 36 *
j3 0:c770ad7363c8 37 * Except as contained in this notice, the name of Maxim Integrated
j3 0:c770ad7363c8 38 * Products, Inc. shall not be used except as stated in the Maxim Integrated
j3 0:c770ad7363c8 39 * Products, Inc. Branding Policy.
j3 0:c770ad7363c8 40 *
j3 0:c770ad7363c8 41 * The mere transfer of this software does not imply any licenses
j3 0:c770ad7363c8 42 * of trade secrets, proprietary technology, copyrights, patents,
j3 0:c770ad7363c8 43 * trademarks, maskwork rights, or any other form of intellectual
j3 0:c770ad7363c8 44 * property whatsoever. Maxim Integrated Products, Inc. retains all
j3 0:c770ad7363c8 45 * ownership rights.
j3 0:c770ad7363c8 46 **********************************************************************/
j3 0:c770ad7363c8 47
j3 0:c770ad7363c8 48
j3 0:c770ad7363c8 49 #ifndef MAX14661_H
j3 0:c770ad7363c8 50 #define MAX14661_H
j3 0:c770ad7363c8 51
j3 0:c770ad7363c8 52
j3 0:c770ad7363c8 53 #include "mbed.h"
j3 0:c770ad7363c8 54
j3 0:c770ad7363c8 55
j3 5:58f3bbd30777 56 /**
j3 5:58f3bbd30777 57 * max14661_i2c_adrs_t - enumerated MAX14661 I2C Addresses
j3 5:58f3bbd30777 58 */
j3 0:c770ad7363c8 59 typedef enum
j3 0:c770ad7363c8 60 {
j3 0:c770ad7363c8 61 MAX14661_I2C_ADRS0 = 0x4C,
j3 0:c770ad7363c8 62 MAX14661_I2C_ADRS1,
j3 0:c770ad7363c8 63 MAX14661_I2C_ADRS2,
j3 0:c770ad7363c8 64 MAX14661_I2C_ADRS3
j3 0:c770ad7363c8 65 }max14661_i2c_adrs_t;
j3 0:c770ad7363c8 66
j3 0:c770ad7363c8 67
j3 5:58f3bbd30777 68 /**
j3 5:58f3bbd30777 69 * max14661_regs_t - enumerated MAX14661 register addresses
j3 5:58f3bbd30777 70 */
j3 0:c770ad7363c8 71 typedef enum
j3 0:c770ad7363c8 72 {
j3 0:c770ad7363c8 73 DIR0, //Switches 8A–1A direct read/write access
j3 0:c770ad7363c8 74 DIR1, //Switches 16A–9A direct read/write access
j3 0:c770ad7363c8 75 DIR2, //Switches 8B–1B direct read/write access
j3 0:c770ad7363c8 76 DIR3, //Switches 16B–9B direct read/write access
j3 0:c770ad7363c8 77 SHDW0 = 0x10, //Switches 8A–1A shadow read/write access
j3 0:c770ad7363c8 78 SHDW1, //Switches 16A–9A shadow read/write access
j3 0:c770ad7363c8 79 SHDW2, //Switches 8B–1B shadow read/write access
j3 0:c770ad7363c8 80 SHDW3, //Switches 16B–9B shadow read/write access
j3 0:c770ad7363c8 81 CMD_A, //Set mux A command (reads 0x00)
j3 0:c770ad7363c8 82 CMD_B //Set mux B command (reads 0x00)
j3 0:c770ad7363c8 83 }max14661_regs_t;
j3 0:c770ad7363c8 84
j3 0:c770ad7363c8 85
j3 5:58f3bbd30777 86 /**
j3 5:58f3bbd30777 87 * max14661_cmds_t - enumerated MAX14661 commands
j3 5:58f3bbd30777 88 */
j3 0:c770ad7363c8 89 typedef enum
j3 0:c770ad7363c8 90 {
j3 0:c770ad7363c8 91 ENABLE_SW01, //enables sw1 on bank only
j3 0:c770ad7363c8 92 ENABLE_SW02, //enables sw2 on bank only
j3 0:c770ad7363c8 93 ENABLE_SW03, //enables sw3 on bank only
j3 0:c770ad7363c8 94 ENABLE_SW04, //enables sw4 on bank only
j3 0:c770ad7363c8 95 ENABLE_SW05, //enables sw5 on bank only
j3 0:c770ad7363c8 96 ENABLE_SW06, //enables sw6 on bank only
j3 0:c770ad7363c8 97 ENABLE_SW07, //enables sw7 on bank only
j3 0:c770ad7363c8 98 ENABLE_SW08, //enables sw8 on bank only
j3 0:c770ad7363c8 99 ENABLE_SW09, //enables sw9 on bank only
j3 0:c770ad7363c8 100 ENABLE_SW10, //enables sw10 on bank only
j3 0:c770ad7363c8 101 ENABLE_SW11, //enables sw11 on bank only
j3 0:c770ad7363c8 102 ENABLE_SW12, //enables sw12 on bank only
j3 0:c770ad7363c8 103 ENABLE_SW13, //enables sw13 on bank only
j3 0:c770ad7363c8 104 ENABLE_SW14, //enables sw14 on bank only
j3 0:c770ad7363c8 105 ENABLE_SW15, //enables sw15 on bank only
j3 0:c770ad7363c8 106 ENABLE_SW16, //enables sw16 on bank only
j3 0:c770ad7363c8 107 DISABLE_BANK, //opens all switches on bank
j3 4:45fa0192f66d 108 COPY_SHADOW, //copies both shadow registers for bank
j3 0:c770ad7363c8 109 NO_CHANGE,
j3 0:c770ad7363c8 110 }max14661_cmds_t;
j3 0:c770ad7363c8 111
j3 0:c770ad7363c8 112
j3 5:58f3bbd30777 113 /**
j3 5:58f3bbd30777 114 * max14661_sw_t - enumerated MAX14661 switch bitmasks
j3 5:58f3bbd30777 115 */
j3 0:c770ad7363c8 116 typedef enum
j3 0:c770ad7363c8 117 {
j3 0:c770ad7363c8 118 SW01 = (1 << 0),
j3 0:c770ad7363c8 119 SW02 = (1 << 1),
j3 0:c770ad7363c8 120 SW03 = (1 << 2),
j3 0:c770ad7363c8 121 SW04 = (1 << 3),
j3 0:c770ad7363c8 122 SW05 = (1 << 4),
j3 0:c770ad7363c8 123 SW06 = (1 << 5),
j3 0:c770ad7363c8 124 SW07 = (1 << 6),
j3 0:c770ad7363c8 125 SW08 = (1 << 7),
j3 0:c770ad7363c8 126 SW09 = (1 << 8),
j3 0:c770ad7363c8 127 SW10 = (1 << 9),
j3 0:c770ad7363c8 128 SW11 = (1 << 10),
j3 0:c770ad7363c8 129 SW12 = (1 << 11),
j3 0:c770ad7363c8 130 SW13 = (1 << 12),
j3 0:c770ad7363c8 131 SW14 = (1 << 13),
j3 0:c770ad7363c8 132 SW15 = (1 << 14),
j3 0:c770ad7363c8 133 SW16 = (1 << 15)
j3 0:c770ad7363c8 134 }max14661_sw_t;
j3 0:c770ad7363c8 135
j3 0:c770ad7363c8 136
j3 0:c770ad7363c8 137 /******************************************************************//**
j3 0:c770ad7363c8 138 * Max14661 Class
j3 0:c770ad7363c8 139 **********************************************************************/
j3 2:88c168ddc145 140 class Max14661 : public I2C
j3 0:c770ad7363c8 141 {
j3 0:c770ad7363c8 142 uint8_t w_adrs, r_adrs;
j3 0:c770ad7363c8 143
j3 0:c770ad7363c8 144 public:
j3 0:c770ad7363c8 145 /**********************************************************//**
j3 1:c1fdfe4c2354 146 * Constructor for Max14661 Class
j3 0:c770ad7363c8 147 *
j3 0:c770ad7363c8 148 * On Entry:
j3 2:88c168ddc145 149 * @param[in] sda - sda pin of I2C bus
j3 2:88c168ddc145 150 * @param[in] scl - scl pin of I2C bus
j3 0:c770ad7363c8 151 * @param[in] i2c_adrs - 7-bit slave address of MAX14661
j3 0:c770ad7363c8 152 *
j3 0:c770ad7363c8 153 * On Exit:
j3 0:c770ad7363c8 154 * @return none
j3 0:c770ad7363c8 155 *
j3 0:c770ad7363c8 156 * Example:
j3 0:c770ad7363c8 157 * @code
j3 0:c770ad7363c8 158 *
j3 2:88c168ddc145 159 * //declare mux object
j3 2:88c168ddc145 160 * Max14661 mux(D14, D15, MAX14661_I2C_ADRS0);
j3 0:c770ad7363c8 161 *
j3 0:c770ad7363c8 162 * @endcode
j3 0:c770ad7363c8 163 **************************************************************/
j3 2:88c168ddc145 164 Max14661(PinName sda, PinName scl, max14661_i2c_adrs_t i2c_adrs);
j3 0:c770ad7363c8 165
j3 4:45fa0192f66d 166
j3 0:c770ad7363c8 167 /******************************************************************//**
j3 0:c770ad7363c8 168 * Writes given commands to CMD_A and CMD_B
j3 0:c770ad7363c8 169 *
j3 0:c770ad7363c8 170 * On Entry:
j3 0:c770ad7363c8 171 * @param[in] cmdA - command for CMD_A
j3 0:c770ad7363c8 172 * @param[in] cmdB - command for CMD_B
j3 0:c770ad7363c8 173 *
j3 0:c770ad7363c8 174 * On Exit:
j3 0:c770ad7363c8 175 * @return return value = 0 on success, non-0 on failure
j3 0:c770ad7363c8 176 *
j3 0:c770ad7363c8 177 * Example:
j3 0:c770ad7363c8 178 * @code
j3 0:c770ad7363c8 179 *
j3 2:88c168ddc145 180 * //declare mux object
j3 2:88c168ddc145 181 * Max14661 mux(D14, D15, MAX14661_I2C_ADRS0);
j3 0:c770ad7363c8 182 *
j3 0:c770ad7363c8 183 * uint16_t rtn_val;
j3 0:c770ad7363c8 184 *
j3 0:c770ad7363c8 185 * rtn_val = mux.wrt_cmd_registers(DISABLE_BANK, DISABLE_BANK);
j3 0:c770ad7363c8 186 *
j3 0:c770ad7363c8 187 * @endcode
j3 0:c770ad7363c8 188 **********************************************************************/
j3 4:45fa0192f66d 189 uint16_t wrt_cmd_registers(max14661_cmds_t cmdA, max14661_cmds_t cmdB);
j3 4:45fa0192f66d 190
j3 4:45fa0192f66d 191
j3 0:c770ad7363c8 192 /******************************************************************//**
j3 4:45fa0192f66d 193 * Writes bankA and bankB to coresponding shadow registers
j3 0:c770ad7363c8 194 *
j3 0:c770ad7363c8 195 * On Entry:
j3 4:45fa0192f66d 196 * @param[in] bankA - binary representation of switch states
j3 4:45fa0192f66d 197 * @param[in] bankB - binary representation of switch states
j3 0:c770ad7363c8 198 *
j3 0:c770ad7363c8 199 * On Exit:
j3 0:c770ad7363c8 200 * @return return value = 0 on success, non-0 on failure
j3 0:c770ad7363c8 201 *
j3 0:c770ad7363c8 202 * Example:
j3 0:c770ad7363c8 203 * @code
j3 0:c770ad7363c8 204 *
j3 2:88c168ddc145 205 * //declare mux object
j3 2:88c168ddc145 206 * Max14661 mux(D14, D15, MAX14661_I2C_ADRS0);
j3 0:c770ad7363c8 207 *
j3 4:45fa0192f66d 208 * uint16_t bankA = (SW12 | SW02); //example only
j3 4:45fa0192f66d 209 * uint16_t bankB = (SW11 | SW01);
j3 0:c770ad7363c8 210 * uint16_t rtn_val;
j3 0:c770ad7363c8 211 *
j3 0:c770ad7363c8 212 * //wite shadow registers
j3 4:45fa0192f66d 213 * rtn_val = mux.wrt_shadow_registers(bankA, bankB);
j3 0:c770ad7363c8 214 *
j3 0:c770ad7363c8 215 * @endcode
j3 0:c770ad7363c8 216 **********************************************************************/
j3 4:45fa0192f66d 217 uint16_t wrt_shadow_registers(uint16_t bankA, uint16_t bankB);
j3 4:45fa0192f66d 218
j3 4:45fa0192f66d 219
j3 0:c770ad7363c8 220 /******************************************************************//**
j3 4:45fa0192f66d 221 * Writes bankA and bankB to coresponding direct access registers
j3 0:c770ad7363c8 222 *
j3 0:c770ad7363c8 223 * On Entry:
j3 4:45fa0192f66d 224 * @param[in] bankA - binary representation of switch states
j3 4:45fa0192f66d 225 * @param[in] bankB - binary representation of switch states
j3 0:c770ad7363c8 226 *
j3 0:c770ad7363c8 227 * On Exit:
j3 0:c770ad7363c8 228 * @return return value = 0 on success, non-0 on failure
j3 0:c770ad7363c8 229 *
j3 0:c770ad7363c8 230 * Example:
j3 1:c1fdfe4c2354 231 * @code
j3 0:c770ad7363c8 232 *
j3 2:88c168ddc145 233 * //declare mux object
j3 2:88c168ddc145 234 * Max14661 mux(D14, D15, MAX14661_I2C_ADRS0);
j3 0:c770ad7363c8 235 *
j3 4:45fa0192f66d 236 * uint16_t bankA = (SW12 | SW02); //example only
j3 4:45fa0192f66d 237 * uint16_t bankB = (SW11 | SW01);
j3 0:c770ad7363c8 238 * uint16_t rtn_val;
j3 0:c770ad7363c8 239 *
j3 0:c770ad7363c8 240 * //wite shadow registers
j3 4:45fa0192f66d 241 * rtn_val = mux.wrt_dir_registers(bankA, bankB);
j3 0:c770ad7363c8 242 *
j3 0:c770ad7363c8 243 * @endcode
j3 0:c770ad7363c8 244 **********************************************************************/
j3 4:45fa0192f66d 245 uint16_t wrt_dir_registers(uint16_t bankA, uint16_t bankB);
j3 4:45fa0192f66d 246
j3 4:45fa0192f66d 247
j3 4:45fa0192f66d 248 /******************************************************************//**
j3 4:45fa0192f66d 249 * Writes bankA and bankB to coresponding shadow register and then
j3 4:45fa0192f66d 250 * issues copy command for both banks
j3 4:45fa0192f66d 251 *
j3 4:45fa0192f66d 252 * On Entry:
j3 4:45fa0192f66d 253 * @param[in] bankA - binary representation of switch states
j3 4:45fa0192f66d 254 * @param[in] bankB - binary representation of switch states
j3 4:45fa0192f66d 255 *
j3 4:45fa0192f66d 256 * On Exit:
j3 4:45fa0192f66d 257 * @return return value = 0 on success, non-0 on failure
j3 4:45fa0192f66d 258 *
j3 4:45fa0192f66d 259 * Example:
j3 4:45fa0192f66d 260 * @code
j3 4:45fa0192f66d 261 *
j3 4:45fa0192f66d 262 * //declare mux object
j3 4:45fa0192f66d 263 * Max14661 mux(D14, D15, MAX14661_I2C_ADRS0);
j3 4:45fa0192f66d 264 *
j3 4:45fa0192f66d 265 * uint16_t bankA = (SW12 | SW02); //example only
j3 4:45fa0192f66d 266 * uint16_t bankB = (SW11 | SW01);
j3 4:45fa0192f66d 267 * uint16_t rtn_val;
j3 4:45fa0192f66d 268 *
j3 4:45fa0192f66d 269 * //wite shadow registers
j3 4:45fa0192f66d 270 * rtn_val = mux.set_switches(bankA, bankB);
j3 4:45fa0192f66d 271 *
j3 4:45fa0192f66d 272 * @endcode
j3 4:45fa0192f66d 273 **********************************************************************/
j3 4:45fa0192f66d 274 uint16_t set_switches(uint16_t bankA, uint16_t bankB);
j3 4:45fa0192f66d 275
j3 4:45fa0192f66d 276
j3 0:c770ad7363c8 277 /**********************************************************//**
j3 0:c770ad7363c8 278 * Reads data from direct access registers starting at DIR0 and
j3 0:c770ad7363c8 279 * stores it in byte array pointed at by 'data'
j3 0:c770ad7363c8 280 *
j3 0:c770ad7363c8 281 * On Entry:
j3 0:c770ad7363c8 282 * @param[in] data - pointer to byte array for storing data
j3 0:c770ad7363c8 283 *
j3 0:c770ad7363c8 284 * On Exit:
j3 0:c770ad7363c8 285 * @param[out] data - data buffer now contains data read
j3 0:c770ad7363c8 286 * from dir registers
j3 0:c770ad7363c8 287 * @return return value = 0 on success, non-0 on failure
j3 0:c770ad7363c8 288 *
j3 0:c770ad7363c8 289 * Example:
j3 0:c770ad7363c8 290 * @code
j3 0:c770ad7363c8 291 *
j3 2:88c168ddc145 292 * //declare mux object
j3 2:88c168ddc145 293 * Max14661 mux(D14, D15, MAX14661_I2C_ADRS0);
j3 0:c770ad7363c8 294 *
j3 0:c770ad7363c8 295 * uint16_t rtn_val;
j3 0:c770ad7363c8 296 * uint8_t data[4];
j3 0:c770ad7363c8 297 *
j3 0:c770ad7363c8 298 * //read direct access registers
j3 0:c770ad7363c8 299 * rtn_val = mux.rd_dir_registers(data);
j3 0:c770ad7363c8 300 *
j3 0:c770ad7363c8 301 * @endcode
j3 0:c770ad7363c8 302 **********************************************************************/
j3 0:c770ad7363c8 303 uint16_t rd_dir_registers(uint8_t* data);
j3 4:45fa0192f66d 304
j3 4:45fa0192f66d 305
j3 0:c770ad7363c8 306 /**********************************************************//**
j3 0:c770ad7363c8 307 * Reads data from shadow registers starting at SHDW0 and stores
j3 0:c770ad7363c8 308 * it in byte array pointed at by 'data'
j3 0:c770ad7363c8 309 *
j3 0:c770ad7363c8 310 * On Entry:
j3 0:c770ad7363c8 311 * @param[in] data - pointer to byte array for storing data
j3 0:c770ad7363c8 312 *
j3 0:c770ad7363c8 313 * On Exit:
j3 0:c770ad7363c8 314 * @param[out] data - data buffer now contains data read
j3 0:c770ad7363c8 315 * from shadow registers
j3 0:c770ad7363c8 316 * @return return value = 0 on success, non-0 on failure
j3 0:c770ad7363c8 317 *
j3 0:c770ad7363c8 318 * Example:
j3 0:c770ad7363c8 319 * @code
j3 0:c770ad7363c8 320 *
j3 2:88c168ddc145 321 * //declare mux object
j3 2:88c168ddc145 322 * Max14661 mux(D14, D15, MAX14661_I2C_ADRS0);
j3 0:c770ad7363c8 323 *
j3 0:c770ad7363c8 324 * uint16_t rtn_val;
j3 0:c770ad7363c8 325 * uint8_t data[4];
j3 0:c770ad7363c8 326 *
j3 0:c770ad7363c8 327 * //read shadow registers
j3 0:c770ad7363c8 328 * rtn_val = mux.rd_shadow_registers(data);
j3 0:c770ad7363c8 329 *
j3 0:c770ad7363c8 330 * @endcode
j3 4:45fa0192f66d 331 **************************************************************/
j3 0:c770ad7363c8 332 uint16_t rd_shadow_registers(uint8_t* data);
j3 0:c770ad7363c8 333 };
j3 0:c770ad7363c8 334
j3 0:c770ad7363c8 335
j3 0:c770ad7363c8 336 #endif /* MAX14661_H*/