wimbeaumont Project / adc_ad9249

sw ADC SPI interface for the SOLID Slow control beta!!

Dependents:   SPItest sscm

AD9249.cpp@2:1fb81137d906, 2015-10-23 (annotated)

Committer:
wbeaumont
Date:
Fri Oct 23 11:22:44 2015 +0000
Revision:
2:1fb81137d906
Parent:
1:01459a6ab296 
production version archiving

Who changed what in which revision?

UserRevisionLine numberNew contents of line
wbeaumont 0:9efb460e962b 1 #include <mbed.h>
wbeaumont 2:1fb81137d906 2 /*
wbeaumont 2:1fb81137d906 3 * (C) Wim Beaumont Univeristeit Antwerpen 2014 , 2015
wbeaumont 2:1fb81137d906 4 */
wbeaumont 0:9efb460e962b 5
wbeaumont 0:9efb460e962b 6 #include "AD9249.h"
wbeaumont 0:9efb460e962b 7 #include "SWSPI_BI.h"
wbeaumont 0:9efb460e962b 8
wbeaumont 1:01459a6ab296 9
wbeaumont 1:01459a6ab296 10 #define AD9249_SRC_VER "1.22"
wbeaumont 1:01459a6ab296 11
wbeaumont 0:9efb460e962b 12 #define CS_POL 1
wbeaumont 0:9efb460e962b 13 #define NCS_POL 0
wbeaumont 0:9efb460e962b 14 /*
wbeaumont 0:9efb460e962b 15 const u16 AD9249::configreg= 0x0;
wbeaumont 0:9efb460e962b 16 const u16 AD9249::chip_id_reg= 0x1;
wbeaumont 0:9efb460e962b 17 const u16 AD9249::chip_grade_reg= 0x2;
wbeaumont 0:9efb460e962b 18 // const u16 AD9249::unused_reg= { 0x3, 0x07, 0xA, 0xE, 0xF ,0x11, 0x12,0x13, 0x17, 0x1D, 0x1E, 0x1F,0x20 };
wbeaumont 0:9efb460e962b 19 const u16 AD9249::dev_index2_reg= 0x4;
wbeaumont 0:9efb460e962b 20 const u16 AD9249::dev_index1_reg= 0x4;
wbeaumont 0:9efb460e962b 21 const u16 AD9249::transfer_reg= 0xFF;
wbeaumont 0:9efb460e962b 22 const u16 AD9249::power_mode_reg= 0x8;
wbeaumont 0:9efb460e962b 23 const u16 AD9249::clock_gobal_reg= 0x9;
wbeaumont 0:9efb460e962b 24 const u16 AD9249::clock_divide_reg= 0xB;
wbeaumont 0:9efb460e962b 25 const u16 AD9249::enhancement_ctr_reg= 0xC;
wbeaumont 0:9efb460e962b 26 const u16 AD9249::test_mode_reg= 0xD;
wbeaumont 0:9efb460e962b 27 const u16 AD9249::offset_adj_reg= 0x10;
wbeaumont 0:9efb460e962b 28 const u16 AD9249::output_mode_reg= 0x14;
wbeaumont 0:9efb460e962b 29 const u16 AD9249::output_adj_reg= 0x15;
wbeaumont 0:9efb460e962b 30 const u16 AD9249::output_phase_reg= 0x16;
wbeaumont 0:9efb460e962b 31 const u16 AD9249::vref_reg= 0x18;
wbeaumont 0:9efb460e962b 32 const u16 AD9249::usserpatt1_LSB_reg= 0x19;
wbeaumont 0:9efb460e962b 33 const u16 AD9249::usserpatt1_MSB_reg= 0x1A;
wbeaumont 0:9efb460e962b 34 const u16 AD9249::usserpatt2_LSB_reg= 0x1B;
wbeaumont 0:9efb460e962b 35 const u16 AD9249::usserpatt2_MSB_reg= 0x1C;
wbeaumont 0:9efb460e962b 36 const u16 AD9249::serial_out_cntr_reg= 0x21;
wbeaumont 0:9efb460e962b 37 const u16 AD9249::serial_status_reg= 0x22;
wbeaumont 0:9efb460e962b 38 const u16 AD9249::sample_rate_reg= 0x100;
wbeaumont 0:9efb460e962b 39 const u16 AD9249::user_io_ctr2_reg= 0x101;
wbeaumont 0:9efb460e962b 40 const u16 AD9249::user_io_ctr3_reg= 0x102;
wbeaumont 0:9efb460e962b 41 const u16 AD9249::sync_reg= 0x109;
wbeaumont 0:9efb460e962b 42 */
wbeaumont 0:9efb460e962b 43
wbeaumont 0:9efb460e962b 44
wbeaumont 1:01459a6ab296 45 AD9249::AD9249( SWSPI_BI* spi_dev, DigitalOut* csb_pin):getVersion( AD9249_HDR_VER,AD9249_SRC_VER, __TIME__, __DATE__) {
wbeaumont 0:9efb460e962b 46 spi=spi_dev;csb=csb_pin;
wbeaumont 0:9efb460e962b 47 }
wbeaumont 0:9efb460e962b 48
wbeaumont 0:9efb460e962b 49
wbeaumont 0:9efb460e962b 50 AD9249::u32 AD9249::spi_cycle( u16 reg , bool rw , u16 nrbytes, u32 data){
wbeaumont 0:9efb460e962b 51 // format instruction
wbeaumont 0:9efb460e962b 52 u32 read =0;
wbeaumont 0:9efb460e962b 53 reg = 0x1FFF & reg;
wbeaumont 0:9efb460e962b 54 if (rw) reg |=0x8000;
wbeaumont 0:9efb460e962b 55 if (nrbytes > 2) return 0; // this function doesn't support stream
wbeaumont 0:9efb460e962b 56 u32 stnrbytes = (nrbytes-1);
wbeaumont 0:9efb460e962b 57 stnrbytes =stnrbytes <<13;
wbeaumont 0:9efb460e962b 58 reg|=stnrbytes; // reg is now the instruction
wbeaumont 0:9efb460e962b 59 spi->format(16,0); // should make sure the sclk is high
wbeaumont 0:9efb460e962b 60 printf("send %04X \n\r",reg);
wbeaumont 0:9efb460e962b 61
wbeaumont 0:9efb460e962b 62
wbeaumont 0:9efb460e962b 63
wbeaumont 0:9efb460e962b 64 if (rw) {
wbeaumont 0:9efb460e962b 65 spi->write(reg, csb , false ,CS_POL,true );
wbeaumont 0:9efb460e962b 66 spi->format((nrbytes)*8 ,0);
wbeaumont 0:9efb460e962b 67 read=spi->read(csb , true ,CS_POL );
wbeaumont 0:9efb460e962b 68 }
wbeaumont 0:9efb460e962b 69 else{
wbeaumont 0:9efb460e962b 70 spi->write(reg, csb , false ,CS_POL );
wbeaumont 0:9efb460e962b 71 spi->format((nrbytes)*8 ,0);
wbeaumont 0:9efb460e962b 72 spi->write(data, csb , true ,CS_POL );
wbeaumont 0:9efb460e962b 73
wbeaumont 0:9efb460e962b 74 }
wbeaumont 0:9efb460e962b 75
wbeaumont 0:9efb460e962b 76 return read;
wbeaumont 0:9efb460e962b 77 }
wbeaumont 0:9efb460e962b 78
wbeaumont 0:9efb460e962b 79
wbeaumont 0:9efb460e962b 80 bool AD9249::getDevInfo(u8&chipid,u8& grade ,u16 &rb ){
wbeaumont 0:9efb460e962b 81 u32 data=spi_cycle( chip_grade_reg, true , 2 , 0);
wbeaumont 0:9efb460e962b 82 rb=data;
wbeaumont 0:9efb460e962b 83 chipid= data & 0XFF;
wbeaumont 0:9efb460e962b 84 grade= (data >> 8) & 0xFF;
wbeaumont 0:9efb460e962b 85 return true;
wbeaumont 0:9efb460e962b 86 }
wbeaumont 0:9efb460e962b 87
wbeaumont 0:9efb460e962b 88 bool AD9249::getDevId(u8&chipid ){
wbeaumont 0:9efb460e962b 89 bool rv=readReg8(chip_id_reg,chipid);
wbeaumont 0:9efb460e962b 90 return rv;
wbeaumont 0:9efb460e962b 91 }
wbeaumont 0:9efb460e962b 92 bool AD9249::getGrade(u8&chipid ){
wbeaumont 0:9efb460e962b 93 bool rv=readReg8(chip_grade_reg,chipid);
wbeaumont 0:9efb460e962b 94 return rv;
wbeaumont 0:9efb460e962b 95 }
wbeaumont 0:9efb460e962b 96
wbeaumont 0:9efb460e962b 97 bool AD9249::readReg16( u16 regaddr, u16& data){
wbeaumont 0:9efb460e962b 98 u32 datai=spi_cycle( regaddr , true , 2 , 0);
wbeaumont 0:9efb460e962b 99 data=(u16)( datai & 0XFFFF);
wbeaumont 0:9efb460e962b 100 return true;
wbeaumont 0:9efb460e962b 101 }
wbeaumont 0:9efb460e962b 102
wbeaumont 0:9efb460e962b 103 bool AD9249::readReg8 ( u16 regaddr, u8& data){
wbeaumont 0:9efb460e962b 104 u32 datai=spi_cycle( regaddr, true , 1 , 0);
wbeaumont 0:9efb460e962b 105 data=(u8)( datai & 0XFF);
wbeaumont 0:9efb460e962b 106 return true;
wbeaumont 0:9efb460e962b 107 }
wbeaumont 0:9efb460e962b 108
wbeaumont 0:9efb460e962b 109
wbeaumont 0:9efb460e962b 110
wbeaumont 0:9efb460e962b 111 bool AD9249::setReg16( u16 regaddr, u16 data){
wbeaumont 0:9efb460e962b 112 u32 datai=spi_cycle( regaddr, false , 2 , (u32)data);
wbeaumont 0:9efb460e962b 113 return true;
wbeaumont 0:9efb460e962b 114 }
wbeaumont 0:9efb460e962b 115
wbeaumont 0:9efb460e962b 116 bool AD9249::setReg8 ( u16 regaddr, u8 data){
wbeaumont 0:9efb460e962b 117 u32 datai=spi_cycle( regaddr, false , 1 , (u32)data);
wbeaumont 0:9efb460e962b 118 return true;
wbeaumont 0:9efb460e962b 119 }
wbeaumont 0:9efb460e962b 120
wbeaumont 0:9efb460e962b 121
wbeaumont 0:9efb460e962b 122 bool AD9249::setPattern1(u16 pattern){
wbeaumont 0:9efb460e962b 123 bool rv=setReg16( usserpatt1_MSB_reg,pattern);
wbeaumont 0:9efb460e962b 124 return rv;
wbeaumont 0:9efb460e962b 125 }
wbeaumont 0:9efb460e962b 126 bool AD9249::setPattern2(u16 pattern){
wbeaumont 0:9efb460e962b 127 bool rv=setReg16( usserpatt2_MSB_reg,pattern);
wbeaumont 0:9efb460e962b 128 return rv;
wbeaumont 0:9efb460e962b 129 }
wbeaumont 0:9efb460e962b 130
wbeaumont 0:9efb460e962b 131 bool AD9249::readPattern1(u16& pattern){
wbeaumont 0:9efb460e962b 132 bool rv= readReg16( usserpatt1_MSB_reg,pattern);
wbeaumont 0:9efb460e962b 133 return rv;
wbeaumont 0:9efb460e962b 134 }
wbeaumont 0:9efb460e962b 135 bool AD9249::readPattern2(u16& pattern){
wbeaumont 0:9efb460e962b 136 bool rv= readReg16( usserpatt2_MSB_reg,pattern);
wbeaumont 0:9efb460e962b 137 return rv;
wbeaumont 0:9efb460e962b 138
wbeaumont 0:9efb460e962b 139 }
wbeaumont 0:9efb460e962b 140
wbeaumont 1:01459a6ab296 141 void AD9249::init1(){}
wbeaumont 1:01459a6ab296 142 void AD9249::init2(){}