wimbeaumont Project / adc_ad9249

sw ADC SPI interface for the SOLID Slow control beta!!

Dependents:   SPItest sscm

AD9249.cpp@1:01459a6ab296, 2014-10-05 (annotated)

Committer:
wbeaumont
Date:
Sun Oct 05 17:10:44 2014 +0000
Revision:
1:01459a6ab296
Parent:
0:9efb460e962b
Child:
2:1fb81137d906
version class added

Who changed what in which revision?

UserRevisionLine numberNew contents of line
wbeaumont 0:9efb460e962b 1 #include <mbed.h>
wbeaumont 0:9efb460e962b 2
wbeaumont 0:9efb460e962b 3 #include "AD9249.h"
wbeaumont 0:9efb460e962b 4 #include "SWSPI_BI.h"
wbeaumont 0:9efb460e962b 5
wbeaumont 1:01459a6ab296 6
wbeaumont 1:01459a6ab296 7 #define AD9249_SRC_VER "1.22"
wbeaumont 1:01459a6ab296 8
wbeaumont 0:9efb460e962b 9 #define CS_POL 1
wbeaumont 0:9efb460e962b 10 #define NCS_POL 0
wbeaumont 0:9efb460e962b 11 /*
wbeaumont 0:9efb460e962b 12 const u16 AD9249::configreg= 0x0;
wbeaumont 0:9efb460e962b 13 const u16 AD9249::chip_id_reg= 0x1;
wbeaumont 0:9efb460e962b 14 const u16 AD9249::chip_grade_reg= 0x2;
wbeaumont 0:9efb460e962b 15 // const u16 AD9249::unused_reg= { 0x3, 0x07, 0xA, 0xE, 0xF ,0x11, 0x12,0x13, 0x17, 0x1D, 0x1E, 0x1F,0x20 };
wbeaumont 0:9efb460e962b 16 const u16 AD9249::dev_index2_reg= 0x4;
wbeaumont 0:9efb460e962b 17 const u16 AD9249::dev_index1_reg= 0x4;
wbeaumont 0:9efb460e962b 18 const u16 AD9249::transfer_reg= 0xFF;
wbeaumont 0:9efb460e962b 19 const u16 AD9249::power_mode_reg= 0x8;
wbeaumont 0:9efb460e962b 20 const u16 AD9249::clock_gobal_reg= 0x9;
wbeaumont 0:9efb460e962b 21 const u16 AD9249::clock_divide_reg= 0xB;
wbeaumont 0:9efb460e962b 22 const u16 AD9249::enhancement_ctr_reg= 0xC;
wbeaumont 0:9efb460e962b 23 const u16 AD9249::test_mode_reg= 0xD;
wbeaumont 0:9efb460e962b 24 const u16 AD9249::offset_adj_reg= 0x10;
wbeaumont 0:9efb460e962b 25 const u16 AD9249::output_mode_reg= 0x14;
wbeaumont 0:9efb460e962b 26 const u16 AD9249::output_adj_reg= 0x15;
wbeaumont 0:9efb460e962b 27 const u16 AD9249::output_phase_reg= 0x16;
wbeaumont 0:9efb460e962b 28 const u16 AD9249::vref_reg= 0x18;
wbeaumont 0:9efb460e962b 29 const u16 AD9249::usserpatt1_LSB_reg= 0x19;
wbeaumont 0:9efb460e962b 30 const u16 AD9249::usserpatt1_MSB_reg= 0x1A;
wbeaumont 0:9efb460e962b 31 const u16 AD9249::usserpatt2_LSB_reg= 0x1B;
wbeaumont 0:9efb460e962b 32 const u16 AD9249::usserpatt2_MSB_reg= 0x1C;
wbeaumont 0:9efb460e962b 33 const u16 AD9249::serial_out_cntr_reg= 0x21;
wbeaumont 0:9efb460e962b 34 const u16 AD9249::serial_status_reg= 0x22;
wbeaumont 0:9efb460e962b 35 const u16 AD9249::sample_rate_reg= 0x100;
wbeaumont 0:9efb460e962b 36 const u16 AD9249::user_io_ctr2_reg= 0x101;
wbeaumont 0:9efb460e962b 37 const u16 AD9249::user_io_ctr3_reg= 0x102;
wbeaumont 0:9efb460e962b 38 const u16 AD9249::sync_reg= 0x109;
wbeaumont 0:9efb460e962b 39 */
wbeaumont 0:9efb460e962b 40
wbeaumont 0:9efb460e962b 41
wbeaumont 1:01459a6ab296 42 AD9249::AD9249( SWSPI_BI* spi_dev, DigitalOut* csb_pin):getVersion( AD9249_HDR_VER,AD9249_SRC_VER, __TIME__, __DATE__) {
wbeaumont 0:9efb460e962b 43 spi=spi_dev;csb=csb_pin;
wbeaumont 0:9efb460e962b 44 }
wbeaumont 0:9efb460e962b 45
wbeaumont 0:9efb460e962b 46
wbeaumont 0:9efb460e962b 47 AD9249::u32 AD9249::spi_cycle( u16 reg , bool rw , u16 nrbytes, u32 data){
wbeaumont 0:9efb460e962b 48 // format instruction
wbeaumont 0:9efb460e962b 49 u32 read =0;
wbeaumont 0:9efb460e962b 50 reg = 0x1FFF & reg;
wbeaumont 0:9efb460e962b 51 if (rw) reg |=0x8000;
wbeaumont 0:9efb460e962b 52 if (nrbytes > 2) return 0; // this function doesn't support stream
wbeaumont 0:9efb460e962b 53 u32 stnrbytes = (nrbytes-1);
wbeaumont 0:9efb460e962b 54 stnrbytes =stnrbytes <<13;
wbeaumont 0:9efb460e962b 55 reg|=stnrbytes; // reg is now the instruction
wbeaumont 0:9efb460e962b 56 spi->format(16,0); // should make sure the sclk is high
wbeaumont 0:9efb460e962b 57 printf("send %04X \n\r",reg);
wbeaumont 0:9efb460e962b 58
wbeaumont 0:9efb460e962b 59
wbeaumont 0:9efb460e962b 60
wbeaumont 0:9efb460e962b 61 if (rw) {
wbeaumont 0:9efb460e962b 62 spi->write(reg, csb , false ,CS_POL,true );
wbeaumont 0:9efb460e962b 63 spi->format((nrbytes)*8 ,0);
wbeaumont 0:9efb460e962b 64 read=spi->read(csb , true ,CS_POL );
wbeaumont 0:9efb460e962b 65 }
wbeaumont 0:9efb460e962b 66 else{
wbeaumont 0:9efb460e962b 67 spi->write(reg, csb , false ,CS_POL );
wbeaumont 0:9efb460e962b 68 spi->format((nrbytes)*8 ,0);
wbeaumont 0:9efb460e962b 69 spi->write(data, csb , true ,CS_POL );
wbeaumont 0:9efb460e962b 70
wbeaumont 0:9efb460e962b 71 }
wbeaumont 0:9efb460e962b 72
wbeaumont 0:9efb460e962b 73 return read;
wbeaumont 0:9efb460e962b 74 }
wbeaumont 0:9efb460e962b 75
wbeaumont 0:9efb460e962b 76
wbeaumont 0:9efb460e962b 77 bool AD9249::getDevInfo(u8&chipid,u8& grade ,u16 &rb ){
wbeaumont 0:9efb460e962b 78 u32 data=spi_cycle( chip_grade_reg, true , 2 , 0);
wbeaumont 0:9efb460e962b 79 rb=data;
wbeaumont 0:9efb460e962b 80 chipid= data & 0XFF;
wbeaumont 0:9efb460e962b 81 grade= (data >> 8) & 0xFF;
wbeaumont 0:9efb460e962b 82 return true;
wbeaumont 0:9efb460e962b 83 }
wbeaumont 0:9efb460e962b 84
wbeaumont 0:9efb460e962b 85 bool AD9249::getDevId(u8&chipid ){
wbeaumont 0:9efb460e962b 86 bool rv=readReg8(chip_id_reg,chipid);
wbeaumont 0:9efb460e962b 87 return rv;
wbeaumont 0:9efb460e962b 88 }
wbeaumont 0:9efb460e962b 89 bool AD9249::getGrade(u8&chipid ){
wbeaumont 0:9efb460e962b 90 bool rv=readReg8(chip_grade_reg,chipid);
wbeaumont 0:9efb460e962b 91 return rv;
wbeaumont 0:9efb460e962b 92 }
wbeaumont 0:9efb460e962b 93
wbeaumont 0:9efb460e962b 94 bool AD9249::readReg16( u16 regaddr, u16& data){
wbeaumont 0:9efb460e962b 95 u32 datai=spi_cycle( regaddr , true , 2 , 0);
wbeaumont 0:9efb460e962b 96 data=(u16)( datai & 0XFFFF);
wbeaumont 0:9efb460e962b 97 return true;
wbeaumont 0:9efb460e962b 98 }
wbeaumont 0:9efb460e962b 99
wbeaumont 0:9efb460e962b 100 bool AD9249::readReg8 ( u16 regaddr, u8& data){
wbeaumont 0:9efb460e962b 101 u32 datai=spi_cycle( regaddr, true , 1 , 0);
wbeaumont 0:9efb460e962b 102 data=(u8)( datai & 0XFF);
wbeaumont 0:9efb460e962b 103 return true;
wbeaumont 0:9efb460e962b 104 }
wbeaumont 0:9efb460e962b 105
wbeaumont 0:9efb460e962b 106
wbeaumont 0:9efb460e962b 107
wbeaumont 0:9efb460e962b 108 bool AD9249::setReg16( u16 regaddr, u16 data){
wbeaumont 0:9efb460e962b 109 u32 datai=spi_cycle( regaddr, false , 2 , (u32)data);
wbeaumont 0:9efb460e962b 110 return true;
wbeaumont 0:9efb460e962b 111 }
wbeaumont 0:9efb460e962b 112
wbeaumont 0:9efb460e962b 113 bool AD9249::setReg8 ( u16 regaddr, u8 data){
wbeaumont 0:9efb460e962b 114 u32 datai=spi_cycle( regaddr, false , 1 , (u32)data);
wbeaumont 0:9efb460e962b 115 return true;
wbeaumont 0:9efb460e962b 116 }
wbeaumont 0:9efb460e962b 117
wbeaumont 0:9efb460e962b 118
wbeaumont 0:9efb460e962b 119 bool AD9249::setPattern1(u16 pattern){
wbeaumont 0:9efb460e962b 120 bool rv=setReg16( usserpatt1_MSB_reg,pattern);
wbeaumont 0:9efb460e962b 121 return rv;
wbeaumont 0:9efb460e962b 122 }
wbeaumont 0:9efb460e962b 123 bool AD9249::setPattern2(u16 pattern){
wbeaumont 0:9efb460e962b 124 bool rv=setReg16( usserpatt2_MSB_reg,pattern);
wbeaumont 0:9efb460e962b 125 return rv;
wbeaumont 0:9efb460e962b 126 }
wbeaumont 0:9efb460e962b 127
wbeaumont 0:9efb460e962b 128 bool AD9249::readPattern1(u16& pattern){
wbeaumont 0:9efb460e962b 129 bool rv= readReg16( usserpatt1_MSB_reg,pattern);
wbeaumont 0:9efb460e962b 130 return rv;
wbeaumont 0:9efb460e962b 131 }
wbeaumont 0:9efb460e962b 132 bool AD9249::readPattern2(u16& pattern){
wbeaumont 0:9efb460e962b 133 bool rv= readReg16( usserpatt2_MSB_reg,pattern);
wbeaumont 0:9efb460e962b 134 return rv;
wbeaumont 0:9efb460e962b 135
wbeaumont 0:9efb460e962b 136 }
wbeaumont 0:9efb460e962b 137
wbeaumont 1:01459a6ab296 138 void AD9249::init1(){}
wbeaumont 1:01459a6ab296 139 void AD9249::init2(){}