Romilly Cocking / MCP23S17

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Dependents:   MCP23S17Test MCP23S17_Basic_IO_Demo HelloWorld Lab3-SnakeGame ... more

main.cpp@1:5abd129839e7, 2010-08-21 (annotated)

Committer:
romilly
Date:
Sat Aug 21 07:05:21 2010 +0000
Revision:
1:5abd129839e7
Parent:
0:930da696072e 
Added methods to set port directions, set outputd to either port and to read each port.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
romilly 0:930da696072e 1 #include "mbed.h"
romilly 0:930da696072e 2
romilly 1:5abd129839e7 3 /*
romilly 1:5abd129839e7 4 * next baby step towards towards a library for MCP23S17
romilly 1:5abd129839e7 5 * I'm proposing to allow 8-bit and 16-bit conditioning, reads, and writes
romilly 1:5abd129839e7 6 * and interrupt conditioning
romilly 0:930da696072e 7 *
romilly 1:5abd129839e7 8 * Unless someone asks for them, I'm not going to implement
romilly 1:5abd129839e7 9 * multi-reads or writes where a sequence of many bytes are read from or written
romilly 1:5abd129839e7 10 * to the same register
romilly 1:5abd129839e7 11 *
romilly 1:5abd129839e7 12 * This is currently experimental code. I'm still checking that I've understood the chip API.
romilly 0:930da696072e 13 */
romilly 0:930da696072e 14
romilly 1:5abd129839e7 15
romilly 1:5abd129839e7 16 // all register addresses assume IOVCON.BANK = 0 (POR default)
romilly 1:5abd129839e7 17
romilly 1:5abd129839e7 18 #define IODIRA 0x00
romilly 1:5abd129839e7 19 #define IODIRB 0x01
romilly 1:5abd129839e7 20 #define IOCON 0x0A
romilly 1:5abd129839e7 21 #define GPIOA 0x12
romilly 1:5abd129839e7 22 #define GPIOB 0x13
romilly 1:5abd129839e7 23 #define OLATA 0x14
romilly 1:5abd129839e7 24 #define OLATB 0x15
romilly 1:5abd129839e7 25
romilly 1:5abd129839e7 26 // Control settings
romilly 1:5abd129839e7 27
romilly 1:5abd129839e7 28 #define IOCON_BANK 0x80 // Banked registers
romilly 1:5abd129839e7 29 #define IOCON_BYTE_MODE 0x20 // Disables sequential operation. If bank = 0, operations toggle between A and B registers
romilly 1:5abd129839e7 30 #define IOCON_HAEN 0x08 // Hardware address enable
romilly 0:930da696072e 31
romilly 0:930da696072e 32 SPI spi(p5, p6, p7);
romilly 1:5abd129839e7 33 DigitalOut ncs(p20); // not chip select; bring this low to enable the chip
romilly 1:5abd129839e7 34 char writeOpcode = 0x40; // A0, A1, A2 are tied to ground on the breadboard.
romilly 1:5abd129839e7 35 char readOpcode = writeOpcode | 1; // low order bit = 1 for read
romilly 0:930da696072e 36
romilly 1:5abd129839e7 37 void _write(char address, char data) {
romilly 0:930da696072e 38 ncs = 0;
romilly 1:5abd129839e7 39 spi.write(writeOpcode);
romilly 0:930da696072e 40 spi.write(address);
romilly 0:930da696072e 41 spi.write(data);
romilly 0:930da696072e 42 ncs = 1;
romilly 0:930da696072e 43 }
romilly 0:930da696072e 44
romilly 1:5abd129839e7 45 char _read(char address) {
romilly 1:5abd129839e7 46 ncs = 0;
romilly 1:5abd129839e7 47 spi.write(readOpcode);
romilly 1:5abd129839e7 48 spi.write(address);
romilly 1:5abd129839e7 49 char result = spi.write(0);
romilly 1:5abd129839e7 50 ncs = 1;
romilly 1:5abd129839e7 51 return result;
romilly 1:5abd129839e7 52 }
romilly 1:5abd129839e7 53
romilly 0:930da696072e 54 void init() {
romilly 1:5abd129839e7 55 _write(IOCON, (IOCON_BYTE_MODE | IOCON_HAEN )); // Hardware addressing on, operations toggle between A and B registers
romilly 0:930da696072e 56 }
romilly 0:930da696072e 57
romilly 1:5abd129839e7 58 void directionA(char direction) {
romilly 1:5abd129839e7 59 _write(IODIRA, direction);
romilly 1:5abd129839e7 60 }
romilly 1:5abd129839e7 61
romilly 1:5abd129839e7 62 void directionB(char direction) {
romilly 1:5abd129839e7 63 _write(IODIRB, direction);
romilly 1:5abd129839e7 64 }
romilly 1:5abd129839e7 65
romilly 1:5abd129839e7 66 void outputA(char byte) {
romilly 1:5abd129839e7 67 _write(OLATA, byte);
romilly 1:5abd129839e7 68 }
romilly 1:5abd129839e7 69
romilly 1:5abd129839e7 70 void outputB(char byte) {
romilly 1:5abd129839e7 71 _write(OLATB, byte);
romilly 1:5abd129839e7 72 }
romilly 1:5abd129839e7 73
romilly 1:5abd129839e7 74 char inputA() {
romilly 1:5abd129839e7 75 return _read(GPIOA);
romilly 0:930da696072e 76 }
romilly 0:930da696072e 77
romilly 0:930da696072e 78 int main() {
romilly 0:930da696072e 79 init();
romilly 1:5abd129839e7 80 directionA(0xFF); // all 8 bits set to input
romilly 1:5abd129839e7 81 directionB(0x00); // all 8 bits set to ouptut
romilly 0:930da696072e 82 while(1) {
romilly 0:930da696072e 83 wait(0.2);
romilly 1:5abd129839e7 84 // copy inputs from A to outputs on B
romilly 1:5abd129839e7 85 outputB(inputA());
romilly 1:5abd129839e7 86
romilly 0:930da696072e 87 }
romilly 0:930da696072e 88 }