v 0.4

Dependents:   MCP23S17Test MCP23S17_Basic_IO_Demo HelloWorld Lab3-SnakeGame ... more

Committer:
romilly
Date:
Mon Aug 23 10:57:59 2010 +0000
Revision:
8:841b19734955
Parent:
7:53498e24592c
Child:
9:068b1e8909bb

        

Who changed what in which revision?

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romilly 7:53498e24592c 1 /* MCP23S17 - drive the Microchip MCP23S17 16-bit Port Extender using SPI
romilly 7:53498e24592c 2 * Copyright (c) 2010 Romilly Cocking
romilly 7:53498e24592c 3 * Released under the MIT License: http://mbed.org/license/mit
romilly 7:53498e24592c 4 *
romilly 8:841b19734955 5 * version 0.3
romilly 7:53498e24592c 6 */
romilly 7:53498e24592c 7 #include "mbed.h"
romilly 7:53498e24592c 8
romilly 7:53498e24592c 9 #ifndef MCP23S17_H
romilly 7:53498e24592c 10 #define MCP23S17_H
romilly 7:53498e24592c 11
romilly 7:53498e24592c 12 #define INTERRUPT_POLARITY_BIT 0x02
romilly 7:53498e24592c 13 #define INTERRUPT_MIRROR_BIT 0x40
romilly 7:53498e24592c 14
romilly 7:53498e24592c 15 // all register addresses assume IOCON.BANK = 0 (POR default)
romilly 7:53498e24592c 16
romilly 7:53498e24592c 17 #define IODIRA 0x00
romilly 7:53498e24592c 18 #define IODIRB 0x01
romilly 7:53498e24592c 19 #define GPINTENA 0x04
romilly 7:53498e24592c 20 #define GPINTENB 0x05
romilly 7:53498e24592c 21 #define DEFVALA 0x06
romilly 7:53498e24592c 22 #define INTCONA 0x08
romilly 7:53498e24592c 23 #define IOCON 0x0A
romilly 7:53498e24592c 24 #define GPIOA 0x12
romilly 7:53498e24592c 25 #define GPIOB 0x13
romilly 7:53498e24592c 26 #define OLATA 0x14
romilly 7:53498e24592c 27 #define OLATB 0x15
romilly 7:53498e24592c 28
romilly 7:53498e24592c 29 // Control settings
romilly 7:53498e24592c 30
romilly 7:53498e24592c 31 #define IOCON_BANK 0x80 // Banked registers
romilly 7:53498e24592c 32 #define IOCON_BYTE_MODE 0x20 // Disables sequential operation. If bank = 0, operations toggle between A and B registers
romilly 7:53498e24592c 33 #define IOCON_HAEN 0x08 // Hardware address enable
romilly 7:53498e24592c 34
romilly 7:53498e24592c 35 enum Polarity { ACTIVE_LOW , ACTIVE_HIGH };
romilly 8:841b19734955 36 enum Port { PORT_A, PORT_B };
romilly 7:53498e24592c 37
romilly 7:53498e24592c 38 class MCP23S17 {
romilly 7:53498e24592c 39 public:
romilly 7:53498e24592c 40 MCP23S17(SPI& spi, PinName ncs, char writeOpcode);
romilly 8:841b19734955 41 void direction(Port port, char direction);
romilly 8:841b19734955 42 void interruptEnable(Port port, char interruptsEnabledMask);
romilly 7:53498e24592c 43 void interruptPolarity(Polarity polarity);
romilly 7:53498e24592c 44 void mirrorInterrupts(bool mirror);
romilly 8:841b19734955 45 void defaultValue(Port port, char valuesToCompare);
romilly 8:841b19734955 46 void interruptControl(Port port, char interruptContolBits);
romilly 8:841b19734955 47 char read(Port port);
romilly 8:841b19734955 48 void write(Port port, char byte);
romilly 7:53498e24592c 49 protected:
romilly 7:53498e24592c 50 SPI& _spi;
romilly 7:53498e24592c 51 DigitalOut _ncs;
romilly 7:53498e24592c 52 void _init();
romilly 8:841b19734955 53 void _write(Port port, char address, char data);
romilly 7:53498e24592c 54 void _write(char address, char data);
romilly 8:841b19734955 55 char _read(Port port, char address);
romilly 7:53498e24592c 56 char _read(char address);
romilly 7:53498e24592c 57 char _readOpcode;
romilly 7:53498e24592c 58 char _writeOpcode;
romilly 7:53498e24592c 59 };
romilly 7:53498e24592c 60
romilly 2:6144709f1700 61 #endif