Tedd OKANO / Mbed 2 deprecated MARY_CAMERA_Hello

Dependencies:   MARY_CAMERA NokiaLCD mbed

Committer:
okano
Date:
Fri Feb 14 09:49:02 2014 +0000
Revision:
3:152362acd181
Parent:
2:2e03fc4f485b
Child:
4:5e1828a8e238
simple prototype #1

Who changed what in which revision?

UserRevisionLine numberNew contents of line
okano 0:1062142e5718 1 #include "mbed.h"
okano 0:1062142e5718 2 #include "MARMEX_OB_oled.h"
okano 0:1062142e5718 3
okano 0:1062142e5718 4
okano 0:1062142e5718 5 #define PARAM_NUM 99
okano 0:1062142e5718 6 #define CAM_I2C_ADDR 0x42
okano 0:1062142e5718 7
okano 0:1062142e5718 8 const char param[2][PARAM_NUM] = {
okano 0:1062142e5718 9 {
okano 0:1062142e5718 10 0x01,0x02,0x03,0x0c,0x0e,0x0f,0x11,0x12,0x15,0x16,0x17,0x18,0x19,0x1a,0x1e,0x21,0x22,
okano 0:1062142e5718 11 0x29,0x32,0x33,0x34,0x35,0x37,0x38,0x39,0x3b,0x3c,0x3d,0x3e,0x3f,0x40,0x41,0x41,
okano 0:1062142e5718 12 0x43,0x44,0x45,0x46,0x47,0x48,0x4b,0x4c,0x4d,0x4e,0x4f,0x50,0x51,0x52,0x53,
okano 0:1062142e5718 13 0x54,0x56,0x58,0x59,0x5a,0x5b,0x5c,0x5d,0x5e,0x69,0x6a,0x6b,0x6c,0x6d,0x6e,
okano 0:1062142e5718 14 0x6f,0x70,0x71,0x72,0x73,0x74,0x75,0x76,0x77,0x78,0x79,0x8d,0x8e,0x8f,0x90,
okano 0:1062142e5718 15 0x91,0x96,0x96,0x97,0x98,0x99,0x9a,0x9a,0x9b,0x9c,0x9d,0x9e,0xa2,0xa4,0xb0,
okano 0:1062142e5718 16 0xb1,0xb2,0xb3,0xb8,0xc8,0xc9
okano 0:1062142e5718 17 },
okano 0:1062142e5718 18 {
okano 0:1062142e5718 19 0x40,0x60,0x02,0x0c,0x61,0x4b,0x81,0x04 ,0x00,0x02,0x39,0x03,0x03,0x7b,0x37,0x02,0x91,
okano 0:1062142e5718 20 0x07,0x80,0x0b,0x11,0x0b,0x1d,0x71,0x2a,0x12,0x78,0xc3,0x11,0x00,0xd0,0x08,0x38,
okano 0:1062142e5718 21 0x0a,0xf0,0x34,0x58,0x28,0x3a,0x09,0x00,0x40,0x20,0x80,0x80,0x00,0x22,0x5e,
okano 0:1062142e5718 22 0x80,0x40,0x9e,0x88,0x88,0x44,0x67,0x49,0x0e,0x00,0x40,0x0a,0x0a,0x55,0x11,
okano 0:1062142e5718 23 0x9f,0x3a,0x35,0x11,0xf1,0x10,0x05,0xe1,0x01,0x04,0x01,0x4f,0x00,0x00,0x00,
okano 0:1062142e5718 24 0x00,0x00,0x00,0x30,0x20,0x30,0x00,0x84,0x29,0x03,0x4c,0x3f,0x52,0x88,0x84,
okano 0:1062142e5718 25 0x0c,0x0e,0x82,0x0a,0xf0,0x60
okano 0:1062142e5718 26 }
okano 0:1062142e5718 27 };
okano 0:1062142e5718 28
okano 0:1062142e5718 29
okano 0:1062142e5718 30 MARMEX_OB_oled oled1( p5, p7, p20, p16, p15 ); // mosi, sclk, cs, rst, power_control -- maple-mini-type-b-slot1
okano 0:1062142e5718 31
okano 0:1062142e5718 32
okano 2:2e03fc4f485b 33 SPI camspi( p5, p6, p7 );
okano 1:ce27bc7b44d4 34 DigitalOut cs2( p22 );
okano 1:ce27bc7b44d4 35 DigitalOut vsync( p9 );
okano 1:ce27bc7b44d4 36 DigitalOut camera_reset( p26 );
okano 1:ce27bc7b44d4 37
okano 1:ce27bc7b44d4 38 void init( void )
okano 0:1062142e5718 39 {
okano 0:1062142e5718 40 I2C i2c( p28, p27 );
okano 0:1062142e5718 41
okano 1:ce27bc7b44d4 42 vsync = 0;
okano 1:ce27bc7b44d4 43 cs2 = 1;
okano 1:ce27bc7b44d4 44 camera_reset = 0;
okano 1:ce27bc7b44d4 45 wait_ms( 100 );
okano 1:ce27bc7b44d4 46 camera_reset = 1;
okano 1:ce27bc7b44d4 47 wait_ms( 100 );
okano 1:ce27bc7b44d4 48
okano 1:ce27bc7b44d4 49
okano 0:1062142e5718 50 for ( int i = 0; i < PARAM_NUM; i++ ) {
okano 0:1062142e5718 51 i2c.start();
okano 0:1062142e5718 52 i2c.write( CAM_I2C_ADDR );
okano 0:1062142e5718 53 i2c.write( param[ 0 ][ i ] );
okano 0:1062142e5718 54 i2c.write( param[ 1 ][ i ] );
okano 0:1062142e5718 55 i2c.stop();
okano 0:1062142e5718 56 wait_ms( 20 );
okano 0:1062142e5718 57 }
okano 3:152362acd181 58
okano 3:152362acd181 59
okano 2:2e03fc4f485b 60 camspi.format(8);
okano 2:2e03fc4f485b 61 camspi.frequency( 1000000 );
okano 1:ce27bc7b44d4 62 vsync = 0;
okano 0:1062142e5718 63
okano 1:ce27bc7b44d4 64 }
okano 0:1062142e5718 65
okano 3:152362acd181 66 int send_spi( char data )
okano 0:1062142e5718 67 {
okano 0:1062142e5718 68 int tmp;
okano 0:1062142e5718 69
okano 0:1062142e5718 70 cs2 = 0;
okano 2:2e03fc4f485b 71 tmp = camspi.write( data );
okano 0:1062142e5718 72 cs2 = 1;
okano 0:1062142e5718 73
okano 0:1062142e5718 74 return ( tmp );
okano 0:1062142e5718 75 }
okano 0:1062142e5718 76
okano 3:152362acd181 77
okano 3:152362acd181 78 #define COMMAND_WRITE 0x00
okano 3:152362acd181 79 #define COMMAND_READ 0x80
okano 3:152362acd181 80 #define COMMAND_ADDR_INCREMENT 0x20
okano 1:ce27bc7b44d4 81
okano 3:152362acd181 82 #define MEMORY_ADDR_LOW__REGISTER 0x0
okano 3:152362acd181 83 #define MEMORY_ADDR_MID__REGISTER 0x1
okano 3:152362acd181 84 #define MEMORY_ADDR_HIGH_REGISTER 0x2
okano 3:152362acd181 85 #define CAMERA_DATA_REGISTER 0x8
okano 3:152362acd181 86 #define CONTROL_DATA_REGISTER 0x3
okano 3:152362acd181 87 #define STATUS_REGISTER 0x4
okano 3:152362acd181 88
okano 3:152362acd181 89 #define CONTROL__PAUSE_BUFFER_UPDATE 0x01
okano 3:152362acd181 90 #define CONTROL__RESUME_BUFFER_UPDATE 0x00
okano 3:152362acd181 91
okano 3:152362acd181 92 void write_register( char reg, char value )
okano 1:ce27bc7b44d4 93 {
okano 3:152362acd181 94 send_spi( COMMAND_WRITE | reg );
okano 3:152362acd181 95 send_spi( value );
okano 3:152362acd181 96 }
okano 1:ce27bc7b44d4 97
okano 3:152362acd181 98 int read_register( char reg )
okano 3:152362acd181 99 {
okano 3:152362acd181 100 // printf( "0x%02X\r\n", COMMAND_READ | reg | ((reg == CAMERA_DATA_REGISTER) ? COMMAND_ADDR_INCREMENT : 0x00) );
okano 3:152362acd181 101
okano 3:152362acd181 102 return ( send_spi( COMMAND_READ | reg | ((reg == CAMERA_DATA_REGISTER) ? COMMAND_ADDR_INCREMENT : 0x00) ) );
okano 3:152362acd181 103 // return ( send_spi( COMMAND_READ | reg ) );
okano 1:ce27bc7b44d4 104 }
okano 1:ce27bc7b44d4 105
okano 1:ce27bc7b44d4 106 void open_transfer( void )
okano 1:ce27bc7b44d4 107 {
okano 3:152362acd181 108 write_register( CONTROL_DATA_REGISTER, CONTROL__PAUSE_BUFFER_UPDATE );
okano 2:2e03fc4f485b 109
okano 2:2e03fc4f485b 110 vsync = 0;
okano 2:2e03fc4f485b 111
okano 3:152362acd181 112 read_register( STATUS_REGISTER );
okano 3:152362acd181 113 while ( !(read_register( STATUS_REGISTER ) & 0x1) ); // wait until LSB becomes '1'
okano 1:ce27bc7b44d4 114 }
okano 1:ce27bc7b44d4 115
okano 1:ce27bc7b44d4 116 void close_transfer( void )
okano 1:ce27bc7b44d4 117 {
okano 3:152362acd181 118 write_register( CONTROL_DATA_REGISTER, CONTROL__RESUME_BUFFER_UPDATE );
okano 2:2e03fc4f485b 119
okano 3:152362acd181 120 read_register( STATUS_REGISTER );
okano 3:152362acd181 121 while ( read_register( STATUS_REGISTER ) & 0x1 ); // wait until LSB becomes '0'
okano 2:2e03fc4f485b 122
okano 2:2e03fc4f485b 123 vsync = 1;
okano 1:ce27bc7b44d4 124 }
okano 1:ce27bc7b44d4 125
okano 1:ce27bc7b44d4 126
okano 1:ce27bc7b44d4 127 void set_address( int address )
okano 1:ce27bc7b44d4 128 {
okano 3:152362acd181 129 write_register( MEMORY_ADDR_LOW__REGISTER, (address >> 0) & 0xFF );
okano 3:152362acd181 130 write_register( MEMORY_ADDR_MID__REGISTER, (address >> 8) & 0xFF );
okano 3:152362acd181 131 write_register( MEMORY_ADDR_HIGH_REGISTER, (address >> 16) & 0xFF );
okano 1:ce27bc7b44d4 132 }
okano 1:ce27bc7b44d4 133
okano 1:ce27bc7b44d4 134 #define PIXEL_PER_LINE 176
okano 1:ce27bc7b44d4 135 #define BYTE_PER_PIXEL 2
okano 1:ce27bc7b44d4 136 #define BYTE_PER_LINE (PIXEL_PER_LINE * BYTE_PER_PIXEL)
okano 1:ce27bc7b44d4 137
okano 1:ce27bc7b44d4 138
okano 1:ce27bc7b44d4 139 void transfer_a_line( short *p, int line_number, int x_offset, int n_of_pixels )
okano 1:ce27bc7b44d4 140 {
okano 3:152362acd181 141 set_address( line_number * BYTE_PER_LINE + x_offset * BYTE_PER_PIXEL );
okano 3:152362acd181 142
okano 3:152362acd181 143 read_register( CAMERA_DATA_REGISTER );
okano 3:152362acd181 144
okano 1:ce27bc7b44d4 145 for( int x = 0; x < n_of_pixels; x++ )
okano 3:152362acd181 146 *p++ = (read_register( CAMERA_DATA_REGISTER ) << 8) | (read_register( CAMERA_DATA_REGISTER ) << 0);
okano 1:ce27bc7b44d4 147 }
okano 1:ce27bc7b44d4 148
okano 1:ce27bc7b44d4 149
okano 1:ce27bc7b44d4 150 #define X_OFFSET 24
okano 1:ce27bc7b44d4 151 #define Y_OFFSET 8
okano 0:1062142e5718 152
okano 0:1062142e5718 153 int main()
okano 0:1062142e5718 154 {
okano 1:ce27bc7b44d4 155 oled1.cls();
okano 1:ce27bc7b44d4 156
okano 3:152362acd181 157 short buf[ 128 ];
okano 1:ce27bc7b44d4 158 init();
okano 0:1062142e5718 159
okano 0:1062142e5718 160 while ( 1 ) {
okano 1:ce27bc7b44d4 161 open_transfer();
okano 0:1062142e5718 162
okano 3:152362acd181 163 for ( int line = 0; line < 128; line++ ) {
okano 3:152362acd181 164 transfer_a_line( buf, line + Y_OFFSET, X_OFFSET, 128 );
okano 1:ce27bc7b44d4 165 oled1.blit565( 0, line, 128, 1, buf );
okano 0:1062142e5718 166 }
okano 0:1062142e5718 167
okano 1:ce27bc7b44d4 168 close_transfer();
okano 0:1062142e5718 169 }
okano 0:1062142e5718 170 }