Tedd OKANO / MARY_CAMERA

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MARY_CAMERA.cpp@25:8f6c2a094544, 2014-03-15 (annotated)

Committer:
okano
Date:
Sat Mar 15 12:00:49 2014 +0000
Revision:
25:8f6c2a094544
Parent:
24:cc4271d1545f
Child:
26:9a4e95fe0576
test code

Who changed what in which revision?

UserRevisionLine numberNew contents of line
okano 0:f4584dba3bac 1 #include "mbed.h"
okano 0:f4584dba3bac 2 #include "MARY_CAMERA.h"
okano 0:f4584dba3bac 3
okano 2:ee71ffdf317e 4 #define PARAM_NUM 99
okano 2:ee71ffdf317e 5 #define CAM_I2C_ADDR 0x42
okano 2:ee71ffdf317e 6
okano 0:f4584dba3bac 7 #define RESET_PULSE_WIDTH 100 // mili-seconds
okano 0:f4584dba3bac 8 #define RESET_RECOVERY_TIME 100 // mili-seconds
okano 0:f4584dba3bac 9
okano 2:ee71ffdf317e 10 #define COMMAND_WRITE 0x00
okano 2:ee71ffdf317e 11 #define COMMAND_READ 0x80
okano 2:ee71ffdf317e 12 #define COMMAND_ADDR_INCREMENT 0x20
okano 0:f4584dba3bac 13
okano 2:ee71ffdf317e 14 #define MEMORY_ADDR_LOW__REGISTER 0x0
okano 2:ee71ffdf317e 15 #define MEMORY_ADDR_MID__REGISTER 0x1
okano 2:ee71ffdf317e 16 #define MEMORY_ADDR_HIGH_REGISTER 0x2
okano 2:ee71ffdf317e 17 #define CAMERA_DATA_REGISTER 0x8
okano 2:ee71ffdf317e 18 #define CONTROL_DATA_REGISTER 0x3
okano 2:ee71ffdf317e 19 #define STATUS_REGISTER 0x4
okano 2:ee71ffdf317e 20
okano 2:ee71ffdf317e 21 #define CONTROL__PAUSE_BUFFER_UPDATE 0x01
okano 2:ee71ffdf317e 22 #define CONTROL__RESUME_BUFFER_UPDATE 0x00
okano 0:f4584dba3bac 23
okano 0:f4584dba3bac 24
okano 0:f4584dba3bac 25 MARY_CAMERA::MARY_CAMERA(
okano 4:cb0ef3fd89c9 26 PinName SPI_mosi,
okano 4:cb0ef3fd89c9 27 PinName SPI_miso,
okano 4:cb0ef3fd89c9 28 PinName SPI_sck,
okano 4:cb0ef3fd89c9 29 PinName SPI_cs,
okano 0:f4584dba3bac 30 PinName cam_reset,
okano 4:cb0ef3fd89c9 31 PinName I2C_sda,
okano 4:cb0ef3fd89c9 32 PinName I2C_scl
okano 2:ee71ffdf317e 33 ) :
okano 4:cb0ef3fd89c9 34 _spi( SPI_mosi, SPI_miso, SPI_sck ),
okano 4:cb0ef3fd89c9 35 _cs( SPI_cs ),
okano 4:cb0ef3fd89c9 36 _reset( cam_reset ),
okano 4:cb0ef3fd89c9 37 _i2c( I2C_sda, I2C_scl )
okano 0:f4584dba3bac 38 {
okano 11:61a025e8ab68 39 #ifdef IGNORE_INITIALIZATION_ERROR
okano 0:f4584dba3bac 40 init();
okano 11:61a025e8ab68 41 #else
okano 22:1a923c255be6 42 if ( 0 != init() )
okano 11:61a025e8ab68 43 error( "camera initialization failed." );
okano 11:61a025e8ab68 44 #endif
okano 0:f4584dba3bac 45 }
okano 0:f4584dba3bac 46
okano 22:1a923c255be6 47 int MARY_CAMERA::init( void )
okano 11:61a025e8ab68 48 {
okano 22:1a923c255be6 49 const char camera_register_setting[ PARAM_NUM ][ 2 ] = {
okano 23:214896356355 50 { 0x01, 0x40 }, { 0x02, 0x60 }, { 0x03, 0x02 }, { 0x0C, 0x0C },
okano 23:214896356355 51 { 0x0E, 0x61 }, { 0x0F, 0x4B }, { 0x11, 0x81 }, { 0x12, 0x04 },
okano 23:214896356355 52 { 0x15, 0x00 }, { 0x16, 0x02 }, { 0x17, 0x39 }, { 0x18, 0x03 },
okano 23:214896356355 53 { 0x19, 0x03 }, { 0x1A, 0x7B }, { 0x1E, 0x37 }, { 0x21, 0x02 },
okano 23:214896356355 54 { 0x22, 0x91 }, { 0x29, 0x07 }, { 0x32, 0x80 }, { 0x33, 0x0B },
okano 23:214896356355 55 { 0x34, 0x11 }, { 0x35, 0x0B }, { 0x37, 0x1D }, { 0x38, 0x71 },
okano 23:214896356355 56 { 0x39, 0x2A }, { 0x3B, 0x12 }, { 0x3C, 0x78 }, { 0x3D, 0xC3 },
okano 23:214896356355 57 { 0x3E, 0x11 }, { 0x3F, 0x00 }, { 0x40, 0xD0 }, { 0x41, 0x08 },
okano 23:214896356355 58 { 0x41, 0x38 }, { 0x43, 0x0A }, { 0x44, 0xF0 }, { 0x45, 0x34 },
okano 23:214896356355 59 { 0x46, 0x58 }, { 0x47, 0x28 }, { 0x48, 0x3A }, { 0x4B, 0x09 },
okano 23:214896356355 60 { 0x4C, 0x00 }, { 0x4D, 0x40 }, { 0x4E, 0x20 }, { 0x4F, 0x80 },
okano 23:214896356355 61 { 0x50, 0x80 }, { 0x51, 0x00 }, { 0x52, 0x22 }, { 0x53, 0x5E },
okano 23:214896356355 62 { 0x54, 0x80 }, { 0x56, 0x40 }, { 0x58, 0x9E }, { 0x59, 0x88 },
okano 23:214896356355 63 { 0x5A, 0x88 }, { 0x5B, 0x44 }, { 0x5C, 0x67 }, { 0x5D, 0x49 },
okano 23:214896356355 64 { 0x5E, 0x0E }, { 0x69, 0x00 }, { 0x6A, 0x40 }, { 0x6B, 0x0A },
okano 23:214896356355 65 { 0x6C, 0x0A }, { 0x6D, 0x55 }, { 0x6E, 0x11 }, { 0x6F, 0x9F },
okano 23:214896356355 66 { 0x70, 0x3A }, { 0x71, 0x35 }, { 0x72, 0x11 }, { 0x73, 0xF1 },
okano 23:214896356355 67 { 0x74, 0x10 }, { 0x75, 0x05 }, { 0x76, 0xE1 }, { 0x77, 0x01 },
okano 23:214896356355 68 { 0x78, 0x04 }, { 0x79, 0x01 }, { 0x8D, 0x4F }, { 0x8E, 0x00 },
okano 23:214896356355 69 { 0x8F, 0x00 }, { 0x90, 0x00 }, { 0x91, 0x00 }, { 0x96, 0x00 },
okano 23:214896356355 70 { 0x96, 0x00 }, { 0x97, 0x30 }, { 0x98, 0x20 }, { 0x99, 0x30 },
okano 23:214896356355 71 { 0x9A, 0x00 }, { 0x9A, 0x84 }, { 0x9B, 0x29 }, { 0x9C, 0x03 },
okano 23:214896356355 72 { 0x9D, 0x4C }, { 0x9E, 0x3F }, { 0xA2, 0x52 }, { 0xA4, 0x88 },
okano 23:214896356355 73 { 0xB0, 0x84 }, { 0xB1, 0x0C }, { 0xB2, 0x0E }, { 0xB3, 0x82 },
okano 23:214896356355 74 { 0xB8, 0x0A }, { 0xC8, 0xF0 }, { 0xC9, 0x60 },
okano 13:210f4bbd0cd6 75 };
okano 19:1d07d6d762a9 76
okano 11:61a025e8ab68 77 // SPI settings
okano 11:61a025e8ab68 78
okano 11:61a025e8ab68 79 _cs = 1; // set ChipSelect signal HIGH
okano 11:61a025e8ab68 80 _spi.format( 8 ); // camera SPI : 8bits/transfer
okano 11:61a025e8ab68 81 _spi.frequency( SPI_FREQUENCY ); // SPI frequency setting
okano 11:61a025e8ab68 82
okano 11:61a025e8ab68 83 // reset
okano 0:f4584dba3bac 84
okano 4:cb0ef3fd89c9 85 _reset = 0;
okano 11:61a025e8ab68 86 wait_ms( RESET_PULSE_WIDTH ); // assert RESET signal
okano 4:cb0ef3fd89c9 87 _reset = 1;
okano 11:61a025e8ab68 88 wait_ms( RESET_RECOVERY_TIME ); // deassert RESET signal
okano 0:f4584dba3bac 89
okano 22:1a923c255be6 90 _horizontal_size = QCIF_PIXEL_PER_LINE;
okano 22:1a923c255be6 91 _vertical_size = QCIF_LINE_PER_FRAME;
okano 19:1d07d6d762a9 92
okano 22:1a923c255be6 93 for ( int i = 0; i < PARAM_NUM; i++ ) {
okano 22:1a923c255be6 94 if ( 0 != (_error_state = _i2c.write( CAM_I2C_ADDR, camera_register_setting[ i ], 2 )) )
okano 22:1a923c255be6 95 break;
okano 22:1a923c255be6 96
okano 22:1a923c255be6 97 wait_ms( 20 ); // camera register writing requires this interval
okano 22:1a923c255be6 98 }
okano 22:1a923c255be6 99
okano 22:1a923c255be6 100 return _error_state; // return non-zero if I2C access failed
okano 22:1a923c255be6 101 }
okano 22:1a923c255be6 102
okano 22:1a923c255be6 103 void MARY_CAMERA::resolution( CameraResolution res )
okano 22:1a923c255be6 104 {
okano 22:1a923c255be6 105 #define OVERWRITE_PARAM_NUM 12
okano 22:1a923c255be6 106 const char over_write_param[ 5 ][ OVERWRITE_PARAM_NUM ] = {
okano 22:1a923c255be6 107 { 0x17, 0x18, 0x32, 0x19, 0x1a, 0x03, 0x0c, 0x3e, 0x71, 0x72, 0x73, 0xa2 }, // register addr
okano 22:1a923c255be6 108 { 0x39, 0x03, 0x80, 0x03, 0x7b, 0x02, 0x0c, 0x11, 0x35, 0x11, 0xf1, 0x52 }, // QSIF
okano 22:1a923c255be6 109 { 0x13, 0x01, 0xb6, 0x02, 0x7a, 0x0a, 0x00, 0x00, 0x35, 0x11, 0xf0, 0x02 }, // VGA
okano 22:1a923c255be6 110 { 0x16, 0x04, 0x80, 0x02, 0x7a, 0x0a, 0x04, 0x19, 0x35, 0x11, 0xf1, 0x02 }, // QVGA
okano 22:1a923c255be6 111 { 0x16, 0x04, 0xa4, 0x02, 0x7a, 0x0a, 0x04, 0x1a, 0x35, 0x22, 0xf2, 0x02 }, // QQVGA
okano 22:1a923c255be6 112 };
okano 22:1a923c255be6 113 char d[ 2 ];
okano 22:1a923c255be6 114
okano 22:1a923c255be6 115 switch ( res ) {
okano 19:1d07d6d762a9 116 case QCIF:
okano 19:1d07d6d762a9 117 _horizontal_size = QCIF_PIXEL_PER_LINE;
okano 19:1d07d6d762a9 118 _vertical_size = QCIF_LINE_PER_FRAME;
okano 19:1d07d6d762a9 119 break;
okano 19:1d07d6d762a9 120 case VGA:
okano 19:1d07d6d762a9 121 _horizontal_size = VGA_PIXEL_PER_LINE;
okano 19:1d07d6d762a9 122 _vertical_size = VGA_LINE_PER_FRAME;
okano 19:1d07d6d762a9 123 break;
okano 19:1d07d6d762a9 124 case QVGA:
okano 19:1d07d6d762a9 125 _horizontal_size = VGA_PIXEL_PER_LINE / 2;
okano 19:1d07d6d762a9 126 _vertical_size = VGA_LINE_PER_FRAME / 2;
okano 19:1d07d6d762a9 127 break;
okano 19:1d07d6d762a9 128 case QQVGA:
okano 19:1d07d6d762a9 129 _horizontal_size = VGA_PIXEL_PER_LINE / 4;
okano 19:1d07d6d762a9 130 _vertical_size = VGA_LINE_PER_FRAME / 4;
okano 19:1d07d6d762a9 131 break;
okano 19:1d07d6d762a9 132 }
okano 19:1d07d6d762a9 133
okano 11:61a025e8ab68 134 // set camera registers
okano 0:f4584dba3bac 135
okano 22:1a923c255be6 136 for ( int i = 0; i < OVERWRITE_PARAM_NUM; i++ ) {
okano 22:1a923c255be6 137 d[ 0 ] = over_write_param[ 0 ][ i ];
okano 22:1a923c255be6 138 d[ 1 ] = over_write_param[ res ][ i ];
okano 23:214896356355 139
okano 22:1a923c255be6 140 if ( 0 != (_error_state = _i2c.write( CAM_I2C_ADDR, d, 2 )) )
okano 13:210f4bbd0cd6 141 break;
okano 23:214896356355 142
okano 13:210f4bbd0cd6 143 wait_ms( 20 ); // camera register writing requires this interval
okano 13:210f4bbd0cd6 144 }
okano 23:214896356355 145
okano 23:214896356355 146 // wait 1 frame buffer update
okano 23:214896356355 147 open_transfer();
okano 23:214896356355 148 close_transfer();
okano 19:1d07d6d762a9 149 }
okano 13:210f4bbd0cd6 150
okano 25:8f6c2a094544 151
okano 25:8f6c2a094544 152 void MARY_CAMERA::test0( int res )
okano 25:8f6c2a094544 153 {
okano 25:8f6c2a094544 154 #define OVERWRITE_PARAM_NUM 12
okano 25:8f6c2a094544 155 const char over_write_param[ 5 ][ OVERWRITE_PARAM_NUM ] = {
okano 25:8f6c2a094544 156 { 0x17, 0x18, 0x32, 0x19, 0x1a, 0x03, 0x0c, 0x3e, 0x71, 0x72, 0x73, 0xa2 }, // register addr
okano 25:8f6c2a094544 157 { 0x39, 0x03, 0x80, 0x03, 0x7b, 0x02, 0x0c, 0x11, 0x35, 0x11, 0xf1, 0x52 }, // QSIF
okano 25:8f6c2a094544 158 { 0x13, 0x01, 0xb6, 0x02, 0x7a, 0x0a, 0x00, 0x00, 0x35, 0x11, 0xf0, 0x02 }, // VGA
okano 25:8f6c2a094544 159 { 0x16, 0x04, 0x80, 0x02, 0x7a, 0x0a, 0x04, 0x19, 0x35, 0x11, 0xf1, 0x02 }, // QVGA
okano 25:8f6c2a094544 160 { 0x16, 0x04, 0xa4, 0x02, 0x7a, 0x0a, 0x04, 0x1A, 0x35, 0x22, 0xf2, 0x02 }, // QQVGA
okano 25:8f6c2a094544 161 };
okano 25:8f6c2a094544 162 char d[ 2 ];
okano 25:8f6c2a094544 163
okano 25:8f6c2a094544 164 switch ( res ) {
okano 25:8f6c2a094544 165 case QCIF:
okano 25:8f6c2a094544 166 _horizontal_size = QCIF_PIXEL_PER_LINE;
okano 25:8f6c2a094544 167 _vertical_size = QCIF_LINE_PER_FRAME;
okano 25:8f6c2a094544 168 break;
okano 25:8f6c2a094544 169 case VGA:
okano 25:8f6c2a094544 170 _horizontal_size = VGA_PIXEL_PER_LINE;
okano 25:8f6c2a094544 171 _vertical_size = VGA_LINE_PER_FRAME;
okano 25:8f6c2a094544 172 break;
okano 25:8f6c2a094544 173 case QVGA:
okano 25:8f6c2a094544 174 _horizontal_size = VGA_PIXEL_PER_LINE / 2;
okano 25:8f6c2a094544 175 _vertical_size = VGA_LINE_PER_FRAME / 2;
okano 25:8f6c2a094544 176 break;
okano 25:8f6c2a094544 177 case QQVGA:
okano 25:8f6c2a094544 178 _horizontal_size = VGA_PIXEL_PER_LINE / 4;
okano 25:8f6c2a094544 179 _vertical_size = VGA_LINE_PER_FRAME / 4;
okano 25:8f6c2a094544 180 break;
okano 25:8f6c2a094544 181 }
okano 25:8f6c2a094544 182
okano 25:8f6c2a094544 183 // set camera registers
okano 25:8f6c2a094544 184
okano 25:8f6c2a094544 185 for ( int i = 0; i < OVERWRITE_PARAM_NUM; i++ ) {
okano 25:8f6c2a094544 186 d[ 0 ] = over_write_param[ 0 ][ i ];
okano 25:8f6c2a094544 187 d[ 1 ] = over_write_param[ res ][ i ];
okano 25:8f6c2a094544 188
okano 25:8f6c2a094544 189 if ( 0 != (_error_state = _i2c.write( CAM_I2C_ADDR, d, 2 )) )
okano 25:8f6c2a094544 190 break;
okano 25:8f6c2a094544 191
okano 25:8f6c2a094544 192 wait_ms( 20 ); // camera register writing requires this interval
okano 25:8f6c2a094544 193 }
okano 25:8f6c2a094544 194
okano 25:8f6c2a094544 195 if ( res == 1 ) {
okano 25:8f6c2a094544 196 d[ 0 ] = 0x3E;
okano 25:8f6c2a094544 197 d[ 1 ] = 0x1A;
okano 25:8f6c2a094544 198
okano 25:8f6c2a094544 199 if ( 0 != (_error_state = _i2c.write( CAM_I2C_ADDR, d, 2 )) )
okano 25:8f6c2a094544 200 return;
okano 25:8f6c2a094544 201
okano 25:8f6c2a094544 202 wait_ms( 20 ); // camera register writing requires this interval
okano 25:8f6c2a094544 203
okano 25:8f6c2a094544 204 d[ 0 ] = 0x3E;
okano 25:8f6c2a094544 205 d[ 1 ] = 0x11;
okano 25:8f6c2a094544 206
okano 25:8f6c2a094544 207 if ( 0 != (_error_state = _i2c.write( CAM_I2C_ADDR, d, 2 )) )
okano 25:8f6c2a094544 208 return;
okano 25:8f6c2a094544 209
okano 25:8f6c2a094544 210 wait_ms( 20 ); // camera register writing requires this interval
okano 25:8f6c2a094544 211 }
okano 25:8f6c2a094544 212 // wait 1 frame buffer update
okano 25:8f6c2a094544 213 open_transfer();
okano 25:8f6c2a094544 214 close_transfer();
okano 25:8f6c2a094544 215 }
okano 25:8f6c2a094544 216
okano 25:8f6c2a094544 217
okano 20:fa4a54e25fc4 218 void MARY_CAMERA::colorbar( SwitchState sw )
okano 20:fa4a54e25fc4 219 {
okano 20:fa4a54e25fc4 220 char s[ 2 ];
okano 22:1a923c255be6 221
okano 20:fa4a54e25fc4 222 s[ 0 ] = 0x12;
okano 20:fa4a54e25fc4 223 s[ 1 ] = sw ? 0x06 : 0x04;
okano 22:1a923c255be6 224
okano 20:fa4a54e25fc4 225 _error_state = _i2c.write( CAM_I2C_ADDR, s, 2 );
okano 20:fa4a54e25fc4 226
okano 20:fa4a54e25fc4 227 }
okano 20:fa4a54e25fc4 228
okano 19:1d07d6d762a9 229 int MARY_CAMERA::horizontal_size( void )
okano 19:1d07d6d762a9 230 {
okano 19:1d07d6d762a9 231 return _horizontal_size; // return last state of I2C access
okano 19:1d07d6d762a9 232 }
okano 2:ee71ffdf317e 233
okano 19:1d07d6d762a9 234 int MARY_CAMERA::vertical_size( void )
okano 19:1d07d6d762a9 235 {
okano 19:1d07d6d762a9 236 return _vertical_size; // return last state of I2C access
okano 0:f4584dba3bac 237 }
okano 0:f4584dba3bac 238
okano 13:210f4bbd0cd6 239 int MARY_CAMERA::ready( void )
okano 13:210f4bbd0cd6 240 {
okano 11:61a025e8ab68 241 return _error_state; // return last state of I2C access
okano 8:23d14d5254d2 242 }
okano 8:23d14d5254d2 243
okano 24:cc4271d1545f 244 extern int read_order_change;
okano 24:cc4271d1545f 245
okano 13:210f4bbd0cd6 246 void MARY_CAMERA::transfer_a_line( short *p, int line_number, int x_offset, int n_of_pixels )
okano 13:210f4bbd0cd6 247 {
okano 24:cc4271d1545f 248 #if 0
okano 24:cc4271d1545f 249
okano 9:c1e24f1bec19 250 char tmp;
okano 24:cc4271d1545f 251
okano 23:214896356355 252 if ( line_number < 0 )
okano 23:214896356355 253 return;
okano 10:82394d226c74 254
okano 11:61a025e8ab68 255 // set camera module's buffer address
okano 19:1d07d6d762a9 256 set_address( line_number * horizontal_size() * BYTE_PER_PIXEL + x_offset * BYTE_PER_PIXEL );
okano 0:f4584dba3bac 257
okano 11:61a025e8ab68 258 // put a read command, first return byte should be ignored
okano 0:f4584dba3bac 259 read_register( CAMERA_DATA_REGISTER );
okano 11:61a025e8ab68 260
okano 10:82394d226c74 261 for( int x = 0; x < n_of_pixels; x++ ) {
okano 11:61a025e8ab68 262 // perform 2 bytes read. a pixel data is in RGB565 format (16bits)
okano 11:61a025e8ab68 263 tmp = read_register( CAMERA_DATA_REGISTER ); // read lower byte
okano 11:61a025e8ab68 264 *p++ = (read_register( CAMERA_DATA_REGISTER ) << 8) | tmp; // read upper byte
okano 9:c1e24f1bec19 265 }
okano 24:cc4271d1545f 266
okano 24:cc4271d1545f 267 #else
okano 24:cc4271d1545f 268
okano 24:cc4271d1545f 269
okano 24:cc4271d1545f 270 short tmp;
okano 24:cc4271d1545f 271
okano 24:cc4271d1545f 272 if ( line_number < 0 )
okano 24:cc4271d1545f 273 return;
okano 24:cc4271d1545f 274
okano 24:cc4271d1545f 275 // set camera module's buffer address
okano 24:cc4271d1545f 276 set_address( line_number * horizontal_size() * BYTE_PER_PIXEL + x_offset * BYTE_PER_PIXEL );
okano 24:cc4271d1545f 277
okano 24:cc4271d1545f 278 // put a read command, first return byte should be ignored
okano 24:cc4271d1545f 279 read_register( CAMERA_DATA_REGISTER );
okano 24:cc4271d1545f 280
okano 24:cc4271d1545f 281
okano 24:cc4271d1545f 282 if ( read_order_change ) {
okano 24:cc4271d1545f 283
okano 24:cc4271d1545f 284 read_register( CAMERA_DATA_REGISTER );
okano 24:cc4271d1545f 285
okano 24:cc4271d1545f 286 for( int x = 0; x < n_of_pixels; x++ ) {
okano 24:cc4271d1545f 287 // perform 2 bytes read. a pixel data is in RGB565 format (16bits)
okano 24:cc4271d1545f 288 tmp = read_register( CAMERA_DATA_REGISTER ) << 8; // read lower byte
okano 24:cc4271d1545f 289 *p++ = (read_register( CAMERA_DATA_REGISTER ) << 0) | tmp; // read upper byte
okano 24:cc4271d1545f 290 }
okano 24:cc4271d1545f 291
okano 24:cc4271d1545f 292 } else {
okano 24:cc4271d1545f 293
okano 24:cc4271d1545f 294 for( int x = 0; x < n_of_pixels; x++ ) {
okano 24:cc4271d1545f 295 // perform 2 bytes read. a pixel data is in RGB565 format (16bits)
okano 24:cc4271d1545f 296 tmp = read_register( CAMERA_DATA_REGISTER ); // read lower byte
okano 24:cc4271d1545f 297 *p++ = (read_register( CAMERA_DATA_REGISTER ) << 8) | tmp; // read upper byte
okano 24:cc4271d1545f 298 }
okano 24:cc4271d1545f 299
okano 24:cc4271d1545f 300 }
okano 24:cc4271d1545f 301
okano 24:cc4271d1545f 302 #endif
okano 0:f4584dba3bac 303 }
okano 0:f4584dba3bac 304
okano 13:210f4bbd0cd6 305 void MARY_CAMERA::open_transfer( void )
okano 13:210f4bbd0cd6 306 {
okano 11:61a025e8ab68 307 // send command to pause the camera buffer update
okano 0:f4584dba3bac 308 write_register( CONTROL_DATA_REGISTER, CONTROL__PAUSE_BUFFER_UPDATE );
okano 0:f4584dba3bac 309
okano 11:61a025e8ab68 310 // read status register (first return byte should be ignored)
okano 0:f4584dba3bac 311 read_register( STATUS_REGISTER );
okano 7:942d8d0a1760 312
okano 11:61a025e8ab68 313 // wait until the status register become 0x51(ready to transfer data)
okano 11:61a025e8ab68 314 while ( 0x51 != read_register( STATUS_REGISTER ) )
okano 11:61a025e8ab68 315 ;
okano 0:f4584dba3bac 316 }
okano 0:f4584dba3bac 317
okano 13:210f4bbd0cd6 318 void MARY_CAMERA::close_transfer( void )
okano 13:210f4bbd0cd6 319 {
okano 11:61a025e8ab68 320 // send command to resume the camera buffer update
okano 0:f4584dba3bac 321 write_register( CONTROL_DATA_REGISTER, CONTROL__RESUME_BUFFER_UPDATE );
okano 0:f4584dba3bac 322
okano 11:61a025e8ab68 323 // read status register (first return byte should be ignored)
okano 0:f4584dba3bac 324 read_register( STATUS_REGISTER );
okano 7:942d8d0a1760 325
okano 11:61a025e8ab68 326 // wait until the status register become 0x50(camera updating the buffer)
okano 11:61a025e8ab68 327 while ( 0x50 != read_register( STATUS_REGISTER ) )
okano 11:61a025e8ab68 328 ;
okano 0:f4584dba3bac 329 }
okano 0:f4584dba3bac 330
okano 13:210f4bbd0cd6 331 void MARY_CAMERA::set_address( int address )
okano 13:210f4bbd0cd6 332 {
okano 11:61a025e8ab68 333 // set memory address (3 bytes)
okano 12:614be3290c47 334
okano 0:f4584dba3bac 335 write_register( MEMORY_ADDR_LOW__REGISTER, (address >> 0) & 0xFF );
okano 0:f4584dba3bac 336 write_register( MEMORY_ADDR_MID__REGISTER, (address >> 8) & 0xFF );
okano 0:f4584dba3bac 337 write_register( MEMORY_ADDR_HIGH_REGISTER, (address >> 16) & 0xFF );
okano 0:f4584dba3bac 338 }
okano 0:f4584dba3bac 339
okano 13:210f4bbd0cd6 340 void MARY_CAMERA::write_register( char reg, char value )
okano 13:210f4bbd0cd6 341 {
okano 11:61a025e8ab68 342 // camera register write
okano 12:614be3290c47 343
okano 11:61a025e8ab68 344 send_spi( COMMAND_WRITE | reg ); // send command and register number
okano 11:61a025e8ab68 345 send_spi( value ); // send register value
okano 11:61a025e8ab68 346 }
okano 11:61a025e8ab68 347
okano 13:210f4bbd0cd6 348 int MARY_CAMERA::read_register( char reg )
okano 13:210f4bbd0cd6 349 {
okano 11:61a025e8ab68 350 // camera register read
okano 11:61a025e8ab68 351 // returning current data in SPI buffer (data returned by previous command)
okano 11:61a025e8ab68 352
okano 11:61a025e8ab68 353 return ( send_spi( COMMAND_READ | reg | ((reg == CAMERA_DATA_REGISTER) ? COMMAND_ADDR_INCREMENT : 0x00) ) );
okano 11:61a025e8ab68 354 }
okano 10:82394d226c74 355
okano 13:210f4bbd0cd6 356 int MARY_CAMERA::send_spi( char data )
okano 13:210f4bbd0cd6 357 {
okano 0:f4584dba3bac 358 int tmp;
okano 12:614be3290c47 359
okano 11:61a025e8ab68 360 // SPI access
okano 0:f4584dba3bac 361
okano 4:cb0ef3fd89c9 362 _cs = 0;
okano 4:cb0ef3fd89c9 363 tmp = _spi.write( data );
okano 4:cb0ef3fd89c9 364 _cs = 1;
okano 12:614be3290c47 365
okano 0:f4584dba3bac 366 return ( tmp );
okano 0:f4584dba3bac 367 }