Matt Briggs / Mbed OS xDotBridge_update_dev_latest

Fork to see if I can get working

Dependencies:   BufferedSerial OneWire WinbondSPIFlash libxDot-dev-mbed5-deprecated

Fork of xDotBridge_update_test20180823 by Matt Briggs

xDotBridge/src/main.cpp@38:8a512e23d99e, 2017-01-26 (annotated)

Committer:
Matt Briggs
Date:
Thu Jan 26 16:23:45 2017 -0700
Revision:
38:8a512e23d99e
Parent:
37:31f8e9c5d075
Child:
39:64f79fa6e3cc
Added stubs for refactor with BaseboardIO and CommProtocol.

Added documentation to to DS2408

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Matt Briggs 34:5618603e5fc3 1 #include <math.h>
Matt Briggs 22:9453658b8d4b 2 #include "config.h"
Matt Briggs 30:2e673a672884 3 #include "xdot_flash.h"
Mike Fiore 11:d2e31743433a 4 #include "dot_util.h"
Mike Fiore 14:19fae4509473 5 #include "RadioEvent.h"
Matt Briggs 34:5618603e5fc3 6 #include <OneWire.h>
Matt Briggs 22:9453658b8d4b 7
mfiore 17:d4f82e16de5f 8 /////////////////////////////////////////////////////////////////////////////
mfiore 17:d4f82e16de5f 9 // -------------------- DOT LIBRARY REQUIRED ------------------------------//
mfiore 17:d4f82e16de5f 10 // * Because these example programs can be used for both mDot and xDot //
mfiore 17:d4f82e16de5f 11 // devices, the LoRa stack is not included. The libmDot library should //
mfiore 17:d4f82e16de5f 12 // be imported if building for mDot devices. The libxDot library //
mfiore 17:d4f82e16de5f 13 // should be imported if building for xDot devices. //
mfiore 17:d4f82e16de5f 14 // * https://developer.mbed.org/teams/MultiTech/code/libmDot-dev-mbed5/ //
mfiore 17:d4f82e16de5f 15 // * https://developer.mbed.org/teams/MultiTech/code/libmDot-mbed5/ //
mfiore 17:d4f82e16de5f 16 // * https://developer.mbed.org/teams/MultiTech/code/libxDot-dev-mbed5/ //
mfiore 17:d4f82e16de5f 17 // * https://developer.mbed.org/teams/MultiTech/code/libxDot-mbed5/ //
mfiore 17:d4f82e16de5f 18 /////////////////////////////////////////////////////////////////////////////
mfiore 17:d4f82e16de5f 19
Mike Fiore 11:d2e31743433a 20 /////////////////////////////////////////////////////////////
Mike Fiore 11:d2e31743433a 21 // * these options must match between the two devices in //
Mike Fiore 11:d2e31743433a 22 // order for communication to be successful
Mike Fiore 11:d2e31743433a 23 /////////////////////////////////////////////////////////////
Mike Fiore 11:d2e31743433a 24 static uint8_t network_address[] = { 0x01, 0x02, 0x03, 0x04 };
Mike Fiore 11:d2e31743433a 25 static uint8_t network_session_key[] = { 0x01, 0x02, 0x03, 0x04, 0x01, 0x02, 0x03, 0x04, 0x01, 0x02, 0x03, 0x04, 0x01, 0x02, 0x03, 0x04 };
mbriggs_vortex 19:75b28b4117cc 26 static uint8_t data_session_key[] = { 0x01, 0x02, 0x03, 0x04, 0x01, 0x02, 0x03, 0x04, 0x01, 0x02, 0x03, 0x04, 0x01, 0x02, 0x03, 0x04 };
Mike Fiore 11:d2e31743433a 27
Matt Briggs 26:9411b26a5084 28 // wireless bridge protocol
Matt Briggs 31:9c535a708ae9 29 const uint8_t TX_PWR = 20; // 20 dBm
Matt Briggs 31:9c535a708ae9 30 const float RX_SLEEP_TIME = 2000; // ms (one second resolution, min 2 seconds)
Matt Briggs 31:9c535a708ae9 31 const uint8_t TX_TIME = 30; // in ms
Matt Briggs 26:9411b26a5084 32
Matt Briggs 31:9c535a708ae9 33 //const uint8_t maxPayloadSize = 10; // Number of bytes (used for toa calcultion)
Matt Briggs 31:9c535a708ae9 34
Matt Briggs 31:9c535a708ae9 35 ///////////////////////
Matt Briggs 31:9c535a708ae9 36 // I/O Configuration //
Matt Briggs 31:9c535a708ae9 37 ///////////////////////
Matt Briggs 29:e05e35976cfe 38 DigitalOut led1(GPIO0);
Matt Briggs 29:e05e35976cfe 39 AnalogIn an1(GPIO1);
Matt Briggs 29:e05e35976cfe 40 AnalogIn an2(GPIO2);
Matt Briggs 29:e05e35976cfe 41
Matt Briggs 29:e05e35976cfe 42 // Inputs
Matt Briggs 37:31f8e9c5d075 43 //DigitalIn gpio3(GPIO3);
Matt Briggs 31:9c535a708ae9 44 //DigitalIn wake_DOUT(WAKE);
Matt Briggs 37:31f8e9c5d075 45 //DigitalIn i2cOut1(I2C1_SCL);
Matt Briggs 37:31f8e9c5d075 46 //DigitalIn i2cOut2(I2C1_SDA);
Matt Briggs 38:8a512e23d99e 47 InterruptIn intTest(I2C1_SDA);
Matt Briggs 33:c7bb3fbc024a 48 //DigitalIn uartOut1(UART1_CTS);
Matt Briggs 33:c7bb3fbc024a 49 //DigitalIn uartOut2(UART1_RTS);
Matt Briggs 33:c7bb3fbc024a 50 //DigitalIn jtag_gpio1(SWDIO);
Matt Briggs 33:c7bb3fbc024a 51 //DigitalIn jtag_gpio2(SWCLK);
Matt Briggs 29:e05e35976cfe 52
Matt Briggs 29:e05e35976cfe 53 // Outputs
Matt Briggs 29:e05e35976cfe 54 //DigitalOut gpio3(GPIO3);
Matt Briggs 29:e05e35976cfe 55 ////DigitalOut wake_DOUT(WAKE);
Matt Briggs 29:e05e35976cfe 56 //DigitalOut i2cOut1(I2C1_SCL);
Matt Briggs 29:e05e35976cfe 57 //DigitalOut i2cOut2(I2C1_SDA);
Matt Briggs 29:e05e35976cfe 58 //
Matt Briggs 29:e05e35976cfe 59 //DigitalOut uartOut1(UART1_CTS);
Matt Briggs 29:e05e35976cfe 60 //DigitalOut uartOut2(UART1_RTS);
Matt Briggs 29:e05e35976cfe 61
Mike Fiore 11:d2e31743433a 62 mDot* dot = NULL;
Mike Fiore 11:d2e31743433a 63
Mike Fiore 11:d2e31743433a 64 Serial pc(USBTX, USBRX);
Mike Fiore 11:d2e31743433a 65
Mike Fiore 11:d2e31743433a 66 int main() {
Matt Briggs 31:9c535a708ae9 67 unsigned int wakeMode;
Matt Briggs 31:9c535a708ae9 68 RadioEvent events; // Custom event handler for automatically displaying RX data
Mike Fiore 11:d2e31743433a 69 uint32_t tx_frequency;
Mike Fiore 11:d2e31743433a 70 uint8_t tx_datarate;
Mike Fiore 11:d2e31743433a 71 uint8_t tx_power;
Mike Fiore 11:d2e31743433a 72 uint8_t frequency_band;
Mike Fiore 11:d2e31743433a 73
Mike Fiore 11:d2e31743433a 74 pc.baud(115200);
Mike Fiore 11:d2e31743433a 75
Matt Briggs 27:6b68ff715ae1 76 mts::MTSLog::setLogLevel(mts::MTSLog::TRACE_LEVEL);
Mike Fiore 11:d2e31743433a 77
Mike Fiore 11:d2e31743433a 78 dot = mDot::getInstance();
Mike Fiore 11:d2e31743433a 79
Mike Fiore 16:a3832552dfe1 80 logInfo("mbed-os library version: %d", MBED_LIBRARY_VERSION);
Mike Fiore 16:a3832552dfe1 81
Mike Fiore 12:ec9768677cea 82 // start from a well-known state
Mike Fiore 12:ec9768677cea 83 logInfo("defaulting Dot configuration");
Mike Fiore 12:ec9768677cea 84 dot->resetConfig();
Mike Fiore 12:ec9768677cea 85
Mike Fiore 11:d2e31743433a 86 // make sure library logging is turned on
Matt Briggs 27:6b68ff715ae1 87 dot->setLogLevel(mts::MTSLog::INFO_LEVEL);
Mike Fiore 11:d2e31743433a 88
Mike Fiore 11:d2e31743433a 89 // attach the custom events handler
Mike Fiore 11:d2e31743433a 90 dot->setEvents(&events);
Mike Fiore 11:d2e31743433a 91
Matt Briggs 31:9c535a708ae9 92 // Setup programmable voltage detector
Matt Briggs 31:9c535a708ae9 93 // PVD_LEVEL0 Falling 1.85
Matt Briggs 31:9c535a708ae9 94 // PVD_LEVEL1 Falling 2.04
Matt Briggs 31:9c535a708ae9 95 // PVD_LEVEL2 Falling 2.24
Matt Briggs 31:9c535a708ae9 96 // PVD_LEVEL3 Falling 2.44
Matt Briggs 31:9c535a708ae9 97 // PVD_LEVEL4 Falling 2.64
Matt Briggs 31:9c535a708ae9 98 // PVD_LEVEL5 Falling 2.84
Matt Briggs 31:9c535a708ae9 99 // PVD_LEVEL6 Falling 3.05
Matt Briggs 31:9c535a708ae9 100 PWR_PVDTypeDef pvdConfig;
Matt Briggs 31:9c535a708ae9 101 pvdConfig.Mode = PWR_PVD_MODE_NORMAL;
Matt Briggs 31:9c535a708ae9 102 pvdConfig.PVDLevel = PWR_PVDLEVEL_5;
Matt Briggs 31:9c535a708ae9 103
Matt Briggs 31:9c535a708ae9 104 HAL_PWR_ConfigPVD(&pvdConfig);
Matt Briggs 31:9c535a708ae9 105 HAL_PWR_EnablePVD();
Matt Briggs 31:9c535a708ae9 106 logInfo("Programmable Voltage Detector set for level: %d", pvdConfig.PVDLevel);
Matt Briggs 31:9c535a708ae9 107
Matt Briggs 31:9c535a708ae9 108 // TODO setup IO here
Matt Briggs 31:9c535a708ae9 109
Mike Fiore 11:d2e31743433a 110 // update configuration if necessary
Matt Briggs 31:9c535a708ae9 111 logInfo("Setting up peer to peer configuration");
Mike Fiore 11:d2e31743433a 112 if (dot->getJoinMode() != mDot::PEER_TO_PEER) {
Mike Fiore 11:d2e31743433a 113 logInfo("changing network join mode to PEER_TO_PEER");
Mike Fiore 11:d2e31743433a 114 if (dot->setJoinMode(mDot::PEER_TO_PEER) != mDot::MDOT_OK) {
Mike Fiore 11:d2e31743433a 115 logError("failed to set network join mode to PEER_TO_PEER");
Mike Fiore 11:d2e31743433a 116 }
Mike Fiore 11:d2e31743433a 117 }
Mike Fiore 11:d2e31743433a 118 frequency_band = dot->getFrequencyBand();
Mike Fiore 11:d2e31743433a 119 switch (frequency_band) {
Mike Fiore 11:d2e31743433a 120 case mDot::FB_EU868:
Mike Fiore 11:d2e31743433a 121 // 250kHz channels achieve higher throughput
Mike Fiore 11:d2e31743433a 122 // DR6 : SF7 @ 250kHz
Mike Fiore 11:d2e31743433a 123 // DR0 - DR5 (125kHz channels) available but much slower
Mike Fiore 11:d2e31743433a 124 tx_frequency = 869850000;
Mike Fiore 11:d2e31743433a 125 tx_datarate = mDot::DR6;
Mike Fiore 11:d2e31743433a 126 // the 869850000 frequency is 100% duty cycle if the total power is under 7 dBm - tx power 4 + antenna gain 3 = 7
Mike Fiore 11:d2e31743433a 127 tx_power = 4;
Mike Fiore 11:d2e31743433a 128 break;
Mike Fiore 11:d2e31743433a 129 case mDot::FB_US915:
Mike Fiore 11:d2e31743433a 130 case mDot::FB_AU915:
Mike Fiore 11:d2e31743433a 131 default:
Mike Fiore 11:d2e31743433a 132 // 500kHz channels achieve highest throughput
Mike Fiore 11:d2e31743433a 133 // DR8 : SF12 @ 500kHz
Mike Fiore 11:d2e31743433a 134 // DR9 : SF11 @ 500kHz
Mike Fiore 11:d2e31743433a 135 // DR10 : SF10 @ 500kHz
Mike Fiore 11:d2e31743433a 136 // DR11 : SF9 @ 500kHz
Mike Fiore 11:d2e31743433a 137 // DR12 : SF8 @ 500kHz
Mike Fiore 11:d2e31743433a 138 // DR13 : SF7 @ 500kHz
Mike Fiore 11:d2e31743433a 139 // DR0 - DR3 (125kHz channels) available but much slower
Mike Fiore 11:d2e31743433a 140 tx_frequency = 915500000;
Mike Fiore 11:d2e31743433a 141 tx_datarate = mDot::DR13;
Mike Fiore 11:d2e31743433a 142 // 915 bands have no duty cycle restrictions, set tx power to max
Mike Fiore 11:d2e31743433a 143 tx_power = 20;
Mike Fiore 11:d2e31743433a 144 break;
Mike Fiore 11:d2e31743433a 145 }
Mike Fiore 11:d2e31743433a 146 // in PEER_TO_PEER mode there is no join request/response transaction
Mike Fiore 11:d2e31743433a 147 // as long as both Dots are configured correctly, they should be able to communicate
Mike Fiore 11:d2e31743433a 148 update_peer_to_peer_config(network_address, network_session_key, data_session_key, tx_frequency, tx_datarate, tx_power);
Mike Fiore 11:d2e31743433a 149
Matt Briggs 24:fdf87e4b72e5 150 ///////////////////////////////
Matt Briggs 24:fdf87e4b72e5 151 // Transmitter Configuration //
Matt Briggs 24:fdf87e4b72e5 152 ///////////////////////////////
Matt Briggs 27:6b68ff715ae1 153 #if BRIDGE_TX_BRUTE
Matt Briggs 24:fdf87e4b72e5 154 wakeMode = mDot::INTERRUPT;
Matt Briggs 24:fdf87e4b72e5 155 #endif
Matt Briggs 24:fdf87e4b72e5 156
Matt Briggs 24:fdf87e4b72e5 157 ////////////////////////////
Matt Briggs 24:fdf87e4b72e5 158 // Receiver Configuration //
Matt Briggs 24:fdf87e4b72e5 159 ////////////////////////////
Matt Briggs 27:6b68ff715ae1 160 #if BRIDGE_RX_BRUTE
Matt Briggs 24:fdf87e4b72e5 161 wakeMode = mDot::RTC_ALARM_OR_INTERRUPT;
Matt Briggs 24:fdf87e4b72e5 162 #endif
Matt Briggs 24:fdf87e4b72e5 163
Matt Briggs 24:fdf87e4b72e5 164 // Common Configuration
Matt Briggs 33:c7bb3fbc024a 165 dot->setTxWait(false);
Matt Briggs 33:c7bb3fbc024a 166 dot->setAck(0); // Disable Ack
Matt Briggs 25:fea776239709 167 dot->setWakePin(WAKE); // Use the wake pin as sleep interrupt
Matt Briggs 25:fea776239709 168 dot->setClass("C"); // Set class C
Matt Briggs 31:9c535a708ae9 169 dot->setTxPower(TX_PWR);
Matt Briggs 24:fdf87e4b72e5 170
Mike Fiore 11:d2e31743433a 171 // save changes to configuration
Mike Fiore 11:d2e31743433a 172 logInfo("saving configuration");
Mike Fiore 11:d2e31743433a 173 if (!dot->saveConfig()) {
Mike Fiore 11:d2e31743433a 174 logError("failed to save configuration");
Mike Fiore 11:d2e31743433a 175 }
Mike Fiore 11:d2e31743433a 176
Mike Fiore 11:d2e31743433a 177 // display configuration
Mike Fiore 11:d2e31743433a 178 display_config();
Mike Fiore 11:d2e31743433a 179
Matt Briggs 26:9411b26a5084 180
Matt Briggs 31:9c535a708ae9 181 unsigned int nTimesToTx = ceil(RX_SLEEP_TIME / ((float)TX_TIME));
Matt Briggs 31:9c535a708ae9 182 logInfo("RX_SLEEP_TIME %f, timeOnAir %lu, nTimesToTx %lu", RX_SLEEP_TIME, TX_TIME, nTimesToTx);
Matt Briggs 26:9411b26a5084 183
mbriggs_vortex 23:4ed894108882 184 uint16_t seqNum=0;
Matt Briggs 26:9411b26a5084 185 uint32_t cDwnLink = dot->getDownLinkCounter();
Matt Briggs 30:2e673a672884 186
Mike Fiore 11:d2e31743433a 187 while (true) {
Matt Briggs 25:fea776239709 188 std::vector<uint8_t> data;
Matt Briggs 31:9c535a708ae9 189 led1=0;
Mike Fiore 11:d2e31743433a 190
Mike Fiore 11:d2e31743433a 191 // join network if not joined
Mike Fiore 11:d2e31743433a 192 if (!dot->getNetworkJoinStatus()) {
Mike Fiore 11:d2e31743433a 193 join_network();
Mike Fiore 11:d2e31743433a 194 }
Mike Fiore 11:d2e31743433a 195
Matt Briggs 31:9c535a708ae9 196 //////////////////////
Matt Briggs 31:9c535a708ae9 197 // Common main loop //
Matt Briggs 31:9c535a708ae9 198 //////////////////////
Matt Briggs 31:9c535a708ae9 199
Matt Briggs 31:9c535a708ae9 200 // TODO sample rotary
Matt Briggs 31:9c535a708ae9 201 // TODO sample DIPs
Matt Briggs 31:9c535a708ae9 202
Matt Briggs 27:6b68ff715ae1 203 //////////////////////////////////////////
Matt Briggs 27:6b68ff715ae1 204 // Brute Protocol Transmitter main loop //
Matt Briggs 27:6b68ff715ae1 205 //////////////////////////////////////////
Matt Briggs 27:6b68ff715ae1 206 #if BRIDGE_TX_BRUTE
Matt Briggs 31:9c535a708ae9 207 #if LED_FEEDBACK
Matt Briggs 26:9411b26a5084 208 led1=1;
Matt Briggs 31:9c535a708ae9 209 #endif
Matt Briggs 31:9c535a708ae9 210 // TODO check for CC_IN
Matt Briggs 31:9c535a708ae9 211
Matt Briggs 25:fea776239709 212 data.push_back((seqNum >> 8) & 0xFF);
Matt Briggs 25:fea776239709 213 data.push_back(seqNum & 0xFF);
Matt Briggs 27:6b68ff715ae1 214 logInfo("Starting TX. Time: %lu, seqNum: %lu", us_ticker_read(), seqNum);
Matt Briggs 26:9411b26a5084 215 for(uint i=0;i<nTimesToTx;++i) {
Matt Briggs 27:6b68ff715ae1 216 dot->send(data);
Matt Briggs 26:9411b26a5084 217 }
mbriggs_vortex 23:4ed894108882 218 seqNum++;
Matt Briggs 25:fea776239709 219 led1=0;
Matt Briggs 27:6b68ff715ae1 220 logInfo("Finished TX. Time: %lu", us_ticker_read());
mbriggs_vortex 23:4ed894108882 221
Matt Briggs 28:b14b2926e916 222 sleep_save_io();
Matt Briggs 28:b14b2926e916 223 sleep_configure_io();
Matt Briggs 24:fdf87e4b72e5 224 dot->sleep(0, wakeMode, false); // Go to sleep until wake button
Matt Briggs 28:b14b2926e916 225 sleep_restore_io();
Matt Briggs 24:fdf87e4b72e5 226 #endif
Matt Briggs 27:6b68ff715ae1 227
Matt Briggs 27:6b68ff715ae1 228 ///////////////////////////////////////
Matt Briggs 27:6b68ff715ae1 229 // Brute Protocol Receiver main loop //
Matt Briggs 27:6b68ff715ae1 230 ///////////////////////////////////////
Matt Briggs 27:6b68ff715ae1 231 #if BRIDGE_RX_BRUTE
Matt Briggs 27:6b68ff715ae1 232 logInfo("Waiting for new message current DLC: %d, Time %d", cDwnLink, us_ticker_read());
Matt Briggs 31:9c535a708ae9 233 wait(TX_TIME/1000.0); // Wait TX_TIME
Matt Briggs 31:9c535a708ae9 234
Matt Briggs 31:9c535a708ae9 235 // TODO need to figure out what to do when DLC get resets
Matt Briggs 31:9c535a708ae9 236
Matt Briggs 26:9411b26a5084 237 if (cDwnLink < dot->getDownLinkCounter()) {
Matt Briggs 26:9411b26a5084 238 cDwnLink = dot->getDownLinkCounter();
Matt Briggs 26:9411b26a5084 239 dot->recv(data);
Matt Briggs 26:9411b26a5084 240 std::string dataStr(data.begin(), data.end());
Matt Briggs 26:9411b26a5084 241 logInfo("Got msg num: %d, payload: %s", seqNum, dataStr.c_str());
Matt Briggs 31:9c535a708ae9 242 // TODO add CC_OUT code here
Matt Briggs 26:9411b26a5084 243 seqNum++;
Matt Briggs 31:9c535a708ae9 244 #if LED_FEEDBACK
Matt Briggs 31:9c535a708ae9 245 led1 = 1;
Matt Briggs 26:9411b26a5084 246 wait(0.5);
Matt Briggs 31:9c535a708ae9 247 #endif
Matt Briggs 25:fea776239709 248 }
Matt Briggs 26:9411b26a5084 249 led1=0;
Matt Briggs 27:6b68ff715ae1 250 logInfo("Sleeping. Time %d", us_ticker_read());
Matt Briggs 28:b14b2926e916 251 sleep_save_io();
Matt Briggs 28:b14b2926e916 252 sleep_configure_io();
Matt Briggs 31:9c535a708ae9 253 // TODO maybe add if statement here to prevent double hits by sleeping for a longer time
Matt Briggs 26:9411b26a5084 254 dot->sleep(2, wakeMode, false); // Go to sleep until wake button
Matt Briggs 28:b14b2926e916 255 sleep_restore_io();
Matt Briggs 25:fea776239709 256 #endif
Matt Briggs 31:9c535a708ae9 257
Matt Briggs 29:e05e35976cfe 258 //////////////
Matt Briggs 29:e05e35976cfe 259 // I/O Play //
Matt Briggs 29:e05e35976cfe 260 //////////////
Matt Briggs 29:e05e35976cfe 261
Matt Briggs 38:8a512e23d99e 262 // Check interrupt
Matt Briggs 38:8a512e23d99e 263
Matt Briggs 31:9c535a708ae9 264 // // Check Analog
Matt Briggs 31:9c535a708ae9 265 // logInfo("Read AN1/GPIO1: %f", an1.read());
Matt Briggs 31:9c535a708ae9 266 // logInfo("Read AN2/GPIO2: %f", an2.read()); // Ranges from 0.0 to 1.0
Matt Briggs 31:9c535a708ae9 267 //
Matt Briggs 31:9c535a708ae9 268 // // check inputs
Matt Briggs 31:9c535a708ae9 269 // logInfo("Read GPIO3: %d", gpio3.read());
Matt Briggs 31:9c535a708ae9 270 //// logInfo("Read wake_DOUT: %d", wake_DOUT.read());
Matt Briggs 31:9c535a708ae9 271 // logInfo("Read i2cOut1: %d", i2cOut1.read()); // Appears to be pulled up
Matt Briggs 31:9c535a708ae9 272 // logInfo("Read i2cOut2: %d", i2cOut2.read()); // Appears to be pulled up
Matt Briggs 31:9c535a708ae9 273 // logInfo("Read uartOut1: %d", uartOut1.read());
Matt Briggs 31:9c535a708ae9 274 // logInfo("Read uartOut2: %d", uartOut2.read());
Matt Briggs 31:9c535a708ae9 275 //
Matt Briggs 31:9c535a708ae9 276 // logInfo("Read jtag_gpio1: %d", jtag_gpio1.read());
Matt Briggs 31:9c535a708ae9 277 // logInfo("Read jtag_gpio2: %d", jtag_gpio2.read());
Matt Briggs 31:9c535a708ae9 278 //
Matt Briggs 31:9c535a708ae9 279 // if (jtag_gpio1.read() == 0) {
Matt Briggs 31:9c535a708ae9 280 // led1 = 1;
Matt Briggs 31:9c535a708ae9 281 // }
Matt Briggs 31:9c535a708ae9 282 // else {
Matt Briggs 31:9c535a708ae9 283 // led1 = 0;
Matt Briggs 31:9c535a708ae9 284 // }
Matt Briggs 29:e05e35976cfe 285
Matt Briggs 29:e05e35976cfe 286 // check digital outputs
Matt Briggs 29:e05e35976cfe 287 // led1 = !led1;
Matt Briggs 29:e05e35976cfe 288 // gpio3 = !gpio3;
Matt Briggs 29:e05e35976cfe 289 //// wake_DOUT = !wake_DOUT;
Matt Briggs 29:e05e35976cfe 290 // i2cOut1 = !i2cOut1;
Matt Briggs 29:e05e35976cfe 291 // i2cOut2 = !i2cOut2;
Matt Briggs 29:e05e35976cfe 292 //
Matt Briggs 29:e05e35976cfe 293 // uartOut1 = !uartOut1;
Matt Briggs 29:e05e35976cfe 294 // uartOut2 = !uartOut2;
Matt Briggs 29:e05e35976cfe 295
Matt Briggs 31:9c535a708ae9 296 // logInfo("================================");
Matt Briggs 31:9c535a708ae9 297 // wait(1.0);
Matt Briggs 34:5618603e5fc3 298 //////////////////
Matt Briggs 34:5618603e5fc3 299 // OneWire Play //
Matt Briggs 34:5618603e5fc3 300 //////////////////
Matt Briggs 34:5618603e5fc3 301
Matt Briggs 38:8a512e23d99e 302 // logInfo("Starting OneWire Play");
Matt Briggs 38:8a512e23d99e 303 // OneWire owMaster(I2C_SDA);
Matt Briggs 38:8a512e23d99e 304 // uint8_t addr[8];
Matt Briggs 38:8a512e23d99e 305 // uint8_t result;
Matt Briggs 38:8a512e23d99e 306 //
Matt Briggs 38:8a512e23d99e 307 // // Search Bus
Matt Briggs 38:8a512e23d99e 308 // logInfo("Starting OneWire Search");
Matt Briggs 38:8a512e23d99e 309 // do {
Matt Briggs 38:8a512e23d99e 310 // result = owMaster.search(addr);
Matt Briggs 38:8a512e23d99e 311 // logInfo("ROM Addr: %02x:%02x:%02x:%02x:%02x:%02x:%02x%02x\n",
Matt Briggs 38:8a512e23d99e 312 // addr[7],addr[6],addr[5],addr[4],addr[3],addr[2],addr[1],addr[0]);
Matt Briggs 38:8a512e23d99e 313 // } while (result == 1);
Matt Briggs 38:8a512e23d99e 314 // logInfo("Finished OneWire Search");
Matt Briggs 38:8a512e23d99e 315 // wait(1.0);
Matt Briggs 38:8a512e23d99e 316 //
Matt Briggs 38:8a512e23d99e 317 // uint8_t pioStateAddr[] = {0x88, 0x00};
Matt Briggs 38:8a512e23d99e 318 // uint8_t pioLatchAddr[] = {0x89, 0x00};
Matt Briggs 38:8a512e23d99e 319 // uint8_t printAddr = 0x88;
Matt Briggs 38:8a512e23d99e 320 // while (true) {
Matt Briggs 38:8a512e23d99e 321 // owMaster.reset();
Matt Briggs 38:8a512e23d99e 322 // owMaster.select(addr);
Matt Briggs 38:8a512e23d99e 323 // owMaster.write(0xF0); // Read Register Command
Matt Briggs 38:8a512e23d99e 324 // owMaster.write_bytes(pioStateAddr, 2); // Write 2 byte addr
Matt Briggs 38:8a512e23d99e 325 // printAddr = 0x88;
Matt Briggs 38:8a512e23d99e 326 // for (int i=0;i<8;i++) {
Matt Briggs 38:8a512e23d99e 327 // result = owMaster.read();
Matt Briggs 38:8a512e23d99e 328 // logInfo("%02x Reg Value: %02x\n", printAddr++, result);
Matt Briggs 38:8a512e23d99e 329 // }
Matt Briggs 38:8a512e23d99e 330 //
Matt Briggs 38:8a512e23d99e 331 // owMaster.reset();
Matt Briggs 38:8a512e23d99e 332 // owMaster.select(addr);
Matt Briggs 38:8a512e23d99e 333 // owMaster.write(0xF0); // Read Register Command
Matt Briggs 38:8a512e23d99e 334 // owMaster.write_bytes(pioLatchAddr, 2); // Write 2 byte addr
Matt Briggs 38:8a512e23d99e 335 // result = owMaster.read();
Matt Briggs 38:8a512e23d99e 336 // logInfo("Latch Reg Value: %02x\n", result);
Matt Briggs 38:8a512e23d99e 337 // // TODO try reading inverted 16-bit CRC
Matt Briggs 38:8a512e23d99e 338 //
Matt Briggs 38:8a512e23d99e 339 // wait(1.0);
Matt Briggs 38:8a512e23d99e 340 // // Try write
Matt Briggs 38:8a512e23d99e 341 // owMaster.reset();
Matt Briggs 38:8a512e23d99e 342 // owMaster.select(addr);
Matt Briggs 38:8a512e23d99e 343 // owMaster.write(0x5A); // Channel Access Write Command
Matt Briggs 38:8a512e23d99e 344 // uint8_t val = ~0xAA;
Matt Briggs 38:8a512e23d99e 345 // owMaster.write(val); // Pull-down all even bits
Matt Briggs 38:8a512e23d99e 346 // owMaster.write(~val); // Pull-down all even bits
Matt Briggs 38:8a512e23d99e 347 // result = owMaster.read();
Matt Briggs 38:8a512e23d99e 348 // logInfo("Confirm after write value: %02x, expected %02x\n", result, 0xAA);
Matt Briggs 38:8a512e23d99e 349 //
Matt Briggs 38:8a512e23d99e 350 // // Check if the read back is just a latch reg thing or a true logic state
Matt Briggs 38:8a512e23d99e 351 // wait(1.0);
Matt Briggs 36:0fb61acf7fae 352 }
Mike Fiore 11:d2e31743433a 353 }
Mike Fiore 11:d2e31743433a 354
Mike Fiore 11:d2e31743433a 355 return 0;
Mike Fiore 11:d2e31743433a 356 }
Mike Fiore 11:d2e31743433a 357
Matt Briggs 27:6b68ff715ae1 358