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Fork to see if I can get working
Dependencies: BufferedSerial OneWire WinbondSPIFlash libxDot-dev-mbed5-deprecated
Fork of xDotBridge_update_test20180823 by
xDotBridge/src/main.cpp@37:31f8e9c5d075, 2017-01-25 (annotated)
- Committer:
- Matt Briggs
- Date:
- Wed Jan 25 16:22:14 2017 -0700
- Revision:
- 37:31f8e9c5d075
- Parent:
- 36:0fb61acf7fae
- Child:
- 38:8a512e23d99e
Working example of one wire
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
Matt Briggs | 34:5618603e5fc3 | 1 | #include <math.h> |
Matt Briggs | 22:9453658b8d4b | 2 | #include "config.h" |
Matt Briggs | 30:2e673a672884 | 3 | #include "xdot_flash.h" |
Mike Fiore |
11:d2e31743433a | 4 | #include "dot_util.h" |
Mike Fiore |
14:19fae4509473 | 5 | #include "RadioEvent.h" |
Matt Briggs | 34:5618603e5fc3 | 6 | #include <OneWire.h> |
Matt Briggs | 22:9453658b8d4b | 7 | |
mfiore | 17:d4f82e16de5f | 8 | ///////////////////////////////////////////////////////////////////////////// |
mfiore | 17:d4f82e16de5f | 9 | // -------------------- DOT LIBRARY REQUIRED ------------------------------// |
mfiore | 17:d4f82e16de5f | 10 | // * Because these example programs can be used for both mDot and xDot // |
mfiore | 17:d4f82e16de5f | 11 | // devices, the LoRa stack is not included. The libmDot library should // |
mfiore | 17:d4f82e16de5f | 12 | // be imported if building for mDot devices. The libxDot library // |
mfiore | 17:d4f82e16de5f | 13 | // should be imported if building for xDot devices. // |
mfiore | 17:d4f82e16de5f | 14 | // * https://developer.mbed.org/teams/MultiTech/code/libmDot-dev-mbed5/ // |
mfiore | 17:d4f82e16de5f | 15 | // * https://developer.mbed.org/teams/MultiTech/code/libmDot-mbed5/ // |
mfiore | 17:d4f82e16de5f | 16 | // * https://developer.mbed.org/teams/MultiTech/code/libxDot-dev-mbed5/ // |
mfiore | 17:d4f82e16de5f | 17 | // * https://developer.mbed.org/teams/MultiTech/code/libxDot-mbed5/ // |
mfiore | 17:d4f82e16de5f | 18 | ///////////////////////////////////////////////////////////////////////////// |
mfiore | 17:d4f82e16de5f | 19 | |
Mike Fiore |
11:d2e31743433a | 20 | ///////////////////////////////////////////////////////////// |
Mike Fiore |
11:d2e31743433a | 21 | // * these options must match between the two devices in // |
Mike Fiore |
11:d2e31743433a | 22 | // order for communication to be successful |
Mike Fiore |
11:d2e31743433a | 23 | ///////////////////////////////////////////////////////////// |
Mike Fiore |
11:d2e31743433a | 24 | static uint8_t network_address[] = { 0x01, 0x02, 0x03, 0x04 }; |
Mike Fiore |
11:d2e31743433a | 25 | static uint8_t network_session_key[] = { 0x01, 0x02, 0x03, 0x04, 0x01, 0x02, 0x03, 0x04, 0x01, 0x02, 0x03, 0x04, 0x01, 0x02, 0x03, 0x04 }; |
mbriggs_vortex | 19:75b28b4117cc | 26 | static uint8_t data_session_key[] = { 0x01, 0x02, 0x03, 0x04, 0x01, 0x02, 0x03, 0x04, 0x01, 0x02, 0x03, 0x04, 0x01, 0x02, 0x03, 0x04 }; |
Mike Fiore |
11:d2e31743433a | 27 | |
Matt Briggs | 26:9411b26a5084 | 28 | // wireless bridge protocol |
Matt Briggs | 31:9c535a708ae9 | 29 | const uint8_t TX_PWR = 20; // 20 dBm |
Matt Briggs | 31:9c535a708ae9 | 30 | const float RX_SLEEP_TIME = 2000; // ms (one second resolution, min 2 seconds) |
Matt Briggs | 31:9c535a708ae9 | 31 | const uint8_t TX_TIME = 30; // in ms |
Matt Briggs | 26:9411b26a5084 | 32 | |
Matt Briggs | 31:9c535a708ae9 | 33 | //const uint8_t maxPayloadSize = 10; // Number of bytes (used for toa calcultion) |
Matt Briggs | 31:9c535a708ae9 | 34 | |
Matt Briggs | 31:9c535a708ae9 | 35 | /////////////////////// |
Matt Briggs | 31:9c535a708ae9 | 36 | // I/O Configuration // |
Matt Briggs | 31:9c535a708ae9 | 37 | /////////////////////// |
Matt Briggs | 29:e05e35976cfe | 38 | DigitalOut led1(GPIO0); |
Matt Briggs | 29:e05e35976cfe | 39 | AnalogIn an1(GPIO1); |
Matt Briggs | 29:e05e35976cfe | 40 | AnalogIn an2(GPIO2); |
Matt Briggs | 29:e05e35976cfe | 41 | |
Matt Briggs | 29:e05e35976cfe | 42 | // Inputs |
Matt Briggs | 37:31f8e9c5d075 | 43 | //DigitalIn gpio3(GPIO3); |
Matt Briggs | 31:9c535a708ae9 | 44 | //DigitalIn wake_DOUT(WAKE); |
Matt Briggs | 37:31f8e9c5d075 | 45 | //DigitalIn i2cOut1(I2C1_SCL); |
Matt Briggs | 37:31f8e9c5d075 | 46 | //DigitalIn i2cOut2(I2C1_SDA); |
Matt Briggs | 33:c7bb3fbc024a | 47 | //DigitalIn uartOut1(UART1_CTS); |
Matt Briggs | 33:c7bb3fbc024a | 48 | //DigitalIn uartOut2(UART1_RTS); |
Matt Briggs | 33:c7bb3fbc024a | 49 | //DigitalIn jtag_gpio1(SWDIO); |
Matt Briggs | 33:c7bb3fbc024a | 50 | //DigitalIn jtag_gpio2(SWCLK); |
Matt Briggs | 29:e05e35976cfe | 51 | |
Matt Briggs | 29:e05e35976cfe | 52 | // Outputs |
Matt Briggs | 29:e05e35976cfe | 53 | //DigitalOut gpio3(GPIO3); |
Matt Briggs | 29:e05e35976cfe | 54 | ////DigitalOut wake_DOUT(WAKE); |
Matt Briggs | 29:e05e35976cfe | 55 | //DigitalOut i2cOut1(I2C1_SCL); |
Matt Briggs | 29:e05e35976cfe | 56 | //DigitalOut i2cOut2(I2C1_SDA); |
Matt Briggs | 29:e05e35976cfe | 57 | // |
Matt Briggs | 29:e05e35976cfe | 58 | //DigitalOut uartOut1(UART1_CTS); |
Matt Briggs | 29:e05e35976cfe | 59 | //DigitalOut uartOut2(UART1_RTS); |
Matt Briggs | 29:e05e35976cfe | 60 | |
Mike Fiore |
11:d2e31743433a | 61 | mDot* dot = NULL; |
Mike Fiore |
11:d2e31743433a | 62 | |
Mike Fiore |
11:d2e31743433a | 63 | Serial pc(USBTX, USBRX); |
Mike Fiore |
11:d2e31743433a | 64 | |
Mike Fiore |
11:d2e31743433a | 65 | int main() { |
Matt Briggs | 31:9c535a708ae9 | 66 | unsigned int wakeMode; |
Matt Briggs | 31:9c535a708ae9 | 67 | RadioEvent events; // Custom event handler for automatically displaying RX data |
Mike Fiore |
11:d2e31743433a | 68 | uint32_t tx_frequency; |
Mike Fiore |
11:d2e31743433a | 69 | uint8_t tx_datarate; |
Mike Fiore |
11:d2e31743433a | 70 | uint8_t tx_power; |
Mike Fiore |
11:d2e31743433a | 71 | uint8_t frequency_band; |
Mike Fiore |
11:d2e31743433a | 72 | |
Mike Fiore |
11:d2e31743433a | 73 | pc.baud(115200); |
Mike Fiore |
11:d2e31743433a | 74 | |
Matt Briggs | 27:6b68ff715ae1 | 75 | mts::MTSLog::setLogLevel(mts::MTSLog::TRACE_LEVEL); |
Mike Fiore |
11:d2e31743433a | 76 | |
Mike Fiore |
11:d2e31743433a | 77 | dot = mDot::getInstance(); |
Mike Fiore |
11:d2e31743433a | 78 | |
Mike Fiore |
16:a3832552dfe1 | 79 | logInfo("mbed-os library version: %d", MBED_LIBRARY_VERSION); |
Mike Fiore |
16:a3832552dfe1 | 80 | |
Mike Fiore |
12:ec9768677cea | 81 | // start from a well-known state |
Mike Fiore |
12:ec9768677cea | 82 | logInfo("defaulting Dot configuration"); |
Mike Fiore |
12:ec9768677cea | 83 | dot->resetConfig(); |
Mike Fiore |
12:ec9768677cea | 84 | |
Mike Fiore |
11:d2e31743433a | 85 | // make sure library logging is turned on |
Matt Briggs | 27:6b68ff715ae1 | 86 | dot->setLogLevel(mts::MTSLog::INFO_LEVEL); |
Mike Fiore |
11:d2e31743433a | 87 | |
Mike Fiore |
11:d2e31743433a | 88 | // attach the custom events handler |
Mike Fiore |
11:d2e31743433a | 89 | dot->setEvents(&events); |
Mike Fiore |
11:d2e31743433a | 90 | |
Matt Briggs | 31:9c535a708ae9 | 91 | // Setup programmable voltage detector |
Matt Briggs | 31:9c535a708ae9 | 92 | // PVD_LEVEL0 Falling 1.85 |
Matt Briggs | 31:9c535a708ae9 | 93 | // PVD_LEVEL1 Falling 2.04 |
Matt Briggs | 31:9c535a708ae9 | 94 | // PVD_LEVEL2 Falling 2.24 |
Matt Briggs | 31:9c535a708ae9 | 95 | // PVD_LEVEL3 Falling 2.44 |
Matt Briggs | 31:9c535a708ae9 | 96 | // PVD_LEVEL4 Falling 2.64 |
Matt Briggs | 31:9c535a708ae9 | 97 | // PVD_LEVEL5 Falling 2.84 |
Matt Briggs | 31:9c535a708ae9 | 98 | // PVD_LEVEL6 Falling 3.05 |
Matt Briggs | 31:9c535a708ae9 | 99 | PWR_PVDTypeDef pvdConfig; |
Matt Briggs | 31:9c535a708ae9 | 100 | pvdConfig.Mode = PWR_PVD_MODE_NORMAL; |
Matt Briggs | 31:9c535a708ae9 | 101 | pvdConfig.PVDLevel = PWR_PVDLEVEL_5; |
Matt Briggs | 31:9c535a708ae9 | 102 | |
Matt Briggs | 31:9c535a708ae9 | 103 | HAL_PWR_ConfigPVD(&pvdConfig); |
Matt Briggs | 31:9c535a708ae9 | 104 | HAL_PWR_EnablePVD(); |
Matt Briggs | 31:9c535a708ae9 | 105 | logInfo("Programmable Voltage Detector set for level: %d", pvdConfig.PVDLevel); |
Matt Briggs | 31:9c535a708ae9 | 106 | |
Matt Briggs | 31:9c535a708ae9 | 107 | // TODO setup IO here |
Matt Briggs | 31:9c535a708ae9 | 108 | |
Mike Fiore |
11:d2e31743433a | 109 | // update configuration if necessary |
Matt Briggs | 31:9c535a708ae9 | 110 | logInfo("Setting up peer to peer configuration"); |
Mike Fiore |
11:d2e31743433a | 111 | if (dot->getJoinMode() != mDot::PEER_TO_PEER) { |
Mike Fiore |
11:d2e31743433a | 112 | logInfo("changing network join mode to PEER_TO_PEER"); |
Mike Fiore |
11:d2e31743433a | 113 | if (dot->setJoinMode(mDot::PEER_TO_PEER) != mDot::MDOT_OK) { |
Mike Fiore |
11:d2e31743433a | 114 | logError("failed to set network join mode to PEER_TO_PEER"); |
Mike Fiore |
11:d2e31743433a | 115 | } |
Mike Fiore |
11:d2e31743433a | 116 | } |
Mike Fiore |
11:d2e31743433a | 117 | frequency_band = dot->getFrequencyBand(); |
Mike Fiore |
11:d2e31743433a | 118 | switch (frequency_band) { |
Mike Fiore |
11:d2e31743433a | 119 | case mDot::FB_EU868: |
Mike Fiore |
11:d2e31743433a | 120 | // 250kHz channels achieve higher throughput |
Mike Fiore |
11:d2e31743433a | 121 | // DR6 : SF7 @ 250kHz |
Mike Fiore |
11:d2e31743433a | 122 | // DR0 - DR5 (125kHz channels) available but much slower |
Mike Fiore |
11:d2e31743433a | 123 | tx_frequency = 869850000; |
Mike Fiore |
11:d2e31743433a | 124 | tx_datarate = mDot::DR6; |
Mike Fiore |
11:d2e31743433a | 125 | // the 869850000 frequency is 100% duty cycle if the total power is under 7 dBm - tx power 4 + antenna gain 3 = 7 |
Mike Fiore |
11:d2e31743433a | 126 | tx_power = 4; |
Mike Fiore |
11:d2e31743433a | 127 | break; |
Mike Fiore |
11:d2e31743433a | 128 | case mDot::FB_US915: |
Mike Fiore |
11:d2e31743433a | 129 | case mDot::FB_AU915: |
Mike Fiore |
11:d2e31743433a | 130 | default: |
Mike Fiore |
11:d2e31743433a | 131 | // 500kHz channels achieve highest throughput |
Mike Fiore |
11:d2e31743433a | 132 | // DR8 : SF12 @ 500kHz |
Mike Fiore |
11:d2e31743433a | 133 | // DR9 : SF11 @ 500kHz |
Mike Fiore |
11:d2e31743433a | 134 | // DR10 : SF10 @ 500kHz |
Mike Fiore |
11:d2e31743433a | 135 | // DR11 : SF9 @ 500kHz |
Mike Fiore |
11:d2e31743433a | 136 | // DR12 : SF8 @ 500kHz |
Mike Fiore |
11:d2e31743433a | 137 | // DR13 : SF7 @ 500kHz |
Mike Fiore |
11:d2e31743433a | 138 | // DR0 - DR3 (125kHz channels) available but much slower |
Mike Fiore |
11:d2e31743433a | 139 | tx_frequency = 915500000; |
Mike Fiore |
11:d2e31743433a | 140 | tx_datarate = mDot::DR13; |
Mike Fiore |
11:d2e31743433a | 141 | // 915 bands have no duty cycle restrictions, set tx power to max |
Mike Fiore |
11:d2e31743433a | 142 | tx_power = 20; |
Mike Fiore |
11:d2e31743433a | 143 | break; |
Mike Fiore |
11:d2e31743433a | 144 | } |
Mike Fiore |
11:d2e31743433a | 145 | // in PEER_TO_PEER mode there is no join request/response transaction |
Mike Fiore |
11:d2e31743433a | 146 | // as long as both Dots are configured correctly, they should be able to communicate |
Mike Fiore |
11:d2e31743433a | 147 | update_peer_to_peer_config(network_address, network_session_key, data_session_key, tx_frequency, tx_datarate, tx_power); |
Mike Fiore |
11:d2e31743433a | 148 | |
Matt Briggs | 24:fdf87e4b72e5 | 149 | /////////////////////////////// |
Matt Briggs | 24:fdf87e4b72e5 | 150 | // Transmitter Configuration // |
Matt Briggs | 24:fdf87e4b72e5 | 151 | /////////////////////////////// |
Matt Briggs | 27:6b68ff715ae1 | 152 | #if BRIDGE_TX_BRUTE |
Matt Briggs | 24:fdf87e4b72e5 | 153 | wakeMode = mDot::INTERRUPT; |
Matt Briggs | 24:fdf87e4b72e5 | 154 | #endif |
Matt Briggs | 24:fdf87e4b72e5 | 155 | |
Matt Briggs | 24:fdf87e4b72e5 | 156 | //////////////////////////// |
Matt Briggs | 24:fdf87e4b72e5 | 157 | // Receiver Configuration // |
Matt Briggs | 24:fdf87e4b72e5 | 158 | //////////////////////////// |
Matt Briggs | 27:6b68ff715ae1 | 159 | #if BRIDGE_RX_BRUTE |
Matt Briggs | 24:fdf87e4b72e5 | 160 | wakeMode = mDot::RTC_ALARM_OR_INTERRUPT; |
Matt Briggs | 24:fdf87e4b72e5 | 161 | #endif |
Matt Briggs | 24:fdf87e4b72e5 | 162 | |
Matt Briggs | 24:fdf87e4b72e5 | 163 | // Common Configuration |
Matt Briggs | 33:c7bb3fbc024a | 164 | dot->setTxWait(false); |
Matt Briggs | 33:c7bb3fbc024a | 165 | dot->setAck(0); // Disable Ack |
Matt Briggs | 25:fea776239709 | 166 | dot->setWakePin(WAKE); // Use the wake pin as sleep interrupt |
Matt Briggs | 25:fea776239709 | 167 | dot->setClass("C"); // Set class C |
Matt Briggs | 31:9c535a708ae9 | 168 | dot->setTxPower(TX_PWR); |
Matt Briggs | 24:fdf87e4b72e5 | 169 | |
Mike Fiore |
11:d2e31743433a | 170 | // save changes to configuration |
Mike Fiore |
11:d2e31743433a | 171 | logInfo("saving configuration"); |
Mike Fiore |
11:d2e31743433a | 172 | if (!dot->saveConfig()) { |
Mike Fiore |
11:d2e31743433a | 173 | logError("failed to save configuration"); |
Mike Fiore |
11:d2e31743433a | 174 | } |
Mike Fiore |
11:d2e31743433a | 175 | |
Mike Fiore |
11:d2e31743433a | 176 | // display configuration |
Mike Fiore |
11:d2e31743433a | 177 | display_config(); |
Mike Fiore |
11:d2e31743433a | 178 | |
Matt Briggs | 26:9411b26a5084 | 179 | |
Matt Briggs | 31:9c535a708ae9 | 180 | unsigned int nTimesToTx = ceil(RX_SLEEP_TIME / ((float)TX_TIME)); |
Matt Briggs | 31:9c535a708ae9 | 181 | logInfo("RX_SLEEP_TIME %f, timeOnAir %lu, nTimesToTx %lu", RX_SLEEP_TIME, TX_TIME, nTimesToTx); |
Matt Briggs | 26:9411b26a5084 | 182 | |
mbriggs_vortex | 23:4ed894108882 | 183 | uint16_t seqNum=0; |
Matt Briggs | 26:9411b26a5084 | 184 | uint32_t cDwnLink = dot->getDownLinkCounter(); |
Matt Briggs | 30:2e673a672884 | 185 | |
Mike Fiore |
11:d2e31743433a | 186 | while (true) { |
Matt Briggs | 25:fea776239709 | 187 | std::vector<uint8_t> data; |
Matt Briggs | 31:9c535a708ae9 | 188 | led1=0; |
Mike Fiore |
11:d2e31743433a | 189 | |
Mike Fiore |
11:d2e31743433a | 190 | // join network if not joined |
Mike Fiore |
11:d2e31743433a | 191 | if (!dot->getNetworkJoinStatus()) { |
Mike Fiore |
11:d2e31743433a | 192 | join_network(); |
Mike Fiore |
11:d2e31743433a | 193 | } |
Mike Fiore |
11:d2e31743433a | 194 | |
Matt Briggs | 31:9c535a708ae9 | 195 | ////////////////////// |
Matt Briggs | 31:9c535a708ae9 | 196 | // Common main loop // |
Matt Briggs | 31:9c535a708ae9 | 197 | ////////////////////// |
Matt Briggs | 31:9c535a708ae9 | 198 | |
Matt Briggs | 31:9c535a708ae9 | 199 | // TODO sample rotary |
Matt Briggs | 31:9c535a708ae9 | 200 | // TODO sample DIPs |
Matt Briggs | 31:9c535a708ae9 | 201 | |
Matt Briggs | 27:6b68ff715ae1 | 202 | ////////////////////////////////////////// |
Matt Briggs | 27:6b68ff715ae1 | 203 | // Brute Protocol Transmitter main loop // |
Matt Briggs | 27:6b68ff715ae1 | 204 | ////////////////////////////////////////// |
Matt Briggs | 27:6b68ff715ae1 | 205 | #if BRIDGE_TX_BRUTE |
Matt Briggs | 31:9c535a708ae9 | 206 | #if LED_FEEDBACK |
Matt Briggs | 26:9411b26a5084 | 207 | led1=1; |
Matt Briggs | 31:9c535a708ae9 | 208 | #endif |
Matt Briggs | 31:9c535a708ae9 | 209 | // TODO check for CC_IN |
Matt Briggs | 31:9c535a708ae9 | 210 | |
Matt Briggs | 25:fea776239709 | 211 | data.push_back((seqNum >> 8) & 0xFF); |
Matt Briggs | 25:fea776239709 | 212 | data.push_back(seqNum & 0xFF); |
Matt Briggs | 27:6b68ff715ae1 | 213 | logInfo("Starting TX. Time: %lu, seqNum: %lu", us_ticker_read(), seqNum); |
Matt Briggs | 26:9411b26a5084 | 214 | for(uint i=0;i<nTimesToTx;++i) { |
Matt Briggs | 27:6b68ff715ae1 | 215 | dot->send(data); |
Matt Briggs | 26:9411b26a5084 | 216 | } |
mbriggs_vortex | 23:4ed894108882 | 217 | seqNum++; |
Matt Briggs | 25:fea776239709 | 218 | led1=0; |
Matt Briggs | 27:6b68ff715ae1 | 219 | logInfo("Finished TX. Time: %lu", us_ticker_read()); |
mbriggs_vortex | 23:4ed894108882 | 220 | |
Matt Briggs | 28:b14b2926e916 | 221 | sleep_save_io(); |
Matt Briggs | 28:b14b2926e916 | 222 | sleep_configure_io(); |
Matt Briggs | 24:fdf87e4b72e5 | 223 | dot->sleep(0, wakeMode, false); // Go to sleep until wake button |
Matt Briggs | 28:b14b2926e916 | 224 | sleep_restore_io(); |
Matt Briggs | 24:fdf87e4b72e5 | 225 | #endif |
Matt Briggs | 27:6b68ff715ae1 | 226 | |
Matt Briggs | 27:6b68ff715ae1 | 227 | /////////////////////////////////////// |
Matt Briggs | 27:6b68ff715ae1 | 228 | // Brute Protocol Receiver main loop // |
Matt Briggs | 27:6b68ff715ae1 | 229 | /////////////////////////////////////// |
Matt Briggs | 27:6b68ff715ae1 | 230 | #if BRIDGE_RX_BRUTE |
Matt Briggs | 27:6b68ff715ae1 | 231 | logInfo("Waiting for new message current DLC: %d, Time %d", cDwnLink, us_ticker_read()); |
Matt Briggs | 31:9c535a708ae9 | 232 | wait(TX_TIME/1000.0); // Wait TX_TIME |
Matt Briggs | 31:9c535a708ae9 | 233 | |
Matt Briggs | 31:9c535a708ae9 | 234 | // TODO need to figure out what to do when DLC get resets |
Matt Briggs | 31:9c535a708ae9 | 235 | |
Matt Briggs | 26:9411b26a5084 | 236 | if (cDwnLink < dot->getDownLinkCounter()) { |
Matt Briggs | 26:9411b26a5084 | 237 | cDwnLink = dot->getDownLinkCounter(); |
Matt Briggs | 26:9411b26a5084 | 238 | dot->recv(data); |
Matt Briggs | 26:9411b26a5084 | 239 | std::string dataStr(data.begin(), data.end()); |
Matt Briggs | 26:9411b26a5084 | 240 | logInfo("Got msg num: %d, payload: %s", seqNum, dataStr.c_str()); |
Matt Briggs | 31:9c535a708ae9 | 241 | // TODO add CC_OUT code here |
Matt Briggs | 26:9411b26a5084 | 242 | seqNum++; |
Matt Briggs | 31:9c535a708ae9 | 243 | #if LED_FEEDBACK |
Matt Briggs | 31:9c535a708ae9 | 244 | led1 = 1; |
Matt Briggs | 26:9411b26a5084 | 245 | wait(0.5); |
Matt Briggs | 31:9c535a708ae9 | 246 | #endif |
Matt Briggs | 25:fea776239709 | 247 | } |
Matt Briggs | 26:9411b26a5084 | 248 | led1=0; |
Matt Briggs | 27:6b68ff715ae1 | 249 | logInfo("Sleeping. Time %d", us_ticker_read()); |
Matt Briggs | 28:b14b2926e916 | 250 | sleep_save_io(); |
Matt Briggs | 28:b14b2926e916 | 251 | sleep_configure_io(); |
Matt Briggs | 31:9c535a708ae9 | 252 | // TODO maybe add if statement here to prevent double hits by sleeping for a longer time |
Matt Briggs | 26:9411b26a5084 | 253 | dot->sleep(2, wakeMode, false); // Go to sleep until wake button |
Matt Briggs | 28:b14b2926e916 | 254 | sleep_restore_io(); |
Matt Briggs | 25:fea776239709 | 255 | #endif |
Matt Briggs | 31:9c535a708ae9 | 256 | |
Matt Briggs | 29:e05e35976cfe | 257 | ////////////// |
Matt Briggs | 29:e05e35976cfe | 258 | // I/O Play // |
Matt Briggs | 29:e05e35976cfe | 259 | ////////////// |
Matt Briggs | 29:e05e35976cfe | 260 | |
Matt Briggs | 31:9c535a708ae9 | 261 | // // Check Analog |
Matt Briggs | 31:9c535a708ae9 | 262 | // logInfo("Read AN1/GPIO1: %f", an1.read()); |
Matt Briggs | 31:9c535a708ae9 | 263 | // logInfo("Read AN2/GPIO2: %f", an2.read()); // Ranges from 0.0 to 1.0 |
Matt Briggs | 31:9c535a708ae9 | 264 | // |
Matt Briggs | 31:9c535a708ae9 | 265 | // // check inputs |
Matt Briggs | 31:9c535a708ae9 | 266 | // logInfo("Read GPIO3: %d", gpio3.read()); |
Matt Briggs | 31:9c535a708ae9 | 267 | //// logInfo("Read wake_DOUT: %d", wake_DOUT.read()); |
Matt Briggs | 31:9c535a708ae9 | 268 | // logInfo("Read i2cOut1: %d", i2cOut1.read()); // Appears to be pulled up |
Matt Briggs | 31:9c535a708ae9 | 269 | // logInfo("Read i2cOut2: %d", i2cOut2.read()); // Appears to be pulled up |
Matt Briggs | 31:9c535a708ae9 | 270 | // logInfo("Read uartOut1: %d", uartOut1.read()); |
Matt Briggs | 31:9c535a708ae9 | 271 | // logInfo("Read uartOut2: %d", uartOut2.read()); |
Matt Briggs | 31:9c535a708ae9 | 272 | // |
Matt Briggs | 31:9c535a708ae9 | 273 | // logInfo("Read jtag_gpio1: %d", jtag_gpio1.read()); |
Matt Briggs | 31:9c535a708ae9 | 274 | // logInfo("Read jtag_gpio2: %d", jtag_gpio2.read()); |
Matt Briggs | 31:9c535a708ae9 | 275 | // |
Matt Briggs | 31:9c535a708ae9 | 276 | // if (jtag_gpio1.read() == 0) { |
Matt Briggs | 31:9c535a708ae9 | 277 | // led1 = 1; |
Matt Briggs | 31:9c535a708ae9 | 278 | // } |
Matt Briggs | 31:9c535a708ae9 | 279 | // else { |
Matt Briggs | 31:9c535a708ae9 | 280 | // led1 = 0; |
Matt Briggs | 31:9c535a708ae9 | 281 | // } |
Matt Briggs | 29:e05e35976cfe | 282 | |
Matt Briggs | 29:e05e35976cfe | 283 | // check digital outputs |
Matt Briggs | 29:e05e35976cfe | 284 | // led1 = !led1; |
Matt Briggs | 29:e05e35976cfe | 285 | // gpio3 = !gpio3; |
Matt Briggs | 29:e05e35976cfe | 286 | //// wake_DOUT = !wake_DOUT; |
Matt Briggs | 29:e05e35976cfe | 287 | // i2cOut1 = !i2cOut1; |
Matt Briggs | 29:e05e35976cfe | 288 | // i2cOut2 = !i2cOut2; |
Matt Briggs | 29:e05e35976cfe | 289 | // |
Matt Briggs | 29:e05e35976cfe | 290 | // uartOut1 = !uartOut1; |
Matt Briggs | 29:e05e35976cfe | 291 | // uartOut2 = !uartOut2; |
Matt Briggs | 29:e05e35976cfe | 292 | |
Matt Briggs | 31:9c535a708ae9 | 293 | // logInfo("================================"); |
Matt Briggs | 31:9c535a708ae9 | 294 | // wait(1.0); |
Matt Briggs | 34:5618603e5fc3 | 295 | ////////////////// |
Matt Briggs | 34:5618603e5fc3 | 296 | // OneWire Play // |
Matt Briggs | 34:5618603e5fc3 | 297 | ////////////////// |
Matt Briggs | 34:5618603e5fc3 | 298 | |
Matt Briggs | 37:31f8e9c5d075 | 299 | logInfo("Starting OneWire Play"); |
Matt Briggs | 36:0fb61acf7fae | 300 | OneWire owMaster(I2C_SDA); |
Matt Briggs | 36:0fb61acf7fae | 301 | uint8_t addr[8]; |
Matt Briggs | 36:0fb61acf7fae | 302 | uint8_t result; |
Matt Briggs | 36:0fb61acf7fae | 303 | |
Matt Briggs | 36:0fb61acf7fae | 304 | // Search Bus |
Matt Briggs | 37:31f8e9c5d075 | 305 | logInfo("Starting OneWire Search"); |
Matt Briggs | 36:0fb61acf7fae | 306 | do { |
Matt Briggs | 36:0fb61acf7fae | 307 | result = owMaster.search(addr); |
Matt Briggs | 36:0fb61acf7fae | 308 | logInfo("ROM Addr: %02x:%02x:%02x:%02x:%02x:%02x:%02x%02x\n", |
Matt Briggs | 37:31f8e9c5d075 | 309 | addr[7],addr[6],addr[5],addr[4],addr[3],addr[2],addr[1],addr[0]); |
Matt Briggs | 36:0fb61acf7fae | 310 | } while (result == 1); |
Matt Briggs | 37:31f8e9c5d075 | 311 | logInfo("Finished OneWire Search"); |
Matt Briggs | 37:31f8e9c5d075 | 312 | wait(1.0); |
Matt Briggs | 36:0fb61acf7fae | 313 | |
Matt Briggs | 37:31f8e9c5d075 | 314 | uint8_t pioStateAddr[] = {0x88, 0x00}; |
Matt Briggs | 37:31f8e9c5d075 | 315 | uint8_t pioLatchAddr[] = {0x89, 0x00}; |
Matt Briggs | 37:31f8e9c5d075 | 316 | uint8_t printAddr = 0x88; |
Matt Briggs | 36:0fb61acf7fae | 317 | while (true) { |
Matt Briggs | 36:0fb61acf7fae | 318 | owMaster.reset(); |
Matt Briggs | 36:0fb61acf7fae | 319 | owMaster.select(addr); |
Matt Briggs | 36:0fb61acf7fae | 320 | owMaster.write(0xF0); // Read Register Command |
Matt Briggs | 36:0fb61acf7fae | 321 | owMaster.write_bytes(pioStateAddr, 2); // Write 2 byte addr |
Matt Briggs | 37:31f8e9c5d075 | 322 | printAddr = 0x88; |
Matt Briggs | 37:31f8e9c5d075 | 323 | for (int i=0;i<8;i++) { |
Matt Briggs | 37:31f8e9c5d075 | 324 | result = owMaster.read(); |
Matt Briggs | 37:31f8e9c5d075 | 325 | logInfo("%02x Reg Value: %02x\n", printAddr++, result); |
Matt Briggs | 37:31f8e9c5d075 | 326 | } |
Matt Briggs | 37:31f8e9c5d075 | 327 | |
Matt Briggs | 37:31f8e9c5d075 | 328 | owMaster.reset(); |
Matt Briggs | 37:31f8e9c5d075 | 329 | owMaster.select(addr); |
Matt Briggs | 37:31f8e9c5d075 | 330 | owMaster.write(0xF0); // Read Register Command |
Matt Briggs | 37:31f8e9c5d075 | 331 | owMaster.write_bytes(pioLatchAddr, 2); // Write 2 byte addr |
Matt Briggs | 36:0fb61acf7fae | 332 | result = owMaster.read(); |
Matt Briggs | 37:31f8e9c5d075 | 333 | logInfo("Latch Reg Value: %02x\n", result); |
Matt Briggs | 36:0fb61acf7fae | 334 | // TODO try reading inverted 16-bit CRC |
Matt Briggs | 36:0fb61acf7fae | 335 | |
Matt Briggs | 37:31f8e9c5d075 | 336 | wait(1.0); |
Matt Briggs | 37:31f8e9c5d075 | 337 | // Try write |
Matt Briggs | 37:31f8e9c5d075 | 338 | owMaster.reset(); |
Matt Briggs | 37:31f8e9c5d075 | 339 | owMaster.select(addr); |
Matt Briggs | 37:31f8e9c5d075 | 340 | owMaster.write(0x5A); // Channel Access Write Command |
Matt Briggs | 37:31f8e9c5d075 | 341 | uint8_t val = ~0xAA; |
Matt Briggs | 37:31f8e9c5d075 | 342 | owMaster.write(val); // Pull-down all even bits |
Matt Briggs | 37:31f8e9c5d075 | 343 | owMaster.write(~val); // Pull-down all even bits |
Matt Briggs | 37:31f8e9c5d075 | 344 | result = owMaster.read(); |
Matt Briggs | 37:31f8e9c5d075 | 345 | logInfo("Confirm after write value: %02x, expected %02x\n", result, 0xAA); |
Matt Briggs | 36:0fb61acf7fae | 346 | |
Matt Briggs | 36:0fb61acf7fae | 347 | // Check if the read back is just a latch reg thing or a true logic state |
Matt Briggs | 37:31f8e9c5d075 | 348 | wait(1.0); |
Matt Briggs | 36:0fb61acf7fae | 349 | |
Matt Briggs | 36:0fb61acf7fae | 350 | } |
Matt Briggs | 36:0fb61acf7fae | 351 | |
Matt Briggs | 34:5618603e5fc3 | 352 | |
Matt Briggs | 34:5618603e5fc3 | 353 | |
Mike Fiore |
11:d2e31743433a | 354 | } |
Mike Fiore |
11:d2e31743433a | 355 | |
Mike Fiore |
11:d2e31743433a | 356 | return 0; |
Mike Fiore |
11:d2e31743433a | 357 | } |
Mike Fiore |
11:d2e31743433a | 358 | |
Matt Briggs | 27:6b68ff715ae1 | 359 |