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Fork to see if I can get working
Dependencies: BufferedSerial OneWire WinbondSPIFlash libxDot-dev-mbed5-deprecated
Fork of xDotBridge_update_test20180823 by
xDotBridge/src/DS2408.cpp@57:bdac7dd17af2, 2017-02-28 (annotated)
- Committer:
- Matt Briggs
- Date:
- Tue Feb 28 09:26:27 2017 -0700
- Revision:
- 57:bdac7dd17af2
- Parent:
- 56:40b454c952cc
- Child:
- 67:2115a2f1b945
Got static networking with static configuration working. Also added disabling test mode for DS2408.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
Matt Briggs | 40:2ec4be320961 | 1 | #include "DS2408.h" |
Matt Briggs | 40:2ec4be320961 | 2 | |
Matt Briggs | 40:2ec4be320961 | 3 | enum DS2408Cmd { |
Matt Briggs | 40:2ec4be320961 | 4 | registerReadCmd = 0xF0, |
Matt Briggs | 40:2ec4be320961 | 5 | channelAccessReadCmd = 0xF5, |
Matt Briggs | 40:2ec4be320961 | 6 | channelAccessWriteCmd = 0x5A |
Matt Briggs | 40:2ec4be320961 | 7 | }; |
Matt Briggs | 40:2ec4be320961 | 8 | |
Matt Briggs | 40:2ec4be320961 | 9 | DS2408::DS2408(OneWire *owMaster, uint8_t romAddr[8]) |
Matt Briggs | 40:2ec4be320961 | 10 | { |
Matt Briggs | 40:2ec4be320961 | 11 | mMaster = owMaster; |
Matt Briggs | 40:2ec4be320961 | 12 | std::memcpy(mRomAddr, romAddr, sizeof(mRomAddr)); |
Matt Briggs | 40:2ec4be320961 | 13 | } |
Matt Briggs | 40:2ec4be320961 | 14 | |
Matt Briggs | 40:2ec4be320961 | 15 | CmdResult DS2408::init() |
Matt Briggs | 40:2ec4be320961 | 16 | { |
Matt Briggs | 57:bdac7dd17af2 | 17 | return disableTestMode(); |
Matt Briggs | 40:2ec4be320961 | 18 | } |
Matt Briggs | 40:2ec4be320961 | 19 | |
Matt Briggs | 56:40b454c952cc | 20 | CmdResult DS2408::registerReadReliable(uint8_t addr, uint8_t &val) |
Matt Briggs | 56:40b454c952cc | 21 | { |
Matt Briggs | 56:40b454c952cc | 22 | uint8_t result = 0; |
Matt Briggs | 56:40b454c952cc | 23 | uint8_t result1 = 0xFF; |
Matt Briggs | 56:40b454c952cc | 24 | uint8_t cmdResult; |
Matt Briggs | 56:40b454c952cc | 25 | cmdResult = registerRead(addr, result); |
Matt Briggs | 56:40b454c952cc | 26 | for (int i=0; i < DS2408_NRETRIES; i++) { |
Matt Briggs | 56:40b454c952cc | 27 | cmdResult = registerRead(addr, result1); |
Matt Briggs | 56:40b454c952cc | 28 | if (cmdResult != cmdSuccess) { |
Matt Briggs | 56:40b454c952cc | 29 | continue; |
Matt Briggs | 56:40b454c952cc | 30 | } |
Matt Briggs | 56:40b454c952cc | 31 | // Check they match |
Matt Briggs | 56:40b454c952cc | 32 | if (result == result1) { |
Matt Briggs | 56:40b454c952cc | 33 | val = result; |
Matt Briggs | 56:40b454c952cc | 34 | return cmdSuccess; |
Matt Briggs | 56:40b454c952cc | 35 | } |
Matt Briggs | 56:40b454c952cc | 36 | else { |
Matt Briggs | 56:40b454c952cc | 37 | result = result1; |
Matt Briggs | 56:40b454c952cc | 38 | } |
Matt Briggs | 56:40b454c952cc | 39 | } |
Matt Briggs | 56:40b454c952cc | 40 | return cmdTimeout; |
Matt Briggs | 56:40b454c952cc | 41 | } |
Matt Briggs | 56:40b454c952cc | 42 | |
Matt Briggs | 40:2ec4be320961 | 43 | CmdResult DS2408::registerRead(uint8_t addr, uint8_t &val) |
Matt Briggs | 40:2ec4be320961 | 44 | { |
Matt Briggs | 40:2ec4be320961 | 45 | uint8_t addrArray[] = {0x00, 0x00}; |
Matt Briggs | 40:2ec4be320961 | 46 | addrArray[0] = addr; |
Matt Briggs | 40:2ec4be320961 | 47 | mMaster->reset(); |
Matt Briggs | 40:2ec4be320961 | 48 | mMaster->select(mRomAddr); |
Matt Briggs | 40:2ec4be320961 | 49 | mMaster->write(registerReadCmd); // Read Register Command |
Matt Briggs | 40:2ec4be320961 | 50 | mMaster->write_bytes(addrArray, 2); // Write 2 byte addr |
Matt Briggs | 40:2ec4be320961 | 51 | val = mMaster->read(); |
Matt Briggs | 40:2ec4be320961 | 52 | // logDebug("Reg Value: %02x\n", result); |
Matt Briggs | 40:2ec4be320961 | 53 | return cmdSuccess; |
Matt Briggs | 40:2ec4be320961 | 54 | } |
Matt Briggs | 40:2ec4be320961 | 55 | |
Matt Briggs | 40:2ec4be320961 | 56 | CmdResult DS2408::pioLogicRead(uint8_t &val) |
Matt Briggs | 40:2ec4be320961 | 57 | { |
Matt Briggs | 40:2ec4be320961 | 58 | return registerRead(pioLogicStateReg, val); |
Matt Briggs | 40:2ec4be320961 | 59 | } |
Matt Briggs | 40:2ec4be320961 | 60 | |
Matt Briggs | 50:e89647e77fd5 | 61 | CmdResult DS2408::pioLogicReliableRead(uint8_t &val) |
Matt Briggs | 50:e89647e77fd5 | 62 | { |
Matt Briggs | 56:40b454c952cc | 63 | return registerReadReliable(pioLogicStateReg, val); |
Matt Briggs | 50:e89647e77fd5 | 64 | } |
Matt Briggs | 50:e89647e77fd5 | 65 | |
Matt Briggs | 40:2ec4be320961 | 66 | CmdResult DS2408::pioLogicWrite(uint8_t val) |
Matt Briggs | 40:2ec4be320961 | 67 | { |
Matt Briggs | 40:2ec4be320961 | 68 | mMaster->reset(); |
Matt Briggs | 40:2ec4be320961 | 69 | mMaster->select(mRomAddr); |
Matt Briggs | 40:2ec4be320961 | 70 | mMaster->write(channelAccessWriteCmd); |
Matt Briggs | 40:2ec4be320961 | 71 | mMaster->write(val); |
Matt Briggs | 40:2ec4be320961 | 72 | mMaster->write(~val); // Need to write complement to ensure no bit errors |
Matt Briggs | 40:2ec4be320961 | 73 | uint8_t result = mMaster->read(); |
Matt Briggs | 40:2ec4be320961 | 74 | if (result == 0xAA) { |
Matt Briggs | 40:2ec4be320961 | 75 | return cmdSuccess; |
Matt Briggs | 40:2ec4be320961 | 76 | } |
Matt Briggs | 40:2ec4be320961 | 77 | else { |
Matt Briggs | 40:2ec4be320961 | 78 | return cmdError; |
Matt Briggs | 40:2ec4be320961 | 79 | } |
Matt Briggs | 40:2ec4be320961 | 80 | } |
Matt Briggs | 50:e89647e77fd5 | 81 | |
Matt Briggs | 57:bdac7dd17af2 | 82 | CmdResult DS2408::pioLogicReliableWrite(uint8_t val) |
Matt Briggs | 57:bdac7dd17af2 | 83 | { |
Matt Briggs | 50:e89647e77fd5 | 84 | uint8_t result; |
Matt Briggs | 50:e89647e77fd5 | 85 | for (int i=0; i < DS2408_NRETRIES; i++) { |
Matt Briggs | 50:e89647e77fd5 | 86 | result = pioLogicWrite(val); |
Matt Briggs | 50:e89647e77fd5 | 87 | if (result == cmdSuccess) { |
Matt Briggs | 50:e89647e77fd5 | 88 | return cmdSuccess; |
Matt Briggs | 50:e89647e77fd5 | 89 | } |
Matt Briggs | 50:e89647e77fd5 | 90 | } |
Matt Briggs | 50:e89647e77fd5 | 91 | return cmdTimeout; |
Matt Briggs | 50:e89647e77fd5 | 92 | } |
Matt Briggs | 57:bdac7dd17af2 | 93 | |
Matt Briggs | 57:bdac7dd17af2 | 94 | CmdResult DS2408::disableTestMode() |
Matt Briggs | 57:bdac7dd17af2 | 95 | { |
Matt Briggs | 57:bdac7dd17af2 | 96 | mMaster->reset(); |
Matt Briggs | 57:bdac7dd17af2 | 97 | mMaster->write(0x96); |
Matt Briggs | 57:bdac7dd17af2 | 98 | |
Matt Briggs | 57:bdac7dd17af2 | 99 | for (uint8_t i = 0; i < 8; i++) mMaster->write(mRomAddr[i]); |
Matt Briggs | 57:bdac7dd17af2 | 100 | |
Matt Briggs | 57:bdac7dd17af2 | 101 | mMaster->write(0x3C); |
Matt Briggs | 57:bdac7dd17af2 | 102 | mMaster->reset(); |
Matt Briggs | 57:bdac7dd17af2 | 103 | return cmdSuccess; |
Matt Briggs | 57:bdac7dd17af2 | 104 | } |