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Fork to see if I can get working
Dependencies: BufferedSerial OneWire WinbondSPIFlash libxDot-dev-mbed5-deprecated
Fork of xDotBridge_update_test20180823 by
xDotBridge/src/DS2408.cpp@67:2115a2f1b945, 2017-03-21 (annotated)
- Committer:
- Matt Briggs
- Date:
- Tue Mar 21 13:04:31 2017 -0600
- Revision:
- 67:2115a2f1b945
- Parent:
- 57:bdac7dd17af2
For real added disabling test mode to DS2408. Plus other incremental changes to code.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
Matt Briggs | 40:2ec4be320961 | 1 | #include "DS2408.h" |
Matt Briggs | 40:2ec4be320961 | 2 | |
Matt Briggs | 40:2ec4be320961 | 3 | enum DS2408Cmd { |
Matt Briggs | 40:2ec4be320961 | 4 | registerReadCmd = 0xF0, |
Matt Briggs | 40:2ec4be320961 | 5 | channelAccessReadCmd = 0xF5, |
Matt Briggs | 40:2ec4be320961 | 6 | channelAccessWriteCmd = 0x5A |
Matt Briggs | 40:2ec4be320961 | 7 | }; |
Matt Briggs | 40:2ec4be320961 | 8 | |
Matt Briggs | 40:2ec4be320961 | 9 | DS2408::DS2408(OneWire *owMaster, uint8_t romAddr[8]) |
Matt Briggs | 40:2ec4be320961 | 10 | { |
Matt Briggs | 40:2ec4be320961 | 11 | mMaster = owMaster; |
Matt Briggs | 40:2ec4be320961 | 12 | std::memcpy(mRomAddr, romAddr, sizeof(mRomAddr)); |
Matt Briggs | 67:2115a2f1b945 | 13 | disableTestMode(); |
Matt Briggs | 40:2ec4be320961 | 14 | } |
Matt Briggs | 40:2ec4be320961 | 15 | |
Matt Briggs | 56:40b454c952cc | 16 | CmdResult DS2408::registerReadReliable(uint8_t addr, uint8_t &val) |
Matt Briggs | 56:40b454c952cc | 17 | { |
Matt Briggs | 56:40b454c952cc | 18 | uint8_t result = 0; |
Matt Briggs | 56:40b454c952cc | 19 | uint8_t result1 = 0xFF; |
Matt Briggs | 56:40b454c952cc | 20 | uint8_t cmdResult; |
Matt Briggs | 56:40b454c952cc | 21 | cmdResult = registerRead(addr, result); |
Matt Briggs | 56:40b454c952cc | 22 | for (int i=0; i < DS2408_NRETRIES; i++) { |
Matt Briggs | 56:40b454c952cc | 23 | cmdResult = registerRead(addr, result1); |
Matt Briggs | 56:40b454c952cc | 24 | if (cmdResult != cmdSuccess) { |
Matt Briggs | 56:40b454c952cc | 25 | continue; |
Matt Briggs | 56:40b454c952cc | 26 | } |
Matt Briggs | 56:40b454c952cc | 27 | // Check they match |
Matt Briggs | 56:40b454c952cc | 28 | if (result == result1) { |
Matt Briggs | 56:40b454c952cc | 29 | val = result; |
Matt Briggs | 56:40b454c952cc | 30 | return cmdSuccess; |
Matt Briggs | 56:40b454c952cc | 31 | } |
Matt Briggs | 56:40b454c952cc | 32 | else { |
Matt Briggs | 56:40b454c952cc | 33 | result = result1; |
Matt Briggs | 56:40b454c952cc | 34 | } |
Matt Briggs | 56:40b454c952cc | 35 | } |
Matt Briggs | 56:40b454c952cc | 36 | return cmdTimeout; |
Matt Briggs | 56:40b454c952cc | 37 | } |
Matt Briggs | 56:40b454c952cc | 38 | |
Matt Briggs | 40:2ec4be320961 | 39 | CmdResult DS2408::registerRead(uint8_t addr, uint8_t &val) |
Matt Briggs | 40:2ec4be320961 | 40 | { |
Matt Briggs | 40:2ec4be320961 | 41 | uint8_t addrArray[] = {0x00, 0x00}; |
Matt Briggs | 40:2ec4be320961 | 42 | addrArray[0] = addr; |
Matt Briggs | 40:2ec4be320961 | 43 | mMaster->reset(); |
Matt Briggs | 40:2ec4be320961 | 44 | mMaster->select(mRomAddr); |
Matt Briggs | 40:2ec4be320961 | 45 | mMaster->write(registerReadCmd); // Read Register Command |
Matt Briggs | 40:2ec4be320961 | 46 | mMaster->write_bytes(addrArray, 2); // Write 2 byte addr |
Matt Briggs | 40:2ec4be320961 | 47 | val = mMaster->read(); |
Matt Briggs | 40:2ec4be320961 | 48 | // logDebug("Reg Value: %02x\n", result); |
Matt Briggs | 40:2ec4be320961 | 49 | return cmdSuccess; |
Matt Briggs | 40:2ec4be320961 | 50 | } |
Matt Briggs | 40:2ec4be320961 | 51 | |
Matt Briggs | 40:2ec4be320961 | 52 | CmdResult DS2408::pioLogicRead(uint8_t &val) |
Matt Briggs | 40:2ec4be320961 | 53 | { |
Matt Briggs | 40:2ec4be320961 | 54 | return registerRead(pioLogicStateReg, val); |
Matt Briggs | 40:2ec4be320961 | 55 | } |
Matt Briggs | 40:2ec4be320961 | 56 | |
Matt Briggs | 50:e89647e77fd5 | 57 | CmdResult DS2408::pioLogicReliableRead(uint8_t &val) |
Matt Briggs | 50:e89647e77fd5 | 58 | { |
Matt Briggs | 56:40b454c952cc | 59 | return registerReadReliable(pioLogicStateReg, val); |
Matt Briggs | 50:e89647e77fd5 | 60 | } |
Matt Briggs | 50:e89647e77fd5 | 61 | |
Matt Briggs | 40:2ec4be320961 | 62 | CmdResult DS2408::pioLogicWrite(uint8_t val) |
Matt Briggs | 40:2ec4be320961 | 63 | { |
Matt Briggs | 40:2ec4be320961 | 64 | mMaster->reset(); |
Matt Briggs | 40:2ec4be320961 | 65 | mMaster->select(mRomAddr); |
Matt Briggs | 40:2ec4be320961 | 66 | mMaster->write(channelAccessWriteCmd); |
Matt Briggs | 40:2ec4be320961 | 67 | mMaster->write(val); |
Matt Briggs | 40:2ec4be320961 | 68 | mMaster->write(~val); // Need to write complement to ensure no bit errors |
Matt Briggs | 40:2ec4be320961 | 69 | uint8_t result = mMaster->read(); |
Matt Briggs | 40:2ec4be320961 | 70 | if (result == 0xAA) { |
Matt Briggs | 40:2ec4be320961 | 71 | return cmdSuccess; |
Matt Briggs | 40:2ec4be320961 | 72 | } |
Matt Briggs | 40:2ec4be320961 | 73 | else { |
Matt Briggs | 40:2ec4be320961 | 74 | return cmdError; |
Matt Briggs | 40:2ec4be320961 | 75 | } |
Matt Briggs | 40:2ec4be320961 | 76 | } |
Matt Briggs | 50:e89647e77fd5 | 77 | |
Matt Briggs | 57:bdac7dd17af2 | 78 | CmdResult DS2408::pioLogicReliableWrite(uint8_t val) |
Matt Briggs | 57:bdac7dd17af2 | 79 | { |
Matt Briggs | 50:e89647e77fd5 | 80 | uint8_t result; |
Matt Briggs | 50:e89647e77fd5 | 81 | for (int i=0; i < DS2408_NRETRIES; i++) { |
Matt Briggs | 50:e89647e77fd5 | 82 | result = pioLogicWrite(val); |
Matt Briggs | 50:e89647e77fd5 | 83 | if (result == cmdSuccess) { |
Matt Briggs | 50:e89647e77fd5 | 84 | return cmdSuccess; |
Matt Briggs | 50:e89647e77fd5 | 85 | } |
Matt Briggs | 50:e89647e77fd5 | 86 | } |
Matt Briggs | 50:e89647e77fd5 | 87 | return cmdTimeout; |
Matt Briggs | 50:e89647e77fd5 | 88 | } |
Matt Briggs | 57:bdac7dd17af2 | 89 | |
Matt Briggs | 57:bdac7dd17af2 | 90 | CmdResult DS2408::disableTestMode() |
Matt Briggs | 57:bdac7dd17af2 | 91 | { |
Matt Briggs | 57:bdac7dd17af2 | 92 | mMaster->reset(); |
Matt Briggs | 57:bdac7dd17af2 | 93 | mMaster->write(0x96); |
Matt Briggs | 57:bdac7dd17af2 | 94 | |
Matt Briggs | 57:bdac7dd17af2 | 95 | for (uint8_t i = 0; i < 8; i++) mMaster->write(mRomAddr[i]); |
Matt Briggs | 57:bdac7dd17af2 | 96 | |
Matt Briggs | 57:bdac7dd17af2 | 97 | mMaster->write(0x3C); |
Matt Briggs | 57:bdac7dd17af2 | 98 | mMaster->reset(); |
Matt Briggs | 57:bdac7dd17af2 | 99 | return cmdSuccess; |
Matt Briggs | 57:bdac7dd17af2 | 100 | } |