Matt Briggs / Mbed OS xDotBridge_update_dev_latest

Fork to see if I can get working

Dependencies:   BufferedSerial OneWire WinbondSPIFlash libxDot-dev-mbed5-deprecated

Fork of xDotBridge_update_test20180823 by Matt Briggs

xDotBridge/src/DS2408.cpp@40:2ec4be320961, 2017-01-26 (annotated)

Committer:
Matt Briggs
Date:
Thu Jan 26 17:36:59 2017 -0700
Revision:
40:2ec4be320961
Child:
50:e89647e77fd5
Fixed include hell.  Refactored to group all header in same location

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Matt Briggs 40:2ec4be320961 1 #include "DS2408.h"
Matt Briggs 40:2ec4be320961 2
Matt Briggs 40:2ec4be320961 3 enum DS2408Cmd {
Matt Briggs 40:2ec4be320961 4 registerReadCmd = 0xF0,
Matt Briggs 40:2ec4be320961 5 channelAccessReadCmd = 0xF5,
Matt Briggs 40:2ec4be320961 6 channelAccessWriteCmd = 0x5A
Matt Briggs 40:2ec4be320961 7 };
Matt Briggs 40:2ec4be320961 8
Matt Briggs 40:2ec4be320961 9 DS2408::DS2408(OneWire *owMaster, uint8_t romAddr[8])
Matt Briggs 40:2ec4be320961 10 {
Matt Briggs 40:2ec4be320961 11 mMaster = owMaster;
Matt Briggs 40:2ec4be320961 12 std::memcpy(mRomAddr, romAddr, sizeof(mRomAddr));
Matt Briggs 40:2ec4be320961 13 }
Matt Briggs 40:2ec4be320961 14
Matt Briggs 40:2ec4be320961 15 CmdResult DS2408::init()
Matt Briggs 40:2ec4be320961 16 {
Matt Briggs 40:2ec4be320961 17 mMaster->reset();
Matt Briggs 40:2ec4be320961 18 // TODO implement safety cancel test mode recommendation
Matt Briggs 40:2ec4be320961 19 return cmdSuccess;
Matt Briggs 40:2ec4be320961 20 }
Matt Briggs 40:2ec4be320961 21
Matt Briggs 40:2ec4be320961 22 CmdResult DS2408::registerRead(uint8_t addr, uint8_t &val)
Matt Briggs 40:2ec4be320961 23 {
Matt Briggs 40:2ec4be320961 24 uint8_t addrArray[] = {0x00, 0x00};
Matt Briggs 40:2ec4be320961 25 addrArray[0] = addr;
Matt Briggs 40:2ec4be320961 26 mMaster->reset();
Matt Briggs 40:2ec4be320961 27 mMaster->select(mRomAddr);
Matt Briggs 40:2ec4be320961 28 mMaster->write(registerReadCmd); // Read Register Command
Matt Briggs 40:2ec4be320961 29 mMaster->write_bytes(addrArray, 2); // Write 2 byte addr
Matt Briggs 40:2ec4be320961 30 val = mMaster->read();
Matt Briggs 40:2ec4be320961 31 // logDebug("Reg Value: %02x\n", result);
Matt Briggs 40:2ec4be320961 32 return cmdSuccess;
Matt Briggs 40:2ec4be320961 33 }
Matt Briggs 40:2ec4be320961 34
Matt Briggs 40:2ec4be320961 35 CmdResult DS2408::pioLogicRead(uint8_t &val)
Matt Briggs 40:2ec4be320961 36 {
Matt Briggs 40:2ec4be320961 37 return registerRead(pioLogicStateReg, val);
Matt Briggs 40:2ec4be320961 38 }
Matt Briggs 40:2ec4be320961 39
Matt Briggs 40:2ec4be320961 40 CmdResult DS2408::pioLogicWrite(uint8_t val)
Matt Briggs 40:2ec4be320961 41 {
Matt Briggs 40:2ec4be320961 42 mMaster->reset();
Matt Briggs 40:2ec4be320961 43 mMaster->select(mRomAddr);
Matt Briggs 40:2ec4be320961 44 mMaster->write(channelAccessWriteCmd);
Matt Briggs 40:2ec4be320961 45 mMaster->write(val);
Matt Briggs 40:2ec4be320961 46 mMaster->write(~val); // Need to write complement to ensure no bit errors
Matt Briggs 40:2ec4be320961 47 uint8_t result = mMaster->read();
Matt Briggs 40:2ec4be320961 48 if (result == 0xAA) {
Matt Briggs 40:2ec4be320961 49 return cmdSuccess;
Matt Briggs 40:2ec4be320961 50 }
Matt Briggs 40:2ec4be320961 51 else {
Matt Briggs 40:2ec4be320961 52 return cmdError;
Matt Briggs 40:2ec4be320961 53 }
Matt Briggs 40:2ec4be320961 54 }