Matt Briggs / Mbed OS xDotBridge_update_dev_latest

Fork to see if I can get working

Dependencies:   BufferedSerial OneWire WinbondSPIFlash libxDot-dev-mbed5-deprecated

Fork of xDotBridge_update_test20180823 by Matt Briggs

xDotBridge/src/DS2408.cpp@56:40b454c952cc, 2017-02-27 (annotated)

Committer:
Matt Briggs
Date:
Mon Feb 27 14:06:54 2017 -0700
Revision:
56:40b454c952cc
Parent:
50:e89647e77fd5
Child:
57:bdac7dd17af2
Updated test BBIO to v3.  Added some sanity checks for LRR if on a new board.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Matt Briggs 40:2ec4be320961 1 #include "DS2408.h"
Matt Briggs 40:2ec4be320961 2
Matt Briggs 40:2ec4be320961 3 enum DS2408Cmd {
Matt Briggs 40:2ec4be320961 4 registerReadCmd = 0xF0,
Matt Briggs 40:2ec4be320961 5 channelAccessReadCmd = 0xF5,
Matt Briggs 40:2ec4be320961 6 channelAccessWriteCmd = 0x5A
Matt Briggs 40:2ec4be320961 7 };
Matt Briggs 40:2ec4be320961 8
Matt Briggs 40:2ec4be320961 9 DS2408::DS2408(OneWire *owMaster, uint8_t romAddr[8])
Matt Briggs 40:2ec4be320961 10 {
Matt Briggs 40:2ec4be320961 11 mMaster = owMaster;
Matt Briggs 40:2ec4be320961 12 std::memcpy(mRomAddr, romAddr, sizeof(mRomAddr));
Matt Briggs 40:2ec4be320961 13 }
Matt Briggs 40:2ec4be320961 14
Matt Briggs 40:2ec4be320961 15 CmdResult DS2408::init()
Matt Briggs 40:2ec4be320961 16 {
Matt Briggs 40:2ec4be320961 17 mMaster->reset();
Matt Briggs 40:2ec4be320961 18 // TODO implement safety cancel test mode recommendation
Matt Briggs 40:2ec4be320961 19 return cmdSuccess;
Matt Briggs 40:2ec4be320961 20 }
Matt Briggs 40:2ec4be320961 21
Matt Briggs 56:40b454c952cc 22 CmdResult DS2408::registerReadReliable(uint8_t addr, uint8_t &val)
Matt Briggs 56:40b454c952cc 23 {
Matt Briggs 56:40b454c952cc 24 uint8_t result = 0;
Matt Briggs 56:40b454c952cc 25 uint8_t result1 = 0xFF;
Matt Briggs 56:40b454c952cc 26 uint8_t cmdResult;
Matt Briggs 56:40b454c952cc 27 cmdResult = registerRead(addr, result);
Matt Briggs 56:40b454c952cc 28 for (int i=0; i < DS2408_NRETRIES; i++) {
Matt Briggs 56:40b454c952cc 29 cmdResult = registerRead(addr, result1);
Matt Briggs 56:40b454c952cc 30 if (cmdResult != cmdSuccess) {
Matt Briggs 56:40b454c952cc 31 continue;
Matt Briggs 56:40b454c952cc 32 }
Matt Briggs 56:40b454c952cc 33 // Check they match
Matt Briggs 56:40b454c952cc 34 if (result == result1) {
Matt Briggs 56:40b454c952cc 35 val = result;
Matt Briggs 56:40b454c952cc 36 return cmdSuccess;
Matt Briggs 56:40b454c952cc 37 }
Matt Briggs 56:40b454c952cc 38 else {
Matt Briggs 56:40b454c952cc 39 result = result1;
Matt Briggs 56:40b454c952cc 40 }
Matt Briggs 56:40b454c952cc 41 }
Matt Briggs 56:40b454c952cc 42 return cmdTimeout;
Matt Briggs 56:40b454c952cc 43 }
Matt Briggs 56:40b454c952cc 44
Matt Briggs 40:2ec4be320961 45 CmdResult DS2408::registerRead(uint8_t addr, uint8_t &val)
Matt Briggs 40:2ec4be320961 46 {
Matt Briggs 40:2ec4be320961 47 uint8_t addrArray[] = {0x00, 0x00};
Matt Briggs 40:2ec4be320961 48 addrArray[0] = addr;
Matt Briggs 40:2ec4be320961 49 mMaster->reset();
Matt Briggs 40:2ec4be320961 50 mMaster->select(mRomAddr);
Matt Briggs 40:2ec4be320961 51 mMaster->write(registerReadCmd); // Read Register Command
Matt Briggs 40:2ec4be320961 52 mMaster->write_bytes(addrArray, 2); // Write 2 byte addr
Matt Briggs 40:2ec4be320961 53 val = mMaster->read();
Matt Briggs 40:2ec4be320961 54 // logDebug("Reg Value: %02x\n", result);
Matt Briggs 40:2ec4be320961 55 return cmdSuccess;
Matt Briggs 40:2ec4be320961 56 }
Matt Briggs 40:2ec4be320961 57
Matt Briggs 40:2ec4be320961 58 CmdResult DS2408::pioLogicRead(uint8_t &val)
Matt Briggs 40:2ec4be320961 59 {
Matt Briggs 40:2ec4be320961 60 return registerRead(pioLogicStateReg, val);
Matt Briggs 40:2ec4be320961 61 }
Matt Briggs 40:2ec4be320961 62
Matt Briggs 50:e89647e77fd5 63 CmdResult DS2408::pioLogicReliableRead(uint8_t &val)
Matt Briggs 50:e89647e77fd5 64 {
Matt Briggs 56:40b454c952cc 65 return registerReadReliable(pioLogicStateReg, val);
Matt Briggs 50:e89647e77fd5 66 }
Matt Briggs 50:e89647e77fd5 67
Matt Briggs 40:2ec4be320961 68 CmdResult DS2408::pioLogicWrite(uint8_t val)
Matt Briggs 40:2ec4be320961 69 {
Matt Briggs 40:2ec4be320961 70 mMaster->reset();
Matt Briggs 40:2ec4be320961 71 mMaster->select(mRomAddr);
Matt Briggs 40:2ec4be320961 72 mMaster->write(channelAccessWriteCmd);
Matt Briggs 40:2ec4be320961 73 mMaster->write(val);
Matt Briggs 40:2ec4be320961 74 mMaster->write(~val); // Need to write complement to ensure no bit errors
Matt Briggs 40:2ec4be320961 75 uint8_t result = mMaster->read();
Matt Briggs 40:2ec4be320961 76 if (result == 0xAA) {
Matt Briggs 40:2ec4be320961 77 return cmdSuccess;
Matt Briggs 40:2ec4be320961 78 }
Matt Briggs 40:2ec4be320961 79 else {
Matt Briggs 40:2ec4be320961 80 return cmdError;
Matt Briggs 40:2ec4be320961 81 }
Matt Briggs 40:2ec4be320961 82 }
Matt Briggs 50:e89647e77fd5 83
Matt Briggs 50:e89647e77fd5 84 CmdResult DS2408::pioLogicReliableWrite(uint8_t val) {
Matt Briggs 50:e89647e77fd5 85 uint8_t result;
Matt Briggs 50:e89647e77fd5 86 for (int i=0; i < DS2408_NRETRIES; i++) {
Matt Briggs 50:e89647e77fd5 87 result = pioLogicWrite(val);
Matt Briggs 50:e89647e77fd5 88 if (result == cmdSuccess) {
Matt Briggs 50:e89647e77fd5 89 return cmdSuccess;
Matt Briggs 50:e89647e77fd5 90 }
Matt Briggs 50:e89647e77fd5 91 }
Matt Briggs 50:e89647e77fd5 92 return cmdTimeout;
Matt Briggs 50:e89647e77fd5 93 }