Matt Briggs / Mbed OS xDotBridge_update_dev_latest

Fork to see if I can get working

Dependencies:   BufferedSerial OneWire WinbondSPIFlash libxDot-dev-mbed5-deprecated

Fork of xDotBridge_update_test20180823 by Matt Briggs

xDotBridge/src/main.cpp@40:2ec4be320961, 2017-01-26 (annotated)

Committer:
Matt Briggs
Date:
Thu Jan 26 17:36:59 2017 -0700
Revision:
40:2ec4be320961
Parent:
39:64f79fa6e3cc
Child:
41:9ef4c4d77711
Fixed include hell.  Refactored to group all header in same location

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Matt Briggs 34:5618603e5fc3 1 #include <math.h>
Matt Briggs 22:9453658b8d4b 2 #include "config.h"
Matt Briggs 30:2e673a672884 3 #include "xdot_flash.h"
Mike Fiore 11:d2e31743433a 4 #include "dot_util.h"
Mike Fiore 14:19fae4509473 5 #include "RadioEvent.h"
Matt Briggs 34:5618603e5fc3 6 #include <OneWire.h>
Matt Briggs 22:9453658b8d4b 7
mfiore 17:d4f82e16de5f 8 /////////////////////////////////////////////////////////////////////////////
mfiore 17:d4f82e16de5f 9 // -------------------- DOT LIBRARY REQUIRED ------------------------------//
mfiore 17:d4f82e16de5f 10 // * Because these example programs can be used for both mDot and xDot //
mfiore 17:d4f82e16de5f 11 // devices, the LoRa stack is not included. The libmDot library should //
mfiore 17:d4f82e16de5f 12 // be imported if building for mDot devices. The libxDot library //
mfiore 17:d4f82e16de5f 13 // should be imported if building for xDot devices. //
mfiore 17:d4f82e16de5f 14 // * https://developer.mbed.org/teams/MultiTech/code/libmDot-dev-mbed5/ //
mfiore 17:d4f82e16de5f 15 // * https://developer.mbed.org/teams/MultiTech/code/libmDot-mbed5/ //
mfiore 17:d4f82e16de5f 16 // * https://developer.mbed.org/teams/MultiTech/code/libxDot-dev-mbed5/ //
mfiore 17:d4f82e16de5f 17 // * https://developer.mbed.org/teams/MultiTech/code/libxDot-mbed5/ //
mfiore 17:d4f82e16de5f 18 /////////////////////////////////////////////////////////////////////////////
mfiore 17:d4f82e16de5f 19
Mike Fiore 11:d2e31743433a 20 /////////////////////////////////////////////////////////////
Mike Fiore 11:d2e31743433a 21 // * these options must match between the two devices in //
Mike Fiore 11:d2e31743433a 22 // order for communication to be successful
Mike Fiore 11:d2e31743433a 23 /////////////////////////////////////////////////////////////
Mike Fiore 11:d2e31743433a 24 static uint8_t network_address[] = { 0x01, 0x02, 0x03, 0x04 };
Mike Fiore 11:d2e31743433a 25 static uint8_t network_session_key[] = { 0x01, 0x02, 0x03, 0x04, 0x01, 0x02, 0x03, 0x04, 0x01, 0x02, 0x03, 0x04, 0x01, 0x02, 0x03, 0x04 };
mbriggs_vortex 19:75b28b4117cc 26 static uint8_t data_session_key[] = { 0x01, 0x02, 0x03, 0x04, 0x01, 0x02, 0x03, 0x04, 0x01, 0x02, 0x03, 0x04, 0x01, 0x02, 0x03, 0x04 };
Mike Fiore 11:d2e31743433a 27
Matt Briggs 26:9411b26a5084 28 // wireless bridge protocol
Matt Briggs 31:9c535a708ae9 29 const uint8_t TX_PWR = 20; // 20 dBm
Matt Briggs 31:9c535a708ae9 30 const float RX_SLEEP_TIME = 2000; // ms (one second resolution, min 2 seconds)
Matt Briggs 31:9c535a708ae9 31 const uint8_t TX_TIME = 30; // in ms
Matt Briggs 26:9411b26a5084 32
Matt Briggs 31:9c535a708ae9 33 //const uint8_t maxPayloadSize = 10; // Number of bytes (used for toa calcultion)
Matt Briggs 31:9c535a708ae9 34
Matt Briggs 31:9c535a708ae9 35 ///////////////////////
Matt Briggs 31:9c535a708ae9 36 // I/O Configuration //
Matt Briggs 31:9c535a708ae9 37 ///////////////////////
Matt Briggs 29:e05e35976cfe 38 DigitalOut led1(GPIO0);
Matt Briggs 29:e05e35976cfe 39 AnalogIn an1(GPIO1);
Matt Briggs 29:e05e35976cfe 40 AnalogIn an2(GPIO2);
Matt Briggs 29:e05e35976cfe 41
Matt Briggs 29:e05e35976cfe 42 // Inputs
Matt Briggs 37:31f8e9c5d075 43 //DigitalIn gpio3(GPIO3);
Matt Briggs 31:9c535a708ae9 44 //DigitalIn wake_DOUT(WAKE);
Matt Briggs 37:31f8e9c5d075 45 //DigitalIn i2cOut1(I2C1_SCL);
Matt Briggs 37:31f8e9c5d075 46 //DigitalIn i2cOut2(I2C1_SDA);
Matt Briggs 38:8a512e23d99e 47 InterruptIn intTest(I2C1_SDA);
Matt Briggs 33:c7bb3fbc024a 48 //DigitalIn uartOut1(UART1_CTS);
Matt Briggs 33:c7bb3fbc024a 49 //DigitalIn uartOut2(UART1_RTS);
Matt Briggs 33:c7bb3fbc024a 50 //DigitalIn jtag_gpio1(SWDIO);
Matt Briggs 33:c7bb3fbc024a 51 //DigitalIn jtag_gpio2(SWCLK);
Matt Briggs 29:e05e35976cfe 52
Matt Briggs 29:e05e35976cfe 53 // Outputs
Matt Briggs 29:e05e35976cfe 54 //DigitalOut gpio3(GPIO3);
Matt Briggs 29:e05e35976cfe 55 ////DigitalOut wake_DOUT(WAKE);
Matt Briggs 29:e05e35976cfe 56 //DigitalOut i2cOut1(I2C1_SCL);
Matt Briggs 29:e05e35976cfe 57 //DigitalOut i2cOut2(I2C1_SDA);
Matt Briggs 29:e05e35976cfe 58 //
Matt Briggs 29:e05e35976cfe 59 //DigitalOut uartOut1(UART1_CTS);
Matt Briggs 29:e05e35976cfe 60 //DigitalOut uartOut2(UART1_RTS);
Matt Briggs 29:e05e35976cfe 61
Mike Fiore 11:d2e31743433a 62 mDot* dot = NULL;
Mike Fiore 11:d2e31743433a 63
Mike Fiore 11:d2e31743433a 64 Serial pc(USBTX, USBRX);
Mike Fiore 11:d2e31743433a 65
Matt Briggs 39:64f79fa6e3cc 66 unsigned int callbackTime = 0;
Matt Briggs 39:64f79fa6e3cc 67
Matt Briggs 39:64f79fa6e3cc 68 void testCallback () {
Matt Briggs 39:64f79fa6e3cc 69 callbackTime = us_ticker_read();
Matt Briggs 39:64f79fa6e3cc 70 }
Matt Briggs 39:64f79fa6e3cc 71
Mike Fiore 11:d2e31743433a 72 int main() {
Matt Briggs 31:9c535a708ae9 73 unsigned int wakeMode;
Matt Briggs 31:9c535a708ae9 74 RadioEvent events; // Custom event handler for automatically displaying RX data
Mike Fiore 11:d2e31743433a 75 uint32_t tx_frequency;
Mike Fiore 11:d2e31743433a 76 uint8_t tx_datarate;
Mike Fiore 11:d2e31743433a 77 uint8_t tx_power;
Mike Fiore 11:d2e31743433a 78 uint8_t frequency_band;
Mike Fiore 11:d2e31743433a 79
Mike Fiore 11:d2e31743433a 80 pc.baud(115200);
Mike Fiore 11:d2e31743433a 81
Matt Briggs 27:6b68ff715ae1 82 mts::MTSLog::setLogLevel(mts::MTSLog::TRACE_LEVEL);
Mike Fiore 11:d2e31743433a 83
Mike Fiore 11:d2e31743433a 84 dot = mDot::getInstance();
Mike Fiore 11:d2e31743433a 85
Mike Fiore 16:a3832552dfe1 86 logInfo("mbed-os library version: %d", MBED_LIBRARY_VERSION);
Mike Fiore 16:a3832552dfe1 87
Mike Fiore 12:ec9768677cea 88 // start from a well-known state
Mike Fiore 12:ec9768677cea 89 logInfo("defaulting Dot configuration");
Mike Fiore 12:ec9768677cea 90 dot->resetConfig();
Mike Fiore 12:ec9768677cea 91
Mike Fiore 11:d2e31743433a 92 // make sure library logging is turned on
Matt Briggs 27:6b68ff715ae1 93 dot->setLogLevel(mts::MTSLog::INFO_LEVEL);
Mike Fiore 11:d2e31743433a 94
Mike Fiore 11:d2e31743433a 95 // attach the custom events handler
Mike Fiore 11:d2e31743433a 96 dot->setEvents(&events);
Mike Fiore 11:d2e31743433a 97
Matt Briggs 31:9c535a708ae9 98 // Setup programmable voltage detector
Matt Briggs 31:9c535a708ae9 99 // PVD_LEVEL0 Falling 1.85
Matt Briggs 31:9c535a708ae9 100 // PVD_LEVEL1 Falling 2.04
Matt Briggs 31:9c535a708ae9 101 // PVD_LEVEL2 Falling 2.24
Matt Briggs 31:9c535a708ae9 102 // PVD_LEVEL3 Falling 2.44
Matt Briggs 31:9c535a708ae9 103 // PVD_LEVEL4 Falling 2.64
Matt Briggs 31:9c535a708ae9 104 // PVD_LEVEL5 Falling 2.84
Matt Briggs 31:9c535a708ae9 105 // PVD_LEVEL6 Falling 3.05
Matt Briggs 31:9c535a708ae9 106 PWR_PVDTypeDef pvdConfig;
Matt Briggs 31:9c535a708ae9 107 pvdConfig.Mode = PWR_PVD_MODE_NORMAL;
Matt Briggs 31:9c535a708ae9 108 pvdConfig.PVDLevel = PWR_PVDLEVEL_5;
Matt Briggs 31:9c535a708ae9 109
Matt Briggs 31:9c535a708ae9 110 HAL_PWR_ConfigPVD(&pvdConfig);
Matt Briggs 31:9c535a708ae9 111 HAL_PWR_EnablePVD();
Matt Briggs 31:9c535a708ae9 112 logInfo("Programmable Voltage Detector set for level: %d", pvdConfig.PVDLevel);
Matt Briggs 31:9c535a708ae9 113
Matt Briggs 31:9c535a708ae9 114 // TODO setup IO here
Matt Briggs 31:9c535a708ae9 115
Mike Fiore 11:d2e31743433a 116 // update configuration if necessary
Matt Briggs 31:9c535a708ae9 117 logInfo("Setting up peer to peer configuration");
Mike Fiore 11:d2e31743433a 118 if (dot->getJoinMode() != mDot::PEER_TO_PEER) {
Mike Fiore 11:d2e31743433a 119 logInfo("changing network join mode to PEER_TO_PEER");
Mike Fiore 11:d2e31743433a 120 if (dot->setJoinMode(mDot::PEER_TO_PEER) != mDot::MDOT_OK) {
Mike Fiore 11:d2e31743433a 121 logError("failed to set network join mode to PEER_TO_PEER");
Mike Fiore 11:d2e31743433a 122 }
Mike Fiore 11:d2e31743433a 123 }
Mike Fiore 11:d2e31743433a 124 frequency_band = dot->getFrequencyBand();
Mike Fiore 11:d2e31743433a 125 switch (frequency_band) {
Mike Fiore 11:d2e31743433a 126 case mDot::FB_EU868:
Mike Fiore 11:d2e31743433a 127 // 250kHz channels achieve higher throughput
Mike Fiore 11:d2e31743433a 128 // DR6 : SF7 @ 250kHz
Mike Fiore 11:d2e31743433a 129 // DR0 - DR5 (125kHz channels) available but much slower
Mike Fiore 11:d2e31743433a 130 tx_frequency = 869850000;
Mike Fiore 11:d2e31743433a 131 tx_datarate = mDot::DR6;
Mike Fiore 11:d2e31743433a 132 // the 869850000 frequency is 100% duty cycle if the total power is under 7 dBm - tx power 4 + antenna gain 3 = 7
Mike Fiore 11:d2e31743433a 133 tx_power = 4;
Mike Fiore 11:d2e31743433a 134 break;
Mike Fiore 11:d2e31743433a 135 case mDot::FB_US915:
Mike Fiore 11:d2e31743433a 136 case mDot::FB_AU915:
Mike Fiore 11:d2e31743433a 137 default:
Mike Fiore 11:d2e31743433a 138 // 500kHz channels achieve highest throughput
Mike Fiore 11:d2e31743433a 139 // DR8 : SF12 @ 500kHz
Mike Fiore 11:d2e31743433a 140 // DR9 : SF11 @ 500kHz
Mike Fiore 11:d2e31743433a 141 // DR10 : SF10 @ 500kHz
Mike Fiore 11:d2e31743433a 142 // DR11 : SF9 @ 500kHz
Mike Fiore 11:d2e31743433a 143 // DR12 : SF8 @ 500kHz
Mike Fiore 11:d2e31743433a 144 // DR13 : SF7 @ 500kHz
Mike Fiore 11:d2e31743433a 145 // DR0 - DR3 (125kHz channels) available but much slower
Mike Fiore 11:d2e31743433a 146 tx_frequency = 915500000;
Mike Fiore 11:d2e31743433a 147 tx_datarate = mDot::DR13;
Mike Fiore 11:d2e31743433a 148 // 915 bands have no duty cycle restrictions, set tx power to max
Mike Fiore 11:d2e31743433a 149 tx_power = 20;
Mike Fiore 11:d2e31743433a 150 break;
Mike Fiore 11:d2e31743433a 151 }
Mike Fiore 11:d2e31743433a 152 // in PEER_TO_PEER mode there is no join request/response transaction
Mike Fiore 11:d2e31743433a 153 // as long as both Dots are configured correctly, they should be able to communicate
Mike Fiore 11:d2e31743433a 154 update_peer_to_peer_config(network_address, network_session_key, data_session_key, tx_frequency, tx_datarate, tx_power);
Mike Fiore 11:d2e31743433a 155
Matt Briggs 24:fdf87e4b72e5 156 ///////////////////////////////
Matt Briggs 24:fdf87e4b72e5 157 // Transmitter Configuration //
Matt Briggs 24:fdf87e4b72e5 158 ///////////////////////////////
Matt Briggs 27:6b68ff715ae1 159 #if BRIDGE_TX_BRUTE
Matt Briggs 24:fdf87e4b72e5 160 wakeMode = mDot::INTERRUPT;
Matt Briggs 24:fdf87e4b72e5 161 #endif
Matt Briggs 24:fdf87e4b72e5 162
Matt Briggs 24:fdf87e4b72e5 163 ////////////////////////////
Matt Briggs 24:fdf87e4b72e5 164 // Receiver Configuration //
Matt Briggs 24:fdf87e4b72e5 165 ////////////////////////////
Matt Briggs 27:6b68ff715ae1 166 #if BRIDGE_RX_BRUTE
Matt Briggs 24:fdf87e4b72e5 167 wakeMode = mDot::RTC_ALARM_OR_INTERRUPT;
Matt Briggs 24:fdf87e4b72e5 168 #endif
Matt Briggs 24:fdf87e4b72e5 169
Matt Briggs 24:fdf87e4b72e5 170 // Common Configuration
Matt Briggs 33:c7bb3fbc024a 171 dot->setTxWait(false);
Matt Briggs 33:c7bb3fbc024a 172 dot->setAck(0); // Disable Ack
Matt Briggs 25:fea776239709 173 dot->setWakePin(WAKE); // Use the wake pin as sleep interrupt
Matt Briggs 25:fea776239709 174 dot->setClass("C"); // Set class C
Matt Briggs 31:9c535a708ae9 175 dot->setTxPower(TX_PWR);
Matt Briggs 24:fdf87e4b72e5 176
Mike Fiore 11:d2e31743433a 177 // save changes to configuration
Mike Fiore 11:d2e31743433a 178 logInfo("saving configuration");
Mike Fiore 11:d2e31743433a 179 if (!dot->saveConfig()) {
Mike Fiore 11:d2e31743433a 180 logError("failed to save configuration");
Mike Fiore 11:d2e31743433a 181 }
Mike Fiore 11:d2e31743433a 182
Mike Fiore 11:d2e31743433a 183 // display configuration
Mike Fiore 11:d2e31743433a 184 display_config();
Mike Fiore 11:d2e31743433a 185
Matt Briggs 26:9411b26a5084 186
Matt Briggs 31:9c535a708ae9 187 unsigned int nTimesToTx = ceil(RX_SLEEP_TIME / ((float)TX_TIME));
Matt Briggs 31:9c535a708ae9 188 logInfo("RX_SLEEP_TIME %f, timeOnAir %lu, nTimesToTx %lu", RX_SLEEP_TIME, TX_TIME, nTimesToTx);
Matt Briggs 26:9411b26a5084 189
mbriggs_vortex 23:4ed894108882 190 uint16_t seqNum=0;
Matt Briggs 26:9411b26a5084 191 uint32_t cDwnLink = dot->getDownLinkCounter();
Matt Briggs 30:2e673a672884 192
Matt Briggs 39:64f79fa6e3cc 193 // Interrupt setup
Matt Briggs 40:2ec4be320961 194 intTest.mode(PullUp);
Matt Briggs 39:64f79fa6e3cc 195 intTest.fall(testCallback);
Matt Briggs 39:64f79fa6e3cc 196
Mike Fiore 11:d2e31743433a 197 while (true) {
Matt Briggs 25:fea776239709 198 std::vector<uint8_t> data;
Matt Briggs 31:9c535a708ae9 199 led1=0;
Mike Fiore 11:d2e31743433a 200
Mike Fiore 11:d2e31743433a 201 // join network if not joined
Mike Fiore 11:d2e31743433a 202 if (!dot->getNetworkJoinStatus()) {
Mike Fiore 11:d2e31743433a 203 join_network();
Mike Fiore 11:d2e31743433a 204 }
Mike Fiore 11:d2e31743433a 205
Matt Briggs 31:9c535a708ae9 206 //////////////////////
Matt Briggs 31:9c535a708ae9 207 // Common main loop //
Matt Briggs 31:9c535a708ae9 208 //////////////////////
Matt Briggs 31:9c535a708ae9 209
Matt Briggs 31:9c535a708ae9 210 // TODO sample rotary
Matt Briggs 31:9c535a708ae9 211 // TODO sample DIPs
Matt Briggs 31:9c535a708ae9 212
Matt Briggs 27:6b68ff715ae1 213 //////////////////////////////////////////
Matt Briggs 27:6b68ff715ae1 214 // Brute Protocol Transmitter main loop //
Matt Briggs 27:6b68ff715ae1 215 //////////////////////////////////////////
Matt Briggs 27:6b68ff715ae1 216 #if BRIDGE_TX_BRUTE
Matt Briggs 31:9c535a708ae9 217 #if LED_FEEDBACK
Matt Briggs 26:9411b26a5084 218 led1=1;
Matt Briggs 31:9c535a708ae9 219 #endif
Matt Briggs 31:9c535a708ae9 220 // TODO check for CC_IN
Matt Briggs 31:9c535a708ae9 221
Matt Briggs 25:fea776239709 222 data.push_back((seqNum >> 8) & 0xFF);
Matt Briggs 25:fea776239709 223 data.push_back(seqNum & 0xFF);
Matt Briggs 27:6b68ff715ae1 224 logInfo("Starting TX. Time: %lu, seqNum: %lu", us_ticker_read(), seqNum);
Matt Briggs 26:9411b26a5084 225 for(uint i=0;i<nTimesToTx;++i) {
Matt Briggs 27:6b68ff715ae1 226 dot->send(data);
Matt Briggs 26:9411b26a5084 227 }
mbriggs_vortex 23:4ed894108882 228 seqNum++;
Matt Briggs 25:fea776239709 229 led1=0;
Matt Briggs 27:6b68ff715ae1 230 logInfo("Finished TX. Time: %lu", us_ticker_read());
mbriggs_vortex 23:4ed894108882 231
Matt Briggs 28:b14b2926e916 232 sleep_save_io();
Matt Briggs 28:b14b2926e916 233 sleep_configure_io();
Matt Briggs 24:fdf87e4b72e5 234 dot->sleep(0, wakeMode, false); // Go to sleep until wake button
Matt Briggs 28:b14b2926e916 235 sleep_restore_io();
Matt Briggs 24:fdf87e4b72e5 236 #endif
Matt Briggs 27:6b68ff715ae1 237
Matt Briggs 27:6b68ff715ae1 238 ///////////////////////////////////////
Matt Briggs 27:6b68ff715ae1 239 // Brute Protocol Receiver main loop //
Matt Briggs 27:6b68ff715ae1 240 ///////////////////////////////////////
Matt Briggs 27:6b68ff715ae1 241 #if BRIDGE_RX_BRUTE
Matt Briggs 27:6b68ff715ae1 242 logInfo("Waiting for new message current DLC: %d, Time %d", cDwnLink, us_ticker_read());
Matt Briggs 31:9c535a708ae9 243 wait(TX_TIME/1000.0); // Wait TX_TIME
Matt Briggs 31:9c535a708ae9 244
Matt Briggs 31:9c535a708ae9 245 // TODO need to figure out what to do when DLC get resets
Matt Briggs 31:9c535a708ae9 246
Matt Briggs 26:9411b26a5084 247 if (cDwnLink < dot->getDownLinkCounter()) {
Matt Briggs 26:9411b26a5084 248 cDwnLink = dot->getDownLinkCounter();
Matt Briggs 26:9411b26a5084 249 dot->recv(data);
Matt Briggs 26:9411b26a5084 250 std::string dataStr(data.begin(), data.end());
Matt Briggs 26:9411b26a5084 251 logInfo("Got msg num: %d, payload: %s", seqNum, dataStr.c_str());
Matt Briggs 31:9c535a708ae9 252 // TODO add CC_OUT code here
Matt Briggs 26:9411b26a5084 253 seqNum++;
Matt Briggs 31:9c535a708ae9 254 #if LED_FEEDBACK
Matt Briggs 31:9c535a708ae9 255 led1 = 1;
Matt Briggs 26:9411b26a5084 256 wait(0.5);
Matt Briggs 31:9c535a708ae9 257 #endif
Matt Briggs 25:fea776239709 258 }
Matt Briggs 26:9411b26a5084 259 led1=0;
Matt Briggs 27:6b68ff715ae1 260 logInfo("Sleeping. Time %d", us_ticker_read());
Matt Briggs 28:b14b2926e916 261 sleep_save_io();
Matt Briggs 28:b14b2926e916 262 sleep_configure_io();
Matt Briggs 31:9c535a708ae9 263 // TODO maybe add if statement here to prevent double hits by sleeping for a longer time
Matt Briggs 26:9411b26a5084 264 dot->sleep(2, wakeMode, false); // Go to sleep until wake button
Matt Briggs 28:b14b2926e916 265 sleep_restore_io();
Matt Briggs 25:fea776239709 266 #endif
Matt Briggs 31:9c535a708ae9 267
Matt Briggs 29:e05e35976cfe 268 //////////////
Matt Briggs 29:e05e35976cfe 269 // I/O Play //
Matt Briggs 29:e05e35976cfe 270 //////////////
Matt Briggs 29:e05e35976cfe 271
Matt Briggs 38:8a512e23d99e 272 // Check interrupt
Matt Briggs 39:64f79fa6e3cc 273 logInfo("Callback last called @ %d", callbackTime);
Matt Briggs 38:8a512e23d99e 274
Matt Briggs 31:9c535a708ae9 275 // // Check Analog
Matt Briggs 31:9c535a708ae9 276 // logInfo("Read AN1/GPIO1: %f", an1.read());
Matt Briggs 31:9c535a708ae9 277 // logInfo("Read AN2/GPIO2: %f", an2.read()); // Ranges from 0.0 to 1.0
Matt Briggs 31:9c535a708ae9 278 //
Matt Briggs 31:9c535a708ae9 279 // // check inputs
Matt Briggs 31:9c535a708ae9 280 // logInfo("Read GPIO3: %d", gpio3.read());
Matt Briggs 31:9c535a708ae9 281 //// logInfo("Read wake_DOUT: %d", wake_DOUT.read());
Matt Briggs 31:9c535a708ae9 282 // logInfo("Read i2cOut1: %d", i2cOut1.read()); // Appears to be pulled up
Matt Briggs 31:9c535a708ae9 283 // logInfo("Read i2cOut2: %d", i2cOut2.read()); // Appears to be pulled up
Matt Briggs 31:9c535a708ae9 284 // logInfo("Read uartOut1: %d", uartOut1.read());
Matt Briggs 31:9c535a708ae9 285 // logInfo("Read uartOut2: %d", uartOut2.read());
Matt Briggs 31:9c535a708ae9 286 //
Matt Briggs 31:9c535a708ae9 287 // logInfo("Read jtag_gpio1: %d", jtag_gpio1.read());
Matt Briggs 31:9c535a708ae9 288 // logInfo("Read jtag_gpio2: %d", jtag_gpio2.read());
Matt Briggs 31:9c535a708ae9 289 //
Matt Briggs 31:9c535a708ae9 290 // if (jtag_gpio1.read() == 0) {
Matt Briggs 31:9c535a708ae9 291 // led1 = 1;
Matt Briggs 31:9c535a708ae9 292 // }
Matt Briggs 31:9c535a708ae9 293 // else {
Matt Briggs 31:9c535a708ae9 294 // led1 = 0;
Matt Briggs 31:9c535a708ae9 295 // }
Matt Briggs 29:e05e35976cfe 296
Matt Briggs 29:e05e35976cfe 297 // check digital outputs
Matt Briggs 29:e05e35976cfe 298 // led1 = !led1;
Matt Briggs 29:e05e35976cfe 299 // gpio3 = !gpio3;
Matt Briggs 29:e05e35976cfe 300 //// wake_DOUT = !wake_DOUT;
Matt Briggs 29:e05e35976cfe 301 // i2cOut1 = !i2cOut1;
Matt Briggs 29:e05e35976cfe 302 // i2cOut2 = !i2cOut2;
Matt Briggs 29:e05e35976cfe 303 //
Matt Briggs 29:e05e35976cfe 304 // uartOut1 = !uartOut1;
Matt Briggs 29:e05e35976cfe 305 // uartOut2 = !uartOut2;
Matt Briggs 29:e05e35976cfe 306
Matt Briggs 39:64f79fa6e3cc 307 logInfo("================================");
Matt Briggs 39:64f79fa6e3cc 308 wait(1.0);
Matt Briggs 34:5618603e5fc3 309 //////////////////
Matt Briggs 34:5618603e5fc3 310 // OneWire Play //
Matt Briggs 34:5618603e5fc3 311 //////////////////
Matt Briggs 34:5618603e5fc3 312
Matt Briggs 38:8a512e23d99e 313 // logInfo("Starting OneWire Play");
Matt Briggs 38:8a512e23d99e 314 // OneWire owMaster(I2C_SDA);
Matt Briggs 38:8a512e23d99e 315 // uint8_t addr[8];
Matt Briggs 38:8a512e23d99e 316 // uint8_t result;
Matt Briggs 38:8a512e23d99e 317 //
Matt Briggs 38:8a512e23d99e 318 // // Search Bus
Matt Briggs 38:8a512e23d99e 319 // logInfo("Starting OneWire Search");
Matt Briggs 38:8a512e23d99e 320 // do {
Matt Briggs 38:8a512e23d99e 321 // result = owMaster.search(addr);
Matt Briggs 38:8a512e23d99e 322 // logInfo("ROM Addr: %02x:%02x:%02x:%02x:%02x:%02x:%02x%02x\n",
Matt Briggs 38:8a512e23d99e 323 // addr[7],addr[6],addr[5],addr[4],addr[3],addr[2],addr[1],addr[0]);
Matt Briggs 38:8a512e23d99e 324 // } while (result == 1);
Matt Briggs 38:8a512e23d99e 325 // logInfo("Finished OneWire Search");
Matt Briggs 38:8a512e23d99e 326 // wait(1.0);
Matt Briggs 38:8a512e23d99e 327 //
Matt Briggs 38:8a512e23d99e 328 // uint8_t pioStateAddr[] = {0x88, 0x00};
Matt Briggs 38:8a512e23d99e 329 // uint8_t pioLatchAddr[] = {0x89, 0x00};
Matt Briggs 38:8a512e23d99e 330 // uint8_t printAddr = 0x88;
Matt Briggs 38:8a512e23d99e 331 // while (true) {
Matt Briggs 38:8a512e23d99e 332 // owMaster.reset();
Matt Briggs 38:8a512e23d99e 333 // owMaster.select(addr);
Matt Briggs 38:8a512e23d99e 334 // owMaster.write(0xF0); // Read Register Command
Matt Briggs 38:8a512e23d99e 335 // owMaster.write_bytes(pioStateAddr, 2); // Write 2 byte addr
Matt Briggs 38:8a512e23d99e 336 // printAddr = 0x88;
Matt Briggs 38:8a512e23d99e 337 // for (int i=0;i<8;i++) {
Matt Briggs 38:8a512e23d99e 338 // result = owMaster.read();
Matt Briggs 38:8a512e23d99e 339 // logInfo("%02x Reg Value: %02x\n", printAddr++, result);
Matt Briggs 38:8a512e23d99e 340 // }
Matt Briggs 38:8a512e23d99e 341 //
Matt Briggs 38:8a512e23d99e 342 // owMaster.reset();
Matt Briggs 38:8a512e23d99e 343 // owMaster.select(addr);
Matt Briggs 38:8a512e23d99e 344 // owMaster.write(0xF0); // Read Register Command
Matt Briggs 38:8a512e23d99e 345 // owMaster.write_bytes(pioLatchAddr, 2); // Write 2 byte addr
Matt Briggs 38:8a512e23d99e 346 // result = owMaster.read();
Matt Briggs 38:8a512e23d99e 347 // logInfo("Latch Reg Value: %02x\n", result);
Matt Briggs 38:8a512e23d99e 348 // // TODO try reading inverted 16-bit CRC
Matt Briggs 38:8a512e23d99e 349 //
Matt Briggs 38:8a512e23d99e 350 // wait(1.0);
Matt Briggs 38:8a512e23d99e 351 // // Try write
Matt Briggs 38:8a512e23d99e 352 // owMaster.reset();
Matt Briggs 38:8a512e23d99e 353 // owMaster.select(addr);
Matt Briggs 38:8a512e23d99e 354 // owMaster.write(0x5A); // Channel Access Write Command
Matt Briggs 38:8a512e23d99e 355 // uint8_t val = ~0xAA;
Matt Briggs 38:8a512e23d99e 356 // owMaster.write(val); // Pull-down all even bits
Matt Briggs 38:8a512e23d99e 357 // owMaster.write(~val); // Pull-down all even bits
Matt Briggs 38:8a512e23d99e 358 // result = owMaster.read();
Matt Briggs 38:8a512e23d99e 359 // logInfo("Confirm after write value: %02x, expected %02x\n", result, 0xAA);
Matt Briggs 38:8a512e23d99e 360 //
Matt Briggs 38:8a512e23d99e 361 // // Check if the read back is just a latch reg thing or a true logic state
Matt Briggs 38:8a512e23d99e 362 // wait(1.0);
Matt Briggs 40:2ec4be320961 363 // }
Mike Fiore 11:d2e31743433a 364 }
Mike Fiore 11:d2e31743433a 365
Mike Fiore 11:d2e31743433a 366 return 0;
Mike Fiore 11:d2e31743433a 367 }
Mike Fiore 11:d2e31743433a 368
Matt Briggs 27:6b68ff715ae1 369