mbed official / mbed-dsp

CMSIS DSP library

Dependents:   performance_timer Surfboard_ gps2rtty Capstone ... more

Legacy Warning

This is an mbed 2 library. To learn more about mbed OS 5, visit the docs.

cmsis_dsp/FilteringFunctions/arm_lms_norm_init_q31.c@3:7a284390b0ce, 2013-11-08 (annotated)

Committer:
mbed_official
Date:
Fri Nov 08 13:45:10 2013 +0000
Revision:
3:7a284390b0ce
Parent:
2:da51fb522205
Child:
5:3762170b6d4d
Synchronized with git revision e69956aba2f68a2a26ac26b051f8d349deaa1ce8

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 1:fdd22bb7aa52 1 /*-----------------------------------------------------------------------------
mbed_official 3:7a284390b0ce 2 * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
emilmont 1:fdd22bb7aa52 3 *
mbed_official 3:7a284390b0ce 4 * $Date: 17. January 2013
mbed_official 3:7a284390b0ce 5 * $Revision: V1.4.1
emilmont 1:fdd22bb7aa52 6 *
emilmont 2:da51fb522205 7 * Project: CMSIS DSP Library
emilmont 1:fdd22bb7aa52 8 * Title: arm_lms_norm_init_q31.c
emilmont 1:fdd22bb7aa52 9 *
emilmont 1:fdd22bb7aa52 10 * Description: Q31 NLMS initialization function.
emilmont 1:fdd22bb7aa52 11 *
emilmont 1:fdd22bb7aa52 12 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
emilmont 1:fdd22bb7aa52 13 *
mbed_official 3:7a284390b0ce 14 * Redistribution and use in source and binary forms, with or without
mbed_official 3:7a284390b0ce 15 * modification, are permitted provided that the following conditions
mbed_official 3:7a284390b0ce 16 * are met:
mbed_official 3:7a284390b0ce 17 * - Redistributions of source code must retain the above copyright
mbed_official 3:7a284390b0ce 18 * notice, this list of conditions and the following disclaimer.
mbed_official 3:7a284390b0ce 19 * - Redistributions in binary form must reproduce the above copyright
mbed_official 3:7a284390b0ce 20 * notice, this list of conditions and the following disclaimer in
mbed_official 3:7a284390b0ce 21 * the documentation and/or other materials provided with the
mbed_official 3:7a284390b0ce 22 * distribution.
mbed_official 3:7a284390b0ce 23 * - Neither the name of ARM LIMITED nor the names of its contributors
mbed_official 3:7a284390b0ce 24 * may be used to endorse or promote products derived from this
mbed_official 3:7a284390b0ce 25 * software without specific prior written permission.
mbed_official 3:7a284390b0ce 26 *
mbed_official 3:7a284390b0ce 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
mbed_official 3:7a284390b0ce 28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
mbed_official 3:7a284390b0ce 29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
mbed_official 3:7a284390b0ce 30 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
mbed_official 3:7a284390b0ce 31 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
mbed_official 3:7a284390b0ce 32 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
mbed_official 3:7a284390b0ce 33 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official 3:7a284390b0ce 34 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 3:7a284390b0ce 35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
mbed_official 3:7a284390b0ce 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
mbed_official 3:7a284390b0ce 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mbed_official 3:7a284390b0ce 38 * POSSIBILITY OF SUCH DAMAGE.
emilmont 1:fdd22bb7aa52 39 * ---------------------------------------------------------------------------*/
emilmont 1:fdd22bb7aa52 40
emilmont 1:fdd22bb7aa52 41 #include "arm_math.h"
emilmont 1:fdd22bb7aa52 42 #include "arm_common_tables.h"
emilmont 1:fdd22bb7aa52 43
emilmont 1:fdd22bb7aa52 44 /**
emilmont 1:fdd22bb7aa52 45 * @addtogroup LMS_NORM
emilmont 1:fdd22bb7aa52 46 * @{
emilmont 1:fdd22bb7aa52 47 */
emilmont 1:fdd22bb7aa52 48
emilmont 1:fdd22bb7aa52 49 /**
emilmont 1:fdd22bb7aa52 50 * @brief Initialization function for Q31 normalized LMS filter.
emilmont 1:fdd22bb7aa52 51 * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
emilmont 1:fdd22bb7aa52 52 * @param[in] numTaps number of filter coefficients.
emilmont 1:fdd22bb7aa52 53 * @param[in] *pCoeffs points to coefficient buffer.
emilmont 1:fdd22bb7aa52 54 * @param[in] *pState points to state buffer.
emilmont 1:fdd22bb7aa52 55 * @param[in] mu step size that controls filter coefficient updates.
emilmont 1:fdd22bb7aa52 56 * @param[in] blockSize number of samples to process.
emilmont 1:fdd22bb7aa52 57 * @param[in] postShift bit shift applied to coefficients.
emilmont 1:fdd22bb7aa52 58 * @return none.
emilmont 1:fdd22bb7aa52 59 *
emilmont 1:fdd22bb7aa52 60 * <b>Description:</b>
emilmont 1:fdd22bb7aa52 61 * \par
emilmont 1:fdd22bb7aa52 62 * <code>pCoeffs</code> points to the array of filter coefficients stored in time reversed order:
emilmont 1:fdd22bb7aa52 63 * <pre>
emilmont 1:fdd22bb7aa52 64 * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
emilmont 1:fdd22bb7aa52 65 * </pre>
emilmont 1:fdd22bb7aa52 66 * The initial filter coefficients serve as a starting point for the adaptive filter.
emilmont 1:fdd22bb7aa52 67 * <code>pState</code> points to an array of length <code>numTaps+blockSize-1</code> samples,
emilmont 1:fdd22bb7aa52 68 * where <code>blockSize</code> is the number of input samples processed by each call to <code>arm_lms_norm_q31()</code>.
emilmont 1:fdd22bb7aa52 69 */
emilmont 1:fdd22bb7aa52 70
emilmont 1:fdd22bb7aa52 71 void arm_lms_norm_init_q31(
emilmont 1:fdd22bb7aa52 72 arm_lms_norm_instance_q31 * S,
emilmont 1:fdd22bb7aa52 73 uint16_t numTaps,
emilmont 1:fdd22bb7aa52 74 q31_t * pCoeffs,
emilmont 1:fdd22bb7aa52 75 q31_t * pState,
emilmont 1:fdd22bb7aa52 76 q31_t mu,
emilmont 1:fdd22bb7aa52 77 uint32_t blockSize,
emilmont 1:fdd22bb7aa52 78 uint8_t postShift)
emilmont 1:fdd22bb7aa52 79 {
emilmont 1:fdd22bb7aa52 80 /* Assign filter taps */
emilmont 1:fdd22bb7aa52 81 S->numTaps = numTaps;
emilmont 1:fdd22bb7aa52 82
emilmont 1:fdd22bb7aa52 83 /* Assign coefficient pointer */
emilmont 1:fdd22bb7aa52 84 S->pCoeffs = pCoeffs;
emilmont 1:fdd22bb7aa52 85
emilmont 1:fdd22bb7aa52 86 /* Clear state buffer and size is always blockSize + numTaps - 1 */
emilmont 1:fdd22bb7aa52 87 memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q31_t));
emilmont 1:fdd22bb7aa52 88
emilmont 1:fdd22bb7aa52 89 /* Assign post Shift value applied to coefficients */
emilmont 1:fdd22bb7aa52 90 S->postShift = postShift;
emilmont 1:fdd22bb7aa52 91
emilmont 1:fdd22bb7aa52 92 /* Assign state pointer */
emilmont 1:fdd22bb7aa52 93 S->pState = pState;
emilmont 1:fdd22bb7aa52 94
emilmont 1:fdd22bb7aa52 95 /* Assign Step size value */
emilmont 1:fdd22bb7aa52 96 S->mu = mu;
emilmont 1:fdd22bb7aa52 97
emilmont 1:fdd22bb7aa52 98 /* Initialize reciprocal pointer table */
emilmont 1:fdd22bb7aa52 99 S->recipTable = (q31_t *) armRecipTableQ31;
emilmont 1:fdd22bb7aa52 100
emilmont 1:fdd22bb7aa52 101 /* Initialise Energy to zero */
emilmont 1:fdd22bb7aa52 102 S->energy = 0;
emilmont 1:fdd22bb7aa52 103
emilmont 1:fdd22bb7aa52 104 /* Initialise x0 to zero */
emilmont 1:fdd22bb7aa52 105 S->x0 = 0;
emilmont 1:fdd22bb7aa52 106
emilmont 1:fdd22bb7aa52 107 }
emilmont 1:fdd22bb7aa52 108
emilmont 1:fdd22bb7aa52 109 /**
emilmont 1:fdd22bb7aa52 110 * @} end of LMS_NORM group
emilmont 1:fdd22bb7aa52 111 */