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CMSIS DSP library

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cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_init_q31.c@5:3762170b6d4d, 2015-11-20 (annotated)

Committer:
mbed_official
Date:
Fri Nov 20 08:45:18 2015 +0000
Revision:
5:3762170b6d4d
Parent:
3:7a284390b0ce 
Synchronized with git revision 2eb940b9a73af188d3004a2575fdfbb05febe62b



Full URL: https://github.com/mbedmicro/mbed/commit/2eb940b9a73af188d3004a2575fdfbb05febe62b/



Added option to build rpc library. closes #1426

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 1:fdd22bb7aa52 1 /* ----------------------------------------------------------------------
mbed_official 5:3762170b6d4d 2 * Copyright (C) 2010-2014 ARM Limited. All rights reserved.
emilmont 1:fdd22bb7aa52 3 *
mbed_official 5:3762170b6d4d 4 * $Date: 19. March 2015
mbed_official 5:3762170b6d4d 5 * $Revision: V.1.4.5
emilmont 1:fdd22bb7aa52 6 *
emilmont 2:da51fb522205 7 * Project: CMSIS DSP Library
emilmont 2:da51fb522205 8 * Title: arm_biquad_cascade_df1_init_q31.c
emilmont 1:fdd22bb7aa52 9 *
emilmont 2:da51fb522205 10 * Description: Q31 Biquad cascade DirectFormI(DF1) filter initialization function.
emilmont 1:fdd22bb7aa52 11 *
emilmont 1:fdd22bb7aa52 12 *
emilmont 1:fdd22bb7aa52 13 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
emilmont 1:fdd22bb7aa52 14 *
mbed_official 3:7a284390b0ce 15 * Redistribution and use in source and binary forms, with or without
mbed_official 3:7a284390b0ce 16 * modification, are permitted provided that the following conditions
mbed_official 3:7a284390b0ce 17 * are met:
mbed_official 3:7a284390b0ce 18 * - Redistributions of source code must retain the above copyright
mbed_official 3:7a284390b0ce 19 * notice, this list of conditions and the following disclaimer.
mbed_official 3:7a284390b0ce 20 * - Redistributions in binary form must reproduce the above copyright
mbed_official 3:7a284390b0ce 21 * notice, this list of conditions and the following disclaimer in
mbed_official 3:7a284390b0ce 22 * the documentation and/or other materials provided with the
mbed_official 3:7a284390b0ce 23 * distribution.
mbed_official 3:7a284390b0ce 24 * - Neither the name of ARM LIMITED nor the names of its contributors
mbed_official 3:7a284390b0ce 25 * may be used to endorse or promote products derived from this
mbed_official 3:7a284390b0ce 26 * software without specific prior written permission.
mbed_official 3:7a284390b0ce 27 *
mbed_official 3:7a284390b0ce 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
mbed_official 3:7a284390b0ce 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
mbed_official 3:7a284390b0ce 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
mbed_official 3:7a284390b0ce 31 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
mbed_official 3:7a284390b0ce 32 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
mbed_official 3:7a284390b0ce 33 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
mbed_official 3:7a284390b0ce 34 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official 3:7a284390b0ce 35 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 3:7a284390b0ce 36 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
mbed_official 3:7a284390b0ce 37 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
mbed_official 3:7a284390b0ce 38 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mbed_official 3:7a284390b0ce 39 * POSSIBILITY OF SUCH DAMAGE.
emilmont 1:fdd22bb7aa52 40 * -------------------------------------------------------------------- */
emilmont 1:fdd22bb7aa52 41
emilmont 1:fdd22bb7aa52 42 #include "arm_math.h"
emilmont 1:fdd22bb7aa52 43
emilmont 1:fdd22bb7aa52 44 /**
emilmont 1:fdd22bb7aa52 45 * @ingroup groupFilters
emilmont 1:fdd22bb7aa52 46 */
emilmont 1:fdd22bb7aa52 47
emilmont 1:fdd22bb7aa52 48 /**
emilmont 1:fdd22bb7aa52 49 * @addtogroup BiquadCascadeDF1
emilmont 1:fdd22bb7aa52 50 * @{
emilmont 1:fdd22bb7aa52 51 */
emilmont 1:fdd22bb7aa52 52
emilmont 1:fdd22bb7aa52 53 /**
emilmont 1:fdd22bb7aa52 54 * @details
emilmont 1:fdd22bb7aa52 55 *
emilmont 1:fdd22bb7aa52 56 * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure.
emilmont 1:fdd22bb7aa52 57 * @param[in] numStages number of 2nd order stages in the filter.
emilmont 1:fdd22bb7aa52 58 * @param[in] *pCoeffs points to the filter coefficients buffer.
emilmont 1:fdd22bb7aa52 59 * @param[in] *pState points to the state buffer.
emilmont 1:fdd22bb7aa52 60 * @param[in] postShift Shift to be applied after the accumulator. Varies according to the coefficients format
emilmont 1:fdd22bb7aa52 61 * @return none
emilmont 1:fdd22bb7aa52 62 *
emilmont 1:fdd22bb7aa52 63 * <b>Coefficient and State Ordering:</b>
emilmont 1:fdd22bb7aa52 64 *
emilmont 1:fdd22bb7aa52 65 * \par
emilmont 1:fdd22bb7aa52 66 * The coefficients are stored in the array <code>pCoeffs</code> in the following order:
emilmont 1:fdd22bb7aa52 67 * <pre>
emilmont 1:fdd22bb7aa52 68 * {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
emilmont 1:fdd22bb7aa52 69 * </pre>
emilmont 1:fdd22bb7aa52 70 * where <code>b1x</code> and <code>a1x</code> are the coefficients for the first stage,
emilmont 1:fdd22bb7aa52 71 * <code>b2x</code> and <code>a2x</code> are the coefficients for the second stage,
emilmont 1:fdd22bb7aa52 72 * and so on. The <code>pCoeffs</code> array contains a total of <code>5*numStages</code> values.
emilmont 1:fdd22bb7aa52 73 *
emilmont 1:fdd22bb7aa52 74 * \par
emilmont 1:fdd22bb7aa52 75 * The <code>pState</code> points to state variables array.
emilmont 1:fdd22bb7aa52 76 * Each Biquad stage has 4 state variables <code>x[n-1], x[n-2], y[n-1],</code> and <code>y[n-2]</code>.
emilmont 1:fdd22bb7aa52 77 * The state variables are arranged in the <code>pState</code> array as:
emilmont 1:fdd22bb7aa52 78 * <pre>
emilmont 1:fdd22bb7aa52 79 * {x[n-1], x[n-2], y[n-1], y[n-2]}
emilmont 1:fdd22bb7aa52 80 * </pre>
emilmont 1:fdd22bb7aa52 81 * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.
emilmont 1:fdd22bb7aa52 82 * The state array has a total length of <code>4*numStages</code> values.
emilmont 1:fdd22bb7aa52 83 * The state variables are updated after each block of data is processed; the coefficients are untouched.
emilmont 1:fdd22bb7aa52 84 */
emilmont 1:fdd22bb7aa52 85
emilmont 1:fdd22bb7aa52 86 void arm_biquad_cascade_df1_init_q31(
emilmont 1:fdd22bb7aa52 87 arm_biquad_casd_df1_inst_q31 * S,
emilmont 1:fdd22bb7aa52 88 uint8_t numStages,
emilmont 1:fdd22bb7aa52 89 q31_t * pCoeffs,
emilmont 1:fdd22bb7aa52 90 q31_t * pState,
emilmont 1:fdd22bb7aa52 91 int8_t postShift)
emilmont 1:fdd22bb7aa52 92 {
emilmont 1:fdd22bb7aa52 93 /* Assign filter stages */
emilmont 1:fdd22bb7aa52 94 S->numStages = numStages;
emilmont 1:fdd22bb7aa52 95
emilmont 1:fdd22bb7aa52 96 /* Assign postShift to be applied to the output */
emilmont 1:fdd22bb7aa52 97 S->postShift = postShift;
emilmont 1:fdd22bb7aa52 98
emilmont 1:fdd22bb7aa52 99 /* Assign coefficient pointer */
emilmont 1:fdd22bb7aa52 100 S->pCoeffs = pCoeffs;
emilmont 1:fdd22bb7aa52 101
emilmont 1:fdd22bb7aa52 102 /* Clear state buffer and size is always 4 * numStages */
emilmont 1:fdd22bb7aa52 103 memset(pState, 0, (4u * (uint32_t) numStages) * sizeof(q31_t));
emilmont 1:fdd22bb7aa52 104
emilmont 1:fdd22bb7aa52 105 /* Assign state pointer */
emilmont 1:fdd22bb7aa52 106 S->pState = pState;
emilmont 1:fdd22bb7aa52 107 }
emilmont 1:fdd22bb7aa52 108
emilmont 1:fdd22bb7aa52 109 /**
emilmont 1:fdd22bb7aa52 110 * @} end of BiquadCascadeDF1 group
emilmont 1:fdd22bb7aa52 111 */