Comms between MAX 10 FPGA and ST uP

Revision:
19:bc9910b1c186
Parent:
18:62462a30d513
Child:
20:aacf2ebd93ff
--- a/FPGA_bus.h	Sun May 24 22:53:59 2020 +0000
+++ b/FPGA_bus.h	Mon May 25 14:14:17 2020 +0000
@@ -7,8 +7,6 @@
  */
 #include "mbed.h"
 
-extern Serial pc;
- 
 #ifndef  FPGA_bus_H
 #define  FPGA_bus_H