jim herd
Comms between MAX 10 FPGA and ST uP
Diff: FPGA_bus.h
- Revision:
- 20:aacf2ebd93ff
- Parent:
- 19:bc9910b1c186
- Child:
- 21:6b2b7a0e2d9a
--- a/FPGA_bus.h Mon May 25 14:14:17 2020 +0000
+++ b/FPGA_bus.h Mon Jun 15 21:29:40 2020 +0000
@@ -10,7 +10,12 @@
#ifndef FPGA_bus_H
#define FPGA_bus_H
-//
+//////////////////////////////////////////////////////////////////////////
+// MACROS
+
+#define LOOP_HERE for(;;)
+
+//////////////////////////////////////////////////////////////////////////
// Pin definitions
#define ASYNC_UP_RW_PIN PB_0
@@ -66,18 +71,22 @@
#define INPUT_BYTE_FROM_BUS (GPIOC->IDR & 0x000000FF)
#define ENABLE_GPIO_SUBSYSTEM (RCC->AHBENR |= RCC_AHBENR_GPIOCEN)
-//
+//////////////////////////////////////////////////////////////////////////
// FPGA constants
#define nS_IN_uS 1000
-#define FPGA_CLOCK_PERIOD_nS 20
+#define FPGA_CLOCK_PERIOD_nS 20
+#define NOS_BUS_CHECKS 3 // number of times to test bus
+#define BUS_TEST_TIMEOUT 1000 // loop counts for timeout test
-//
+//////////////////////////////////////////////////////////////////////////
// error codes
-#define NO_ERROR 0
+#define NO_ERROR 0
+#define BUS_FAIL -30
-#define LOOP_HERE for(;;)
+//////////////////////////////////////////////////////////////////////////
+// typedef structures
typedef struct {
uint8_t command;
@@ -96,16 +105,31 @@
enum {READ_BUS=0, WRITE_BUS=1};
enum {LOW=0, HIGH=1};
-//
+//////////////////////////////////////////////////////////////////////////
// SYS_data registers
enum {SYS_DATA_REG_ADDR=0};
-// PWM registers
+//////////////////////////////////////////////////////////////////////////
+// PWM registers with relative addresses
//
enum {PWM_PERIOD=0, PWM_ON_TIME=1, PWM_CONFIG=2, PWM_STATUS=3};
+//
+// constants to define bits in PWM config register
-// QE registers
+#define PWM_CONFIG_DEFAULT 0x00
+enum {PWM_OFF=0x0, PWM_ON=0x1};
+enum {INT_H_BRIDGE_OFF=0x0, INT_H_BRIDGE_ON=0x10000};
+enum {EXT_H_BRIDGE_OFF=0x0, EXT_H_BRIDGE_ON=0x20000};
+enum {MODE_PWM_CONTROL=0x0, MODE_DIR_CONTROL=0x40000};
+enum {MOTOR_COAST=0x0, MOTOR_FORWARD=0x100000, MOTOR_BACKWARD=0x300000, MOTOR_BRAKE=0xC00000};
+enum {NO_SWAP=0x0, YES_SWAP=0x1000000};
+enum {PWM_BRAKE_DWELL=0x0, PWM_COAST_DWELL=0x2000000};
+enum {NO_INVERT = 0x0, H_BRIDGE_1_INVERT=0x4000000, H_BRIDGE_2_INVERT=0x8000000, ALL_INVERT=0xC000000};
+enum {BACKWARD, FORWARD};
+
+//////////////////////////////////////////////////////////////////////////
+// QE registers with relative addresses
//
enum {QE_COUNT_BUFFER=0, QE_TURN_BUFFER=1, QE_SPEED_BUFFER=2, QE_SIM_PHASE_TIME=3,
QE_COUNTS_PER_REV=4, QE_CONFIG=5, QE_STATUS=6};
@@ -121,66 +145,66 @@
enum {QE_SPEED_CALC_FILTER_DISABLE=0x00, QE_SPEED_CALC_FILTER_ENABLE=0x20000};
enum {QE_FILTER_SAMPLE_2=0x00, QE_FILTER_SAMPLE_4=0x100000, QE_FILTER_SAMPLE_8=0x200000,
QE_FILTER_SAMPLE_16=0x300000, QE_FILTER_SAMPLE_32=0x400000};
-
-// RC servo registers
+
+//////////////////////////////////////////////////////////////////////////
+// RC servo registers with relative addresses
//
enum {RC_SERVO_PERIOD=0, RC_SERVO_CONFIG=1, RC_SERVO_STATUS=2, RC_SERVO_ON_TIME=3};
-//
-// constants to define bits in PWM config register
+//////////////////////////////////////////////////////////////////////////
+// FPGA_bus class
+// ==============
-#define PWM_CONFIG_DEFAULT 0x00
-enum {PWM_OFF=0x0, PWM_ON=0x1};
-enum {INT_H_BRIDGE_OFF=0x0, INT_H_BRIDGE_ON=0x10000};
-enum {EXT_H_BRIDGE_OFF=0x0, EXT_H_BRIDGE_ON=0x20000};
-enum {MODE_PWM_CONTROL=0x0, MODE_DIR_CONTROL=0x40000};
-enum {MOTOR_COAST=0x0, MOTOR_FORWARD=0x100000, MOTOR_BACKWARD=0x300000, MOTOR_BRAKE=0xC00000};
-enum {NO_SWAP=0x0, YES_SWAP=0x1000000};
-enum {PWM_BRAKE_DWELL=0x0, PWM_COAST_DWELL=0x2000000};
-enum {NO_INVERT = 0x0, H_BRIDGE_1_INVERT=0x4000000, H_BRIDGE_2_INVERT=0x8000000, ALL_INVERT=0xC000000};
-enum {BACKWARD, FORWARD};
-
-//DigitalOut async_uP_start(ASYNC_UP_START_PIN, LOW);
-//DigitalOut async_uP_handshake_1(ASYNC_UP_HANDSHAKE_1_PIN, LOW);
-//DigitalOut async_uP_RW(ASYNC_UP_RW_PIN, LOW);
-//DigitalOut async_uP_reset(ASYNC_UP_RESET_PIN, HIGH);
-//DigitalIn uP_ack(ASYNC_UP_ACK_PIN, PullDown);
-//DigitalIn uP_handshake_2(ASYNC_UP_HANDSHAKE_2_PIN);
-
class FPGA_bus {
public:
FPGA_bus(int nos_PWM = NOS_PWM_CHANNELS ,
int nos_QE = NOS_QE_CHANNELS ,
int nos_servo = NOS_RC_CHANNELS ); // constructor
-
- void initialise(void);
- void do_transaction(uint32_t command,
- uint32_t register_address,
- uint32_t register_data,
- uint32_t *data,
- uint32_t *status);
- uint32_t do_command(FPGA_packet_t cmd_packet);
- void write_register(uint32_t register_addr, uint32_t value);
- void set_PWM_period(uint32_t channel, float frequency);
- void set_PWM_duty(uint32_t channel, float percentage);
- void PWM_enable(uint32_t channel);
- void PWM_config(uint32_t channel, uint32_t config_value);
- void set_RC_period(void);
- void set_RC_period(uint32_t duty_uS);
- void set_RC_pulse(uint32_t channel, uint32_t pulse_uS);
- void enable_RC_channel(uint32_t channel);
- void disable_RC_channel(uint32_t channel);
- void QE_config(uint32_t channel, uint32_t config_value);
- void enable_speed_measure(uint32_t channel, uint32_t config_value, uint32_t phase_time);
+//
+// functions
+//
+ int32_t initialise(void);
+ void do_transaction(uint32_t command,
+ uint32_t register_address,
+ uint32_t register_data,
+ uint32_t *data,
+ uint32_t *status);
+ void write_register(uint32_t register_addr, uint32_t value);
+ void set_PWM_period(uint32_t channel, float frequency);
+ void set_PWM_duty(uint32_t channel, float percentage);
+ void PWM_enable(uint32_t channel);
+ void PWM_config(uint32_t channel, uint32_t config_value);
+ void set_RC_period(void);
+ void set_RC_period(uint32_t duty_uS);
+ void set_RC_pulse(uint32_t channel, uint32_t pulse_uS);
+ void enable_RC_channel(uint32_t channel);
+ void disable_RC_channel(uint32_t channel);
+ void QE_config(uint32_t channel, uint32_t config_value);
+ void enable_speed_measure(uint32_t channel, uint32_t config_value, uint32_t phase_time);
uint32_t read_speed_measure(uint32_t channel);
uint32_t read_count_measure(uint32_t channel);
- void update_FPGA_register_pointers(void);
-
uint32_t get_SYS_data(void);
-
+//
+// data
+//
int32_t global_FPGA_unit_error_flag;
+//
+// persistant system data
+//
+ struct SYS_data {
+ uint8_t major_version;
+ uint8_t minor_version;
+ uint8_t number_of_PWM_channels;
+ uint8_t number_of_QE_channels;
+ uint8_t number_of_RC_channels;
+ uint32_t PWM_period_value[NOS_PWM_CHANNELS];
+ uint32_t PWM_duty_value[NOS_PWM_CHANNELS];
+ } sys_data;
private:
+//
+// data
+//
uint32_t _nos_PWM_units;
uint32_t _nos_QE_units;
uint32_t _nos_servo_units;
@@ -189,16 +213,23 @@
uint32_t data, status, tmp_config;
received_packet_t in_pkt;
-
- void do_start(void);
- void do_end(void);
- void write_byte(uint32_t byte_value);
+//
+// functions
+//
+ void do_start(void);
+ void do_end(void);
+ void write_byte(uint32_t byte_value);
uint32_t read_byte(void);
- void do_write( uint32_t command,
- uint32_t register_address,
- uint32_t register_data);
- void do_read(received_packet_t *buffer);
-
+ void do_write( uint32_t command,
+ uint32_t register_address,
+ uint32_t register_data);
+ void do_read(received_packet_t *buffer);
+ void do_reset(void);
+ int32_t check_bus(void);
+ void update_FPGA_register_pointers(void);
+//
+// Hardware digital I/O lines
+//
DigitalOut async_uP_start;
DigitalOut async_uP_handshake_1;
DigitalOut async_uP_RW;
@@ -208,15 +239,6 @@
DigitalOut log_pin;
- struct SYS_data {
- uint8_t major_version;
- uint8_t minor_version;
- uint8_t number_of_PWM_channels;
- uint8_t number_of_QE_channels;
- uint8_t number_of_RC_channels;
- uint32_t PWM_period_value[NOS_PWM_CHANNELS];
- uint32_t PWM_duty_value[NOS_PWM_CHANNELS];
- } sys_data;
};
#endif