jim herd / FPGA_bus

Comms between MAX 10 FPGA and ST uP

FPGA_bus.h@18:62462a30d513, 2020-05-24 (annotated)

Committer:
jimherd
Date:
Sun May 24 22:53:59 2020 +0000
Revision:
18:62462a30d513
Parent:
17:928b755cba80
Child:
19:bc9910b1c186
Updated H-bridge bit enum definitions

Who changed what in which revision?

UserRevisionLine numberNew contents of line
jimherd 0:9600ed6fd725 1 /*
jimherd 0:9600ed6fd725 2 * FPGA_bus : 8-bit bi-directional bus between uP and FPGA
jimherd 0:9600ed6fd725 3 *
jimherd 0:9600ed6fd725 4 * Author : Jim Herd
jimherd 0:9600ed6fd725 5 *
jimherd 0:9600ed6fd725 6 * Version 0.1 : initial release
jimherd 0:9600ed6fd725 7 */
jimherd 0:9600ed6fd725 8 #include "mbed.h"
jimherd 17:928b755cba80 9
jimherd 17:928b755cba80 10 extern Serial pc;
jimherd 0:9600ed6fd725 11
jimherd 0:9600ed6fd725 12 #ifndef FPGA_bus_H
jimherd 0:9600ed6fd725 13 #define FPGA_bus_H
jimherd 0:9600ed6fd725 14
jimherd 0:9600ed6fd725 15 //
jimherd 0:9600ed6fd725 16 // Pin definitions
jimherd 0:9600ed6fd725 17
jimherd 0:9600ed6fd725 18 #define ASYNC_UP_RW_PIN PB_0
jimherd 0:9600ed6fd725 19 #define ASYNC_UP_HANDSHAKE_1_PIN PB_1
jimherd 0:9600ed6fd725 20 #define ASYNC_UP_HANDSHAKE_2_PIN PB_2
jimherd 0:9600ed6fd725 21 #define ASYNC_UP_START_PIN PB_3
jimherd 0:9600ed6fd725 22 #define ASYNC_UP_ACK_PIN PB_4
jimherd 0:9600ed6fd725 23 #define ASYNC_UP_RESET_PIN PB_5
jimherd 0:9600ed6fd725 24
jimherd 9:6fe95fb0c7ea 25 #define LOG_PIN PB_8
jimherd 9:6fe95fb0c7ea 26
jimherd 0:9600ed6fd725 27 //
jimherd 16:d69a36a541c5 28 //#define PWM_BASE 1
jimherd 0:9600ed6fd725 29 #define NOS_PWM_REGISTERS 4
jimherd 14:b56473e54f6f 30 #define NOS_PWM_CHANNELS 1
jimherd 0:9600ed6fd725 31
jimherd 16:d69a36a541c5 32 //#define QE_BASE ((NOS_PWM_REGISTERS * NOS_PWM_CHANNELS) + PWM_BASE)
jimherd 0:9600ed6fd725 33 #define NOS_QE_REGISTERS 7
jimherd 14:b56473e54f6f 34 #define NOS_QE_CHANNELS 1
jimherd 0:9600ed6fd725 35
jimherd 16:d69a36a541c5 36 //#define RC_BASE ((NOS_QE_REGISTERS * NOS_QE_CHANNELS) + QE_BASE)
jimherd 0:9600ed6fd725 37 #define NOS_RC_CHANNELS 8
jimherd 2:fd5c862b86db 38 #define GLOBAL_RC_ENABLE 0x80000000
jimherd 0:9600ed6fd725 39
jimherd 16:d69a36a541c5 40 #define PWM_ch0 (PWM_base + (0 * NOS_PWM_REGISTERS))
jimherd 16:d69a36a541c5 41 #define PWM_ch1 (PWM_base + (1 * NOS_PWM_REGISTERS))
jimherd 16:d69a36a541c5 42 #define PWM_ch3 (PWM_base + (3 * NOS_PWM_REGISTERS))
jimherd 0:9600ed6fd725 43
jimherd 0:9600ed6fd725 44 #define RC_0 RC_BASE
jimherd 0:9600ed6fd725 45
jimherd 9:6fe95fb0c7ea 46 //
jimherd 9:6fe95fb0c7ea 47 // System can be configured to return ONE or TWO 32-bit values from the FPGA.
jimherd 9:6fe95fb0c7ea 48 //
jimherd 9:6fe95fb0c7ea 49 // first value : 32-bit data value
jimherd 9:6fe95fb0c7ea 50 // second value : 32-bit status value
jimherd 9:6fe95fb0c7ea 51 //
jimherd 9:6fe95fb0c7ea 52 // In practice, the status word carries little or no information but consumes
jimherd 9:6fe95fb0c7ea 53 // four 8-bit transactions between the FPGA and the uP.
jimherd 9:6fe95fb0c7ea 54 //
jimherd 9:6fe95fb0c7ea 55 // Uncomment following #define to enable status word to be returned.
jimherd 9:6fe95fb0c7ea 56
jimherd 9:6fe95fb0c7ea 57 //#define INCLUDE_32_BIT_STATUS_RETURN
jimherd 9:6fe95fb0c7ea 58
jimherd 9:6fe95fb0c7ea 59 #ifdef INCLUDE_32_BIT_STATUS_RETURN
jimherd 9:6fe95fb0c7ea 60 #define NOS_RECEIVED_PACKET_WORDS 2
jimherd 9:6fe95fb0c7ea 61 #else
jimherd 9:6fe95fb0c7ea 62 #define NOS_RECEIVED_PACKET_WORDS 1
jimherd 9:6fe95fb0c7ea 63 #endif
jimherd 0:9600ed6fd725 64
jimherd 0:9600ed6fd725 65 #define SET_BUS_INPUT (GPIOC->MODER = (GPIOC->MODER & 0xFFFF0000))
jimherd 0:9600ed6fd725 66 #define SET_BUS_OUTPUT (GPIOC->MODER = ((GPIOC->MODER & 0xFFFF0000) | 0x00005555))
jimherd 0:9600ed6fd725 67 #define OUTPUT_BYTE_TO_BUS(value) (GPIOC->ODR = ((GPIOC->ODR & 0x0000FF00) | (value & 0x000000FF)))
jimherd 0:9600ed6fd725 68 #define INPUT_BYTE_FROM_BUS (GPIOC->IDR & 0x000000FF)
jimherd 0:9600ed6fd725 69 #define ENABLE_GPIO_SUBSYSTEM (RCC->AHBENR |= RCC_AHBENR_GPIOCEN)
jimherd 0:9600ed6fd725 70
jimherd 1:b819a72b3b5d 71 //
jimherd 1:b819a72b3b5d 72 // FPGA constants
jimherd 1:b819a72b3b5d 73
jimherd 1:b819a72b3b5d 74 #define nS_IN_uS 1000
jimherd 1:b819a72b3b5d 75 #define FPGA_CLOCK_PERIOD_nS 20
jimherd 1:b819a72b3b5d 76
jimherd 1:b819a72b3b5d 77 //
jimherd 1:b819a72b3b5d 78 // error codes
jimherd 1:b819a72b3b5d 79
jimherd 1:b819a72b3b5d 80 #define NO_ERROR 0
jimherd 1:b819a72b3b5d 81
jimherd 0:9600ed6fd725 82 #define LOOP_HERE for(;;)
jimherd 0:9600ed6fd725 83
jimherd 0:9600ed6fd725 84 typedef struct {
jimherd 0:9600ed6fd725 85 uint8_t command;
jimherd 0:9600ed6fd725 86 uint8_t register_no;
jimherd 0:9600ed6fd725 87 uint32_t cmd_data;
jimherd 0:9600ed6fd725 88 uint32_t reply_data;
jimherd 0:9600ed6fd725 89 uint32_t reply_status;
jimherd 0:9600ed6fd725 90 } FPGA_packet_t;
jimherd 0:9600ed6fd725 91
jimherd 0:9600ed6fd725 92 typedef union {
jimherd 9:6fe95fb0c7ea 93 uint32_t word_data[2]; // NOS_RECEIVED_PACKET_WORDS];
jimherd 9:6fe95fb0c7ea 94 uint8_t byte_data[8]; // NOS_RECEIVED_PACKET_WORDS << 2];
jimherd 0:9600ed6fd725 95 } received_packet_t;
jimherd 0:9600ed6fd725 96
jimherd 0:9600ed6fd725 97 enum {READ_REGISTER_CMD=0, WRITE_REGISTER_CMD=1};
jimherd 0:9600ed6fd725 98 enum {READ_BUS=0, WRITE_BUS=1};
jimherd 0:9600ed6fd725 99 enum {LOW=0, HIGH=1};
jimherd 4:e5d36eee9245 100
jimherd 6:e68defb7b775 101 //
jimherd 6:e68defb7b775 102 // SYS_data registers
jimherd 6:e68defb7b775 103
jimherd 6:e68defb7b775 104 enum {SYS_DATA_REG_ADDR=0};
jimherd 6:e68defb7b775 105
jimherd 4:e5d36eee9245 106 // PWM registers
jimherd 4:e5d36eee9245 107 //
jimherd 0:9600ed6fd725 108 enum {PWM_PERIOD=0, PWM_ON_TIME=1, PWM_CONFIG=2, PWM_STATUS=3};
jimherd 0:9600ed6fd725 109
jimherd 4:e5d36eee9245 110 // QE registers
jimherd 4:e5d36eee9245 111 //
jimherd 4:e5d36eee9245 112 enum {QE_COUNT_BUFFER=0, QE_TURN_BUFFER=1, QE_SPEED_BUFFER=2, QE_SIM_PHASE_TIME=3,
jimherd 4:e5d36eee9245 113 QE_COUNTS_PER_REV=4, QE_CONFIG=5, QE_STATUS=6};
jimherd 8:65d1b1a7bfcc 114 //
jimherd 8:65d1b1a7bfcc 115 // constants to define bits in QE config register
jimherd 4:e5d36eee9245 116
jimherd 9:6fe95fb0c7ea 117 #define QE_CONFIG_DEFAULT 0x00
jimherd 8:65d1b1a7bfcc 118 enum {QE_SIG_EXT=0x00, QE_SIG_INT_SIM=0x02};
jimherd 8:65d1b1a7bfcc 119 enum {QE_INT_SIM_DISABLE=0x0, QE_INT_SIM_ENABLE=0x04};
jimherd 8:65d1b1a7bfcc 120 enum {QE_SIM_DIR_FORWARD=0x0, QE_SIM_DIR_BACKWARD=0x08};
jimherd 8:65d1b1a7bfcc 121 enum {QE_NO_SWAP_AB=0x00, QE_SWAP_AB=0x10};
jimherd 8:65d1b1a7bfcc 122 enum {QE_SPEED_CALC_DISABLE=0x00, QE_SPEED_CALC_ENABLE=0x10000};
jimherd 8:65d1b1a7bfcc 123 enum {QE_SPEED_CALC_FILTER_DISABLE=0x00, QE_SPEED_CALC_FILTER_ENABLE=0x20000};
jimherd 10:56a045a02047 124 enum {QE_FILTER_SAMPLE_2=0x00, QE_FILTER_SAMPLE_4=0x100000, QE_FILTER_SAMPLE_8=0x200000,
jimherd 10:56a045a02047 125 QE_FILTER_SAMPLE_16=0x300000, QE_FILTER_SAMPLE_32=0x400000};
jimherd 8:65d1b1a7bfcc 126
jimherd 4:e5d36eee9245 127 // RC servo registers
jimherd 4:e5d36eee9245 128 //
jimherd 0:9600ed6fd725 129 enum {RC_SERVO_PERIOD=0, RC_SERVO_CONFIG=1, RC_SERVO_STATUS=2, RC_SERVO_ON_TIME=3};
jimherd 0:9600ed6fd725 130
jimherd 9:6fe95fb0c7ea 131 //
jimherd 9:6fe95fb0c7ea 132 // constants to define bits in PWM config register
jimherd 9:6fe95fb0c7ea 133
jimherd 9:6fe95fb0c7ea 134 #define PWM_CONFIG_DEFAULT 0x00
jimherd 0:9600ed6fd725 135 enum {PWM_OFF=0x0, PWM_ON=0x1};
jimherd 0:9600ed6fd725 136 enum {INT_H_BRIDGE_OFF=0x0, INT_H_BRIDGE_ON=0x10000};
jimherd 0:9600ed6fd725 137 enum {EXT_H_BRIDGE_OFF=0x0, EXT_H_BRIDGE_ON=0x20000};
jimherd 18:62462a30d513 138 enum {MODE_PWM_CONTROL=0x0, MODE_DIR_CONTROL=0x40000};
jimherd 18:62462a30d513 139 enum {MOTOR_COAST=0x0, MOTOR_FORWARD=0x100000, MOTOR_BACKWARD=0x300000, MOTOR_BRAKE=0xC00000};
jimherd 18:62462a30d513 140 enum {NO_SWAP=0x0, YES_SWAP=0x1000000};
jimherd 18:62462a30d513 141 enum {PWM_BRAKE_DWELL=0x0, PWM_COAST_DWELL=0x2000000};
jimherd 18:62462a30d513 142 enum {NO_INVERT = 0x0, H_BRIDGE_1_INVERT=0x4000000, H_BRIDGE_2_INVERT=0x8000000, ALL_INVERT=0xC000000};
jimherd 0:9600ed6fd725 143 enum {BACKWARD, FORWARD};
jimherd 0:9600ed6fd725 144
jimherd 0:9600ed6fd725 145 //DigitalOut async_uP_start(ASYNC_UP_START_PIN, LOW);
jimherd 0:9600ed6fd725 146 //DigitalOut async_uP_handshake_1(ASYNC_UP_HANDSHAKE_1_PIN, LOW);
jimherd 0:9600ed6fd725 147 //DigitalOut async_uP_RW(ASYNC_UP_RW_PIN, LOW);
jimherd 0:9600ed6fd725 148 //DigitalOut async_uP_reset(ASYNC_UP_RESET_PIN, HIGH);
jimherd 0:9600ed6fd725 149 //DigitalIn uP_ack(ASYNC_UP_ACK_PIN, PullDown);
jimherd 0:9600ed6fd725 150 //DigitalIn uP_handshake_2(ASYNC_UP_HANDSHAKE_2_PIN);
jimherd 0:9600ed6fd725 151
jimherd 0:9600ed6fd725 152 class FPGA_bus {
jimherd 0:9600ed6fd725 153 public:
jimherd 7:c0bef9c1f5d5 154 FPGA_bus(int nos_PWM = NOS_PWM_CHANNELS ,
jimherd 7:c0bef9c1f5d5 155 int nos_QE = NOS_QE_CHANNELS ,
jimherd 14:b56473e54f6f 156 int nos_servo = NOS_RC_CHANNELS ); // constructor
jimherd 7:c0bef9c1f5d5 157
jimherd 14:b56473e54f6f 158 void initialise(void);
jimherd 11:16b526669574 159 void do_transaction(uint32_t command,
jimherd 11:16b526669574 160 uint32_t register_address,
jimherd 11:16b526669574 161 uint32_t register_data,
jimherd 11:16b526669574 162 uint32_t *data,
jimherd 11:16b526669574 163 uint32_t *status);
jimherd 0:9600ed6fd725 164 uint32_t do_command(FPGA_packet_t cmd_packet);
jimherd 9:6fe95fb0c7ea 165 void write_register(uint32_t register_addr, uint32_t value);
jimherd 1:b819a72b3b5d 166 void set_PWM_period(uint32_t channel, float frequency);
jimherd 1:b819a72b3b5d 167 void set_PWM_duty(uint32_t channel, float percentage);
jimherd 1:b819a72b3b5d 168 void PWM_enable(uint32_t channel);
jimherd 1:b819a72b3b5d 169 void PWM_config(uint32_t channel, uint32_t config_value);
jimherd 4:e5d36eee9245 170 void set_RC_period(void);
jimherd 4:e5d36eee9245 171 void set_RC_period(uint32_t duty_uS);
jimherd 1:b819a72b3b5d 172 void set_RC_pulse(uint32_t channel, uint32_t pulse_uS);
jimherd 1:b819a72b3b5d 173 void enable_RC_channel(uint32_t channel);
jimherd 2:fd5c862b86db 174 void disable_RC_channel(uint32_t channel);
jimherd 9:6fe95fb0c7ea 175 void QE_config(uint32_t channel, uint32_t config_value);
jimherd 9:6fe95fb0c7ea 176 void enable_speed_measure(uint32_t channel, uint32_t config_value, uint32_t phase_time);
jimherd 5:64c677e9995c 177 uint32_t read_speed_measure(uint32_t channel);
jimherd 10:56a045a02047 178 uint32_t read_count_measure(uint32_t channel);
jimherd 15:6420b52d30cc 179 void update_FPGA_register_pointers(void);
jimherd 1:b819a72b3b5d 180
jimherd 6:e68defb7b775 181 uint32_t get_SYS_data(void);
jimherd 6:e68defb7b775 182
jimherd 1:b819a72b3b5d 183 int32_t global_FPGA_unit_error_flag;
jimherd 0:9600ed6fd725 184
jimherd 15:6420b52d30cc 185 private:
jimherd 0:9600ed6fd725 186 uint32_t _nos_PWM_units;
jimherd 0:9600ed6fd725 187 uint32_t _nos_QE_units;
jimherd 0:9600ed6fd725 188 uint32_t _nos_servo_units;
jimherd 0:9600ed6fd725 189
jimherd 15:6420b52d30cc 190 uint32_t PWM_base, QE_base, RC_base;
jimherd 15:6420b52d30cc 191
jimherd 0:9600ed6fd725 192 uint32_t data, status, tmp_config;
jimherd 0:9600ed6fd725 193 received_packet_t in_pkt;
jimherd 0:9600ed6fd725 194
jimherd 0:9600ed6fd725 195 void do_start(void);
jimherd 0:9600ed6fd725 196 void do_end(void);
jimherd 0:9600ed6fd725 197 void write_byte(uint32_t byte_value);
jimherd 0:9600ed6fd725 198 uint32_t read_byte(void);
jimherd 0:9600ed6fd725 199 void do_write( uint32_t command,
jimherd 0:9600ed6fd725 200 uint32_t register_address,
jimherd 0:9600ed6fd725 201 uint32_t register_data);
jimherd 0:9600ed6fd725 202 void do_read(received_packet_t *buffer);
jimherd 0:9600ed6fd725 203
jimherd 0:9600ed6fd725 204 DigitalOut async_uP_start;
jimherd 0:9600ed6fd725 205 DigitalOut async_uP_handshake_1;
jimherd 0:9600ed6fd725 206 DigitalOut async_uP_RW;
jimherd 0:9600ed6fd725 207 DigitalOut async_uP_reset;
jimherd 0:9600ed6fd725 208 DigitalIn uP_ack;
jimherd 0:9600ed6fd725 209 DigitalIn uP_handshake_2;
jimherd 0:9600ed6fd725 210
jimherd 9:6fe95fb0c7ea 211 DigitalOut log_pin;
jimherd 9:6fe95fb0c7ea 212
jimherd 0:9600ed6fd725 213 struct SYS_data {
jimherd 6:e68defb7b775 214 uint8_t major_version;
jimherd 6:e68defb7b775 215 uint8_t minor_version;
jimherd 6:e68defb7b775 216 uint8_t number_of_PWM_channels;
jimherd 6:e68defb7b775 217 uint8_t number_of_QE_channels;
jimherd 6:e68defb7b775 218 uint8_t number_of_RC_channels;
jimherd 17:928b755cba80 219 uint32_t PWM_period_value[NOS_PWM_CHANNELS];
jimherd 17:928b755cba80 220 uint32_t PWM_duty_value[NOS_PWM_CHANNELS];
jimherd 0:9600ed6fd725 221 } sys_data;
jimherd 0:9600ed6fd725 222 };
jimherd 0:9600ed6fd725 223
jimherd 0:9600ed6fd725 224 #endif
jimherd 0:9600ed6fd725 225