jim herd / FPGA_bus

Comms between MAX 10 FPGA and ST uP

FPGA_bus.h@8:65d1b1a7bfcc, 2019-05-12 (annotated)

Committer:
jimherd
Date:
Sun May 12 21:10:50 2019 +0000
Revision:
8:65d1b1a7bfcc
Parent:
6:e68defb7b775
Child:
9:6fe95fb0c7ea
Named bits in QE configuration register

Who changed what in which revision?

UserRevisionLine numberNew contents of line
jimherd 0:9600ed6fd725 1 /*
jimherd 0:9600ed6fd725 2 * FPGA_bus : 8-bit bi-directional bus between uP and FPGA
jimherd 0:9600ed6fd725 3 *
jimherd 0:9600ed6fd725 4 * Author : Jim Herd
jimherd 0:9600ed6fd725 5 *
jimherd 0:9600ed6fd725 6 * Version 0.1 : initial release
jimherd 0:9600ed6fd725 7 */
jimherd 0:9600ed6fd725 8 #include "mbed.h"
jimherd 0:9600ed6fd725 9
jimherd 0:9600ed6fd725 10 #ifndef FPGA_bus_H
jimherd 0:9600ed6fd725 11 #define FPGA_bus_H
jimherd 0:9600ed6fd725 12
jimherd 0:9600ed6fd725 13 //
jimherd 0:9600ed6fd725 14 // Pin definitions
jimherd 0:9600ed6fd725 15
jimherd 0:9600ed6fd725 16 #define ASYNC_UP_RW_PIN PB_0
jimherd 0:9600ed6fd725 17 #define ASYNC_UP_HANDSHAKE_1_PIN PB_1
jimherd 0:9600ed6fd725 18 #define ASYNC_UP_HANDSHAKE_2_PIN PB_2
jimherd 0:9600ed6fd725 19 #define ASYNC_UP_START_PIN PB_3
jimherd 0:9600ed6fd725 20 #define ASYNC_UP_ACK_PIN PB_4
jimherd 0:9600ed6fd725 21 #define ASYNC_UP_RESET_PIN PB_5
jimherd 0:9600ed6fd725 22
jimherd 0:9600ed6fd725 23 //
jimherd 0:9600ed6fd725 24 //
jimherd 0:9600ed6fd725 25 #define PWM_BASE 1
jimherd 0:9600ed6fd725 26 #define NOS_PWM_REGISTERS 4
jimherd 0:9600ed6fd725 27 #define NOS_PWM_CHANNELS 4
jimherd 0:9600ed6fd725 28
jimherd 0:9600ed6fd725 29 #define QE_BASE ((NOS_PWM_REGISTERS * NOS_PWM_CHANNELS) + PWM_BASE)
jimherd 0:9600ed6fd725 30 #define NOS_QE_REGISTERS 7
jimherd 0:9600ed6fd725 31 #define NOS_QE_CHANNELS 4
jimherd 0:9600ed6fd725 32
jimherd 0:9600ed6fd725 33 #define RC_BASE ((NOS_QE_REGISTERS * NOS_QE_CHANNELS) + QE_BASE)
jimherd 0:9600ed6fd725 34 #define NOS_RC_CHANNELS 8
jimherd 2:fd5c862b86db 35 #define GLOBAL_RC_ENABLE 0x80000000
jimherd 0:9600ed6fd725 36
jimherd 0:9600ed6fd725 37 #define PWM_ch0 (PWM_BASE + (0 * NOS_PWM_REGISTERS))
jimherd 0:9600ed6fd725 38 #define PWM_ch1 (PWM_BASE + (1 * NOS_PWM_REGISTERS))
jimherd 0:9600ed6fd725 39 #define PWM_ch3 (PWM_BASE + (3 * NOS_PWM_REGISTERS))
jimherd 0:9600ed6fd725 40
jimherd 0:9600ed6fd725 41 #define RC_0 RC_BASE
jimherd 0:9600ed6fd725 42
jimherd 0:9600ed6fd725 43 #define NOS_RECEIVED_PACKET_WORDS 2
jimherd 0:9600ed6fd725 44
jimherd 0:9600ed6fd725 45 #define SET_BUS_INPUT (GPIOC->MODER = (GPIOC->MODER & 0xFFFF0000))
jimherd 0:9600ed6fd725 46 #define SET_BUS_OUTPUT (GPIOC->MODER = ((GPIOC->MODER & 0xFFFF0000) | 0x00005555))
jimherd 0:9600ed6fd725 47 #define OUTPUT_BYTE_TO_BUS(value) (GPIOC->ODR = ((GPIOC->ODR & 0x0000FF00) | (value & 0x000000FF)))
jimherd 0:9600ed6fd725 48 #define INPUT_BYTE_FROM_BUS (GPIOC->IDR & 0x000000FF)
jimherd 0:9600ed6fd725 49 #define ENABLE_GPIO_SUBSYSTEM (RCC->AHBENR |= RCC_AHBENR_GPIOCEN)
jimherd 0:9600ed6fd725 50
jimherd 1:b819a72b3b5d 51 //
jimherd 1:b819a72b3b5d 52 // FPGA constants
jimherd 1:b819a72b3b5d 53
jimherd 1:b819a72b3b5d 54 #define nS_IN_uS 1000
jimherd 1:b819a72b3b5d 55 #define FPGA_CLOCK_PERIOD_nS 20
jimherd 1:b819a72b3b5d 56
jimherd 1:b819a72b3b5d 57 //
jimherd 1:b819a72b3b5d 58 // error codes
jimherd 1:b819a72b3b5d 59
jimherd 1:b819a72b3b5d 60 #define NO_ERROR 0
jimherd 1:b819a72b3b5d 61
jimherd 0:9600ed6fd725 62 #define LOOP_HERE for(;;)
jimherd 0:9600ed6fd725 63
jimherd 0:9600ed6fd725 64 typedef struct {
jimherd 0:9600ed6fd725 65 uint8_t command;
jimherd 0:9600ed6fd725 66 uint8_t register_no;
jimherd 0:9600ed6fd725 67 uint32_t cmd_data;
jimherd 0:9600ed6fd725 68 uint32_t reply_data;
jimherd 0:9600ed6fd725 69 uint32_t reply_status;
jimherd 0:9600ed6fd725 70 } FPGA_packet_t;
jimherd 0:9600ed6fd725 71
jimherd 0:9600ed6fd725 72 typedef union {
jimherd 0:9600ed6fd725 73 uint32_t word_data[NOS_RECEIVED_PACKET_WORDS];
jimherd 0:9600ed6fd725 74 uint8_t byte_data[NOS_RECEIVED_PACKET_WORDS << 2];
jimherd 0:9600ed6fd725 75 } received_packet_t;
jimherd 0:9600ed6fd725 76
jimherd 0:9600ed6fd725 77 enum {READ_REGISTER_CMD=0, WRITE_REGISTER_CMD=1};
jimherd 0:9600ed6fd725 78 enum {READ_BUS=0, WRITE_BUS=1};
jimherd 0:9600ed6fd725 79 enum {LOW=0, HIGH=1};
jimherd 4:e5d36eee9245 80
jimherd 6:e68defb7b775 81 //
jimherd 6:e68defb7b775 82 // SYS_data registers
jimherd 6:e68defb7b775 83
jimherd 6:e68defb7b775 84 enum {SYS_DATA_REG_ADDR=0};
jimherd 6:e68defb7b775 85
jimherd 4:e5d36eee9245 86 // PWM registers
jimherd 4:e5d36eee9245 87 //
jimherd 0:9600ed6fd725 88 enum {PWM_PERIOD=0, PWM_ON_TIME=1, PWM_CONFIG=2, PWM_STATUS=3};
jimherd 0:9600ed6fd725 89
jimherd 4:e5d36eee9245 90 // QE registers
jimherd 4:e5d36eee9245 91 //
jimherd 4:e5d36eee9245 92 enum {QE_COUNT_BUFFER=0, QE_TURN_BUFFER=1, QE_SPEED_BUFFER=2, QE_SIM_PHASE_TIME=3,
jimherd 4:e5d36eee9245 93 QE_COUNTS_PER_REV=4, QE_CONFIG=5, QE_STATUS=6};
jimherd 8:65d1b1a7bfcc 94 //
jimherd 8:65d1b1a7bfcc 95 // constants to define bits in QE config register
jimherd 4:e5d36eee9245 96
jimherd 8:65d1b1a7bfcc 97 enum {QE_SIG_EXT=0x00, QE_SIG_INT_SIM=0x02};
jimherd 8:65d1b1a7bfcc 98 enum {QE_INT_SIM_DISABLE=0x0, QE_INT_SIM_ENABLE=0x04};
jimherd 8:65d1b1a7bfcc 99 enum {QE_SIM_DIR_FORWARD=0x0, QE_SIM_DIR_BACKWARD=0x08};
jimherd 8:65d1b1a7bfcc 100 enum {QE_NO_SWAP_AB=0x00, QE_SWAP_AB=0x10};
jimherd 8:65d1b1a7bfcc 101 enum {QE_SPEED_CALC_DISABLE=0x00, QE_SPEED_CALC_ENABLE=0x10000};
jimherd 8:65d1b1a7bfcc 102 enum {QE_SPEED_CALC_FILTER_DISABLE=0x00, QE_SPEED_CALC_FILTER_ENABLE=0x20000};
jimherd 8:65d1b1a7bfcc 103 enum {QE_FILTER_SAMPLE_2=0x00, QE_FILTER_SAMPLE_4=0x40000, QE_FILTER_SAMPLE_8=0x80000,
jimherd 8:65d1b1a7bfcc 104 QE_FILTER_SAMPLE_16=0xC0000, QE_FILTER_SAMPLE_32=0x100000};
jimherd 8:65d1b1a7bfcc 105
jimherd 4:e5d36eee9245 106 // RC servo registers
jimherd 4:e5d36eee9245 107 //
jimherd 0:9600ed6fd725 108 enum {RC_SERVO_PERIOD=0, RC_SERVO_CONFIG=1, RC_SERVO_STATUS=2, RC_SERVO_ON_TIME=3};
jimherd 0:9600ed6fd725 109
jimherd 0:9600ed6fd725 110 enum {PWM_OFF=0x0, PWM_ON=0x1};
jimherd 0:9600ed6fd725 111 enum {INT_H_BRIDGE_OFF=0x0, INT_H_BRIDGE_ON=0x10000};
jimherd 0:9600ed6fd725 112 enum {EXT_H_BRIDGE_OFF=0x0, EXT_H_BRIDGE_ON=0x20000};
jimherd 0:9600ed6fd725 113 enum {MOTOR_COAST=0x0, MOTOR_FORWARD=0x40000, MOTOR_BACKWARD=0x80000, MOTOR_BRAKE=0xC0000};
jimherd 0:9600ed6fd725 114 enum {MODE_PWM_CONTROL=0x0, MODE_DIR_CONTROL=0x200000};
jimherd 0:9600ed6fd725 115 enum {NO_SWAP=0x0, YES_SWAP=0x800000};
jimherd 0:9600ed6fd725 116 enum {PWM_BRAKE_DWELL=0x0, PWM_COAST_DWELL=0x1000000};
jimherd 0:9600ed6fd725 117 enum {NO_INVERT = 0x0, H_BRIDGE_1_INVERT=0x2000000, H_BRIDGE_2_INVERT=0x4000000, ALL_INVERT=0x6000000};
jimherd 0:9600ed6fd725 118 enum {BACKWARD, FORWARD};
jimherd 0:9600ed6fd725 119
jimherd 0:9600ed6fd725 120 //DigitalOut async_uP_start(ASYNC_UP_START_PIN, LOW);
jimherd 0:9600ed6fd725 121 //DigitalOut async_uP_handshake_1(ASYNC_UP_HANDSHAKE_1_PIN, LOW);
jimherd 0:9600ed6fd725 122 //DigitalOut async_uP_RW(ASYNC_UP_RW_PIN, LOW);
jimherd 0:9600ed6fd725 123 //DigitalOut async_uP_reset(ASYNC_UP_RESET_PIN, HIGH);
jimherd 0:9600ed6fd725 124 //DigitalIn uP_ack(ASYNC_UP_ACK_PIN, PullDown);
jimherd 0:9600ed6fd725 125 //DigitalIn uP_handshake_2(ASYNC_UP_HANDSHAKE_2_PIN);
jimherd 0:9600ed6fd725 126
jimherd 0:9600ed6fd725 127 class FPGA_bus {
jimherd 0:9600ed6fd725 128 public:
jimherd 0:9600ed6fd725 129 FPGA_bus(int nos_PWM, int nos_QE, int nos_servo); // constructor
jimherd 0:9600ed6fd725 130 FPGA_bus(); // constructor
jimherd 0:9600ed6fd725 131
jimherd 0:9600ed6fd725 132 void initialise(void);
jimherd 0:9600ed6fd725 133 uint32_t do_command(FPGA_packet_t cmd_packet);
jimherd 1:b819a72b3b5d 134 void set_PWM_period(uint32_t channel, float frequency);
jimherd 1:b819a72b3b5d 135 void set_PWM_duty(uint32_t channel, float percentage);
jimherd 1:b819a72b3b5d 136 void PWM_enable(uint32_t channel);
jimherd 1:b819a72b3b5d 137 void PWM_config(uint32_t channel, uint32_t config_value);
jimherd 4:e5d36eee9245 138 void set_RC_period(void);
jimherd 4:e5d36eee9245 139 void set_RC_period(uint32_t duty_uS);
jimherd 1:b819a72b3b5d 140 void set_RC_pulse(uint32_t channel, uint32_t pulse_uS);
jimherd 1:b819a72b3b5d 141 void enable_RC_channel(uint32_t channel);
jimherd 2:fd5c862b86db 142 void disable_RC_channel(uint32_t channel);
jimherd 4:e5d36eee9245 143 void enable_speed_measure(uint32_t channel);
jimherd 5:64c677e9995c 144 uint32_t read_speed_measure(uint32_t channel);
jimherd 1:b819a72b3b5d 145
jimherd 6:e68defb7b775 146 uint32_t get_SYS_data(void);
jimherd 6:e68defb7b775 147
jimherd 1:b819a72b3b5d 148 int32_t global_FPGA_unit_error_flag;
jimherd 0:9600ed6fd725 149
jimherd 0:9600ed6fd725 150 protected:
jimherd 0:9600ed6fd725 151 uint32_t _nos_PWM_units;
jimherd 0:9600ed6fd725 152 uint32_t _nos_QE_units;
jimherd 0:9600ed6fd725 153 uint32_t _nos_servo_units;
jimherd 0:9600ed6fd725 154
jimherd 0:9600ed6fd725 155 private:
jimherd 0:9600ed6fd725 156 uint32_t data, status, tmp_config;
jimherd 0:9600ed6fd725 157 received_packet_t in_pkt;
jimherd 0:9600ed6fd725 158
jimherd 0:9600ed6fd725 159 void do_start(void);
jimherd 0:9600ed6fd725 160 void do_end(void);
jimherd 0:9600ed6fd725 161 void write_byte(uint32_t byte_value);
jimherd 0:9600ed6fd725 162 uint32_t read_byte(void);
jimherd 0:9600ed6fd725 163 void do_write( uint32_t command,
jimherd 0:9600ed6fd725 164 uint32_t register_address,
jimherd 0:9600ed6fd725 165 uint32_t register_data);
jimherd 0:9600ed6fd725 166 void do_read(received_packet_t *buffer);
jimherd 0:9600ed6fd725 167 void do_transaction(uint32_t command,
jimherd 0:9600ed6fd725 168 uint32_t register_address,
jimherd 0:9600ed6fd725 169 uint32_t register_data,
jimherd 0:9600ed6fd725 170 uint32_t *data,
jimherd 0:9600ed6fd725 171 uint32_t *status);
jimherd 0:9600ed6fd725 172
jimherd 0:9600ed6fd725 173 DigitalOut async_uP_start;
jimherd 0:9600ed6fd725 174 DigitalOut async_uP_handshake_1;
jimherd 0:9600ed6fd725 175 DigitalOut async_uP_RW;
jimherd 0:9600ed6fd725 176 DigitalOut async_uP_reset;
jimherd 0:9600ed6fd725 177 DigitalIn uP_ack;
jimherd 0:9600ed6fd725 178 DigitalIn uP_handshake_2;
jimherd 0:9600ed6fd725 179
jimherd 0:9600ed6fd725 180 struct SYS_data {
jimherd 6:e68defb7b775 181 uint8_t major_version;
jimherd 6:e68defb7b775 182 uint8_t minor_version;
jimherd 6:e68defb7b775 183 uint8_t number_of_PWM_channels;
jimherd 6:e68defb7b775 184 uint8_t number_of_QE_channels;
jimherd 6:e68defb7b775 185 uint8_t number_of_RC_channels;
jimherd 6:e68defb7b775 186 uint8_t PWM_period_value[NOS_PWM_CHANNELS];
jimherd 6:e68defb7b775 187 uint8_t PWM_duty_value[NOS_PWM_CHANNELS];
jimherd 6:e68defb7b775 188 uint8_t pad1;
jimherd 0:9600ed6fd725 189 } sys_data;
jimherd 0:9600ed6fd725 190 };
jimherd 0:9600ed6fd725 191
jimherd 0:9600ed6fd725 192 #endif
jimherd 0:9600ed6fd725 193