Clark Scheff / A7105TxRx

Library for interfacing with the AMICCOM A7105 2.4GHz FSK/GFSK Transceiver.

Dependents:   HubsanTX

A7105.h@8:033e328fb7c3, 2015-01-01 (annotated)

Committer:
d34d
Date:
Thu Jan 01 22:24:40 2015 +0000
Revision:
8:033e328fb7c3
Parent:
7:1b1d7e446aa4 
Fix A7105::writeData method

Who changed what in which revision?

UserRevisionLine numberNew contents of line
d34d 0:212eb977fe10 1 #ifndef _A7105_TX_RX_H
d34d 0:212eb977fe10 2 #define _A7105_TX_RX_H
d34d 0:212eb977fe10 3
d34d 3:cd7f899f155f 4 #define _WRITE(a) ((a) & ~0x40)
d34d 3:cd7f899f155f 5 #define _READ(a) ((a) | 0x40)
d34d 3:cd7f899f155f 6
d34d 4:ca02a935e8eb 7 /**
d34d 4:ca02a935e8eb 8 * TXRX state
d34d 4:ca02a935e8eb 9 */
d34d 3:cd7f899f155f 10 enum TXRX_State {
d34d 3:cd7f899f155f 11 TXRX_OFF,
d34d 3:cd7f899f155f 12 TX_EN,
d34d 3:cd7f899f155f 13 RX_EN,
d34d 3:cd7f899f155f 14 };
d34d 3:cd7f899f155f 15
d34d 4:ca02a935e8eb 16 /**
d34d 4:ca02a935e8eb 17 * A7105 states for strobe
d34d 4:ca02a935e8eb 18 */
d34d 3:cd7f899f155f 19 enum A7105_State {
d34d 3:cd7f899f155f 20 A7105_SLEEP = 0x80,
d34d 3:cd7f899f155f 21 A7105_IDLE = 0x90,
d34d 3:cd7f899f155f 22 A7105_STANDBY = 0xA0,
d34d 3:cd7f899f155f 23 A7105_PLL = 0xB0,
d34d 3:cd7f899f155f 24 A7105_RX = 0xC0,
d34d 3:cd7f899f155f 25 A7105_TX = 0xD0,
d34d 3:cd7f899f155f 26 A7105_RST_WRPTR = 0xE0,
d34d 3:cd7f899f155f 27 A7105_RST_RDPTR = 0xF0,
d34d 3:cd7f899f155f 28 };
d34d 3:cd7f899f155f 29
d34d 4:ca02a935e8eb 30 /**
d34d 4:ca02a935e8eb 31 * Register addresses
d34d 4:ca02a935e8eb 32 */
d34d 3:cd7f899f155f 33 enum {
d34d 3:cd7f899f155f 34 A7105_00_MODE = 0x00,
d34d 3:cd7f899f155f 35 A7105_01_MODE_CONTROL = 0x01,
d34d 3:cd7f899f155f 36 A7105_02_CALC = 0x02,
d34d 3:cd7f899f155f 37 A7105_03_FIFOI = 0x03,
d34d 3:cd7f899f155f 38 A7105_04_FIFOII = 0x04,
d34d 3:cd7f899f155f 39 A7105_05_FIFO_DATA = 0x05,
d34d 3:cd7f899f155f 40 A7105_06_ID_DATA = 0x06,
d34d 3:cd7f899f155f 41 A7105_07_RC_OSC_I = 0x07,
d34d 3:cd7f899f155f 42 A7105_08_RC_OSC_II = 0x08,
d34d 3:cd7f899f155f 43 A7105_09_RC_OSC_III = 0x09,
d34d 3:cd7f899f155f 44 A7105_0A_CK0_PIN = 0x0A,
d34d 3:cd7f899f155f 45 A7105_0B_GPIO1_PIN_I = 0x0B,
d34d 3:cd7f899f155f 46 A7105_0C_GPIO2_PIN_II = 0x0C,
d34d 3:cd7f899f155f 47 A7105_0D_CLOCK = 0x0D,
d34d 3:cd7f899f155f 48 A7105_0E_DATA_RATE = 0x0E,
d34d 3:cd7f899f155f 49 A7105_0F_PLL_I = 0x0F,
d34d 3:cd7f899f155f 50 A7105_10_PLL_II = 0x10,
d34d 3:cd7f899f155f 51 A7105_11_PLL_III = 0x11,
d34d 3:cd7f899f155f 52 A7105_12_PLL_IV = 0x12,
d34d 3:cd7f899f155f 53 A7105_13_PLL_V = 0x13,
d34d 3:cd7f899f155f 54 A7105_14_TX_I = 0x14,
d34d 3:cd7f899f155f 55 A7105_15_TX_II = 0x15,
d34d 3:cd7f899f155f 56 A7105_16_DELAY_I = 0x16,
d34d 3:cd7f899f155f 57 A7105_17_DELAY_II = 0x17,
d34d 3:cd7f899f155f 58 A7105_18_RX = 0x18,
d34d 3:cd7f899f155f 59 A7105_19_RX_GAIN_I = 0x19,
d34d 3:cd7f899f155f 60 A7105_1A_RX_GAIN_II = 0x1A,
d34d 3:cd7f899f155f 61 A7105_1B_RX_GAIN_III = 0x1B,
d34d 3:cd7f899f155f 62 A7105_1C_RX_GAIN_IV = 0x1C,
d34d 3:cd7f899f155f 63 A7105_1D_RSSI_THOLD = 0x1D,
d34d 3:cd7f899f155f 64 A7105_1E_ADC = 0x1E,
d34d 3:cd7f899f155f 65 A7105_1F_CODE_I = 0x1F,
d34d 3:cd7f899f155f 66 A7105_20_CODE_II = 0x20,
d34d 3:cd7f899f155f 67 A7105_21_CODE_III = 0x21,
d34d 3:cd7f899f155f 68 A7105_22_IF_CALIB_I = 0x22,
d34d 3:cd7f899f155f 69 A7105_23_IF_CALIB_II = 0x23,
d34d 3:cd7f899f155f 70 A7105_24_VCO_CURCAL = 0x24,
d34d 3:cd7f899f155f 71 A7105_25_VCO_SBCAL_I = 0x25,
d34d 3:cd7f899f155f 72 A7105_26_VCO_SBCAL_II = 0x26,
d34d 3:cd7f899f155f 73 A7105_27_BATTERY_DET = 0x27,
d34d 3:cd7f899f155f 74 A7105_28_TX_TEST = 0x28,
d34d 3:cd7f899f155f 75 A7105_29_RX_DEM_TEST_I = 0x29,
d34d 3:cd7f899f155f 76 A7105_2A_RX_DEM_TEST_II = 0x2A,
d34d 3:cd7f899f155f 77 A7105_2B_CPC = 0x2B,
d34d 3:cd7f899f155f 78 A7105_2C_XTAL_TEST = 0x2C,
d34d 3:cd7f899f155f 79 A7105_2D_PLL_TEST = 0x2D,
d34d 3:cd7f899f155f 80 A7105_2E_VCO_TEST_I = 0x2E,
d34d 3:cd7f899f155f 81 A7105_2F_VCO_TEST_II = 0x2F,
d34d 3:cd7f899f155f 82 A7105_30_IFAT = 0x30,
d34d 3:cd7f899f155f 83 A7105_31_RSCALE = 0x31,
d34d 3:cd7f899f155f 84 A7105_32_FILTER_TEST = 0x32,
d34d 3:cd7f899f155f 85 };
d34d 3:cd7f899f155f 86 #define A7105_0F_CHANNEL A7105_0F_PLL_I
d34d 3:cd7f899f155f 87
d34d 3:cd7f899f155f 88 enum A7105_MASK {
d34d 3:cd7f899f155f 89 A7105_MASK_FBCF = 1 << 4,
d34d 3:cd7f899f155f 90 A7105_MASK_VBCF = 1 << 3,
d34d 3:cd7f899f155f 91 };
d34d 0:212eb977fe10 92
d34d 0:212eb977fe10 93 /**
d34d 0:212eb977fe10 94 * Class for interfacing with the AMICCOM A7105 2.4G FSK/GFSK Transceiver
d34d 0:212eb977fe10 95 *
d34d 0:212eb977fe10 96 * See the A7105 datasheet for complete documentation on this part
d34d 0:212eb977fe10 97 * http://www.avantcom.com.tw/AVANTCOM/TC/DATA/PRODUCT/SOLVE/18_3.pdf
d34d 1:2ae040ee7239 98 *
d34d 1:2ae040ee7239 99 *
d34d 1:2ae040ee7239 100 * Example:
d34d 1:2ae040ee7239 101 * @code
d34d 1:2ae040ee7239 102 * #include "mbed.h"
d34d 5:a070723fc0ed 103 * #include "A7105.h"
d34d 1:2ae040ee7239 104 *
d34d 1:2ae040ee7239 105 * #define A7105_SPI_FREQUENCY 10000000 // 10MHz
d34d 1:2ae040ee7239 106 *
d34d 1:2ae040ee7239 107 * A7105 txrx(D4, D5, D3, D6, A7105_SPI_FREQUENCY);
d34d 1:2ae040ee7239 108 *
d34d 1:2ae040ee7239 109 * int main() {
d34d 1:2ae040ee7239 110 * // reset
d34d 1:2ae040ee7239 111 * ret = txrx.reset();
d34d 1:2ae040ee7239 112 * // use GPIO1 as miso
d34d 4:ca02a935e8eb 113 * ret = txrx.writeRegister(A7105_0B_GPIO1_PIN_I, 0x19);
d34d 1:2ae040ee7239 114 * // set various radio options
d34d 4:ca02a935e8eb 115 * ret = txrx.writeRegister(A7105_01_MODE_CONTROL, 0x63);
d34d 1:2ae040ee7239 116 * // set packet length (FIFO end pointer) to 0x0f + 1 == 16
d34d 4:ca02a935e8eb 117 * ret = txrx.writeRegister(A7105_03_FIFOI, 0x0f);
d34d 1:2ae040ee7239 118 * // select crystal oscillator and system clock divider of 1/2
d34d 4:ca02a935e8eb 119 * ret = txrx.writeRegister(A7105_0D_CLOCK, 0x05);
d34d 1:2ae040ee7239 120 *
d34d 1:2ae040ee7239 121 * // sanity check
d34d 4:ca02a935e8eb 122 * ret = txrx.readRegister(A7105_0D_CLOCK);
d34d 1:2ae040ee7239 123 * if (ret != 0x05) {
d34d 1:2ae040ee7239 124 * // do something :)
d34d 1:2ae040ee7239 125 * }
d34d 1:2ae040ee7239 126 * }
d34d 1:2ae040ee7239 127 * @endcode
d34d 0:212eb977fe10 128 */
d34d 0:212eb977fe10 129 class A7105 {
d34d 0:212eb977fe10 130 public:
d34d 0:212eb977fe10 131 /**
d34d 0:212eb977fe10 132 * @param mosi Pin used to transmit data to the slave
d34d 0:212eb977fe10 133 * @param miso Pin used to receive data from the slave
d34d 0:212eb977fe10 134 * @param clk Pin used for the clock
d34d 0:212eb977fe10 135 * @param cs Pin used for the chip select
d34d 0:212eb977fe10 136 * @param freqHz Frequency used to clock data in and out
d34d 0:212eb977fe10 137 */
d34d 0:212eb977fe10 138 A7105(PinName mosi, PinName miso, PinName clk, PinName cs, uint32_t freqHz);
d34d 0:212eb977fe10 139 ~A7105();
d34d 0:212eb977fe10 140
d34d 0:212eb977fe10 141 /**
d34d 0:212eb977fe10 142 * Writes a value to the given register
d34d 0:212eb977fe10 143 *
d34d 0:212eb977fe10 144 * @param regAddr Address of the register to write to
d34d 0:212eb977fe10 145 * @param value Value to write into the register
d34d 0:212eb977fe10 146 * @return Value returned from slave when writing the register
d34d 0:212eb977fe10 147 */
d34d 0:212eb977fe10 148 uint8_t writeRegister(uint8_t regAddr, uint8_t value);
d34d 0:212eb977fe10 149
d34d 0:212eb977fe10 150 /**
d34d 0:212eb977fe10 151 * Reads a value from the given register
d34d 0:212eb977fe10 152 *
d34d 0:212eb977fe10 153 * @param regAddr Address of the register to read
d34d 0:212eb977fe10 154 * @return The value of the register
d34d 0:212eb977fe10 155 */
d34d 0:212eb977fe10 156 uint8_t readRegister(uint8_t regAddr);
d34d 0:212eb977fe10 157
d34d 4:ca02a935e8eb 158 /**
d34d 4:ca02a935e8eb 159 * Sends a strobe command to the A7105
d34d 4:ca02a935e8eb 160 *
d34d 4:ca02a935e8eb 161 * @param state Strobe command state
d34d 4:ca02a935e8eb 162 */
d34d 3:cd7f899f155f 163 uint8_t strobe(enum A7105_State state);
d34d 3:cd7f899f155f 164
d34d 3:cd7f899f155f 165 /**
d34d 4:ca02a935e8eb 166 * Send a packet of data to the A7105
d34d 3:cd7f899f155f 167 *
d34d 3:cd7f899f155f 168 * @param data Byte array to send
d34d 3:cd7f899f155f 169 * @param len Length of the byte array
d34d 8:033e328fb7c3 170 * @param channel Channel to transmit data on
d34d 3:cd7f899f155f 171 */
d34d 8:033e328fb7c3 172 void writeData(uint8_t* data, size_t len, uint8_t channel);
d34d 3:cd7f899f155f 173
d34d 4:ca02a935e8eb 174 /**
d34d 4:ca02a935e8eb 175 * Read a packet of date from the A7105
d34d 4:ca02a935e8eb 176 *
d34d 4:ca02a935e8eb 177 * @param buffer Byte array to hold the incoming data
d34d 4:ca02a935e8eb 178 * @param len Length of the buffer, number of bytes to read in
d34d 4:ca02a935e8eb 179 */
d34d 3:cd7f899f155f 180 void readData(uint8_t* buffer, size_t len);
d34d 3:cd7f899f155f 181
d34d 4:ca02a935e8eb 182 /**
d34d 4:ca02a935e8eb 183 * Set the A7105's ID
d34d 4:ca02a935e8eb 184 *
d34d 4:ca02a935e8eb 185 * @param id 32-bit identifier
d34d 4:ca02a935e8eb 186 */
d34d 3:cd7f899f155f 187 void setId(uint32_t id);
d34d 3:cd7f899f155f 188
d34d 4:ca02a935e8eb 189 /**
d34d 4:ca02a935e8eb 190 * Set the TX power
d34d 4:ca02a935e8eb 191 *
d34d 4:ca02a935e8eb 192 * @param power Output power in dBm
d34d 4:ca02a935e8eb 193 */
d34d 3:cd7f899f155f 194 void setPower(int32_t power);
d34d 3:cd7f899f155f 195
d34d 4:ca02a935e8eb 196 /**
d34d 4:ca02a935e8eb 197 * Sets the TxRx mode
d34d 4:ca02a935e8eb 198 *
d34d 4:ca02a935e8eb 199 * @aparam mode TxRx mode
d34d 4:ca02a935e8eb 200 */
d34d 3:cd7f899f155f 201 void setTxRxMode(enum TXRX_State mode);
d34d 3:cd7f899f155f 202
d34d 0:212eb977fe10 203 /**
d34d 0:212eb977fe10 204 * Resets the A7105, putting it into standby mode.
d34d 0:212eb977fe10 205 */
d34d 3:cd7f899f155f 206 int8_t reset();
d34d 0:212eb977fe10 207
d34d 0:212eb977fe10 208 private:
d34d 4:ca02a935e8eb 209 SPI _spi;
d34d 4:ca02a935e8eb 210 DigitalOut _cs;
d34d 7:1b1d7e446aa4 211
d34d 7:1b1d7e446aa4 212 inline void assertChipSelect() { _cs = 0; wait_us(1); }
d34d 7:1b1d7e446aa4 213 inline void deassertChipSelect() { wait_us(1); _cs = 1; }
d34d 0:212eb977fe10 214 };
d34d 0:212eb977fe10 215
d34d 0:212eb977fe10 216 #endif // #ifndef _A7105_TX_RX_H