Clark Scheff / A7105TxRx

Library for interfacing with the AMICCOM A7105 2.4GHz FSK/GFSK Transceiver.

Dependents:   HubsanTX

a7105txrx.h@0:212eb977fe10, 2014-09-01 (annotated)

Committer:
d34d
Date:
Mon Sep 01 19:38:06 2014 +0000
Revision:
0:212eb977fe10
Child:
1:2ae040ee7239
Initial commit since we gotta start somewhere.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
d34d 0:212eb977fe10 1 #ifndef _A7105_TX_RX_H
d34d 0:212eb977fe10 2 #define _A7105_TX_RX_H
d34d 0:212eb977fe10 3
d34d 0:212eb977fe10 4 /******************************
d34d 0:212eb977fe10 5 * Control register addresses *
d34d 0:212eb977fe10 6 ******************************/
d34d 0:212eb977fe10 7 //! Mode register
d34d 0:212eb977fe10 8 #define MODE 0x00
d34d 0:212eb977fe10 9 //! Mode control register
d34d 0:212eb977fe10 10 #define MODE_CONTROL 0x01
d34d 0:212eb977fe10 11 //! Calibration control register
d34d 0:212eb977fe10 12 #define CALC 0x02
d34d 0:212eb977fe10 13 //! FIFO register 1
d34d 0:212eb977fe10 14 #define FIFO_1 0x03
d34d 0:212eb977fe10 15 //! FIFO register 2
d34d 0:212eb977fe10 16 #define FIFO_2 0x04
d34d 0:212eb977fe10 17 //! FIFO data register
d34d 0:212eb977fe10 18 #define FIFO_DATA 0x05
d34d 0:212eb977fe10 19 //! ID data register
d34d 0:212eb977fe10 20 #define ID_DATA 0x06
d34d 0:212eb977fe10 21 //! RC OSC register 1
d34d 0:212eb977fe10 22 #define RC_OSC_1 0x07
d34d 0:212eb977fe10 23 //! RC OSC register 2
d34d 0:212eb977fe10 24 #define RC_OSC_2 0x08
d34d 0:212eb977fe10 25 //! RC OSC register 3
d34d 0:212eb977fe10 26 #define RC_OSC_3 0x09
d34d 0:212eb977fe10 27 //! CKO pin control register
d34d 0:212eb977fe10 28 #define CKO 0x0A
d34d 0:212eb977fe10 29 //! GPIO1 pin control register
d34d 0:212eb977fe10 30 #define GPIO1 0x0B
d34d 0:212eb977fe10 31 //! GPIO2 pin control register
d34d 0:212eb977fe10 32 #define CPIO2 0x0C
d34d 0:212eb977fe10 33 //! Clock register
d34d 0:212eb977fe10 34 #define CLOCK 0x0D
d34d 0:212eb977fe10 35 //! Data rate register
d34d 0:212eb977fe10 36 #define DATA_RATE 0x0E
d34d 0:212eb977fe10 37 //! PLL register 1
d34d 0:212eb977fe10 38 #define PLL_1 0x0F
d34d 0:212eb977fe10 39 //! PLL register 2
d34d 0:212eb977fe10 40 #define PLL_2 0x10
d34d 0:212eb977fe10 41 //! PLL register 3
d34d 0:212eb977fe10 42 #define PLL_3 0x11
d34d 0:212eb977fe10 43 //! PLL register 4
d34d 0:212eb977fe10 44 #define PLL_4 0x12
d34d 0:212eb977fe10 45 //! PLL register 5
d34d 0:212eb977fe10 46 #define PLL_5 0x13
d34d 0:212eb977fe10 47 //! TX register 1
d34d 0:212eb977fe10 48 #define TX_1 0x14
d34d 0:212eb977fe10 49 //! TX register 2
d34d 0:212eb977fe10 50 #define TX_2 0x15
d34d 0:212eb977fe10 51 //! Delay register 1
d34d 0:212eb977fe10 52 #define DELAY_1 0x16
d34d 0:212eb977fe10 53 //! Delay register 2
d34d 0:212eb977fe10 54 #define DELAY_2 0x17
d34d 0:212eb977fe10 55 //! RX register
d34d 0:212eb977fe10 56 #define RX 0x18
d34d 0:212eb977fe10 57 //! RX gain register 1
d34d 0:212eb977fe10 58 #define RX_GAIN_1 0x19
d34d 0:212eb977fe10 59 //! RX gain register 2
d34d 0:212eb977fe10 60 #define RX_GAIN_2 0x1A
d34d 0:212eb977fe10 61 //! RX gain register 3
d34d 0:212eb977fe10 62 #define RX_GAIN_3 0x1B
d34d 0:212eb977fe10 63 //! RX gain register 4
d34d 0:212eb977fe10 64 #define RX_GAIN_4 0x1C
d34d 0:212eb977fe10 65 //! RSSI threshold register
d34d 0:212eb977fe10 66 #define RSSI_THRESHOLD 0x1D
d34d 0:212eb977fe10 67 //! ADC control register
d34d 0:212eb977fe10 68 #define ADC_CONTROL 0x1E
d34d 0:212eb977fe10 69 //! Code register 1
d34d 0:212eb977fe10 70 #define CODE_1 0x1F
d34d 0:212eb977fe10 71 //! Code register 2
d34d 0:212eb977fe10 72 #define CODE_2 0x20
d34d 0:212eb977fe10 73 //! Code register 3
d34d 0:212eb977fe10 74 #define CODE_3 0x21
d34d 0:212eb977fe10 75 //! IF calibration register 1
d34d 0:212eb977fe10 76 #define IF_CAL_1 0x22
d34d 0:212eb977fe10 77 //! IF calibration register 2
d34d 0:212eb977fe10 78 #define IF_CAL_2 0x23
d34d 0:212eb977fe10 79 //! VCO current calibration register
d34d 0:212eb977fe10 80 #define VCO_CUR_CAL 0x24
d34d 0:212eb977fe10 81 //! VCO single band calibration register 1
d34d 0:212eb977fe10 82 #define VCO_SBC_1 0x25
d34d 0:212eb977fe10 83 //! VCO single band calibration register 2
d34d 0:212eb977fe10 84 #define VCO_SBC_2 0x26
d34d 0:212eb977fe10 85 //! Battery detect register
d34d 0:212eb977fe10 86 #define BATTERY_DETECT 0x27
d34d 0:212eb977fe10 87 //! TX test register
d34d 0:212eb977fe10 88 #define TX_TEST 0x28
d34d 0:212eb977fe10 89 //! RX dem test register 1
d34d 0:212eb977fe10 90 #define RX_DEM_TEST_1 0x29
d34d 0:212eb977fe10 91 //! RX dem test register 2
d34d 0:212eb977fe10 92 #define RX_DEM_TEST_2 0x2A
d34d 0:212eb977fe10 93 //! Charge pump current register
d34d 0:212eb977fe10 94 #define CPC 0x2B
d34d 0:212eb977fe10 95 //! Crystal test register
d34d 0:212eb977fe10 96 #define XTAL_TEST 0x2C
d34d 0:212eb977fe10 97 //! PLL test register
d34d 0:212eb977fe10 98 #define PLL_TEST 0x2D
d34d 0:212eb977fe10 99 //! VCO test register 1
d34d 0:212eb977fe10 100 #define VCO_TEST_1 0x2E
d34d 0:212eb977fe10 101 //! VCO test register 2
d34d 0:212eb977fe10 102 #define VCO_TEST_2 0x2F
d34d 0:212eb977fe10 103 //! IFAT register
d34d 0:212eb977fe10 104 #define IFAT 0x30
d34d 0:212eb977fe10 105 //! RScale register
d34d 0:212eb977fe10 106 #define RSCALE 0x31
d34d 0:212eb977fe10 107 //! Filter test register
d34d 0:212eb977fe10 108 #define FILTER_TEST 0x32
d34d 0:212eb977fe10 109
d34d 0:212eb977fe10 110 /**
d34d 0:212eb977fe10 111 * Class for interfacing with the AMICCOM A7105 2.4G FSK/GFSK Transceiver
d34d 0:212eb977fe10 112 *
d34d 0:212eb977fe10 113 * See the A7105 datasheet for complete documentation on this part
d34d 0:212eb977fe10 114 * http://www.avantcom.com.tw/AVANTCOM/TC/DATA/PRODUCT/SOLVE/18_3.pdf
d34d 0:212eb977fe10 115 */
d34d 0:212eb977fe10 116 class A7105 {
d34d 0:212eb977fe10 117 public:
d34d 0:212eb977fe10 118 /**
d34d 0:212eb977fe10 119 * @param mosi Pin used to transmit data to the slave
d34d 0:212eb977fe10 120 * @param miso Pin used to receive data from the slave
d34d 0:212eb977fe10 121 * @param clk Pin used for the clock
d34d 0:212eb977fe10 122 * @param cs Pin used for the chip select
d34d 0:212eb977fe10 123 * @param freqHz Frequency used to clock data in and out
d34d 0:212eb977fe10 124 */
d34d 0:212eb977fe10 125 A7105(PinName mosi, PinName miso, PinName clk, PinName cs, uint32_t freqHz);
d34d 0:212eb977fe10 126 ~A7105();
d34d 0:212eb977fe10 127
d34d 0:212eb977fe10 128 /**
d34d 0:212eb977fe10 129 * Writes a value to the given register
d34d 0:212eb977fe10 130 *
d34d 0:212eb977fe10 131 * @param regAddr Address of the register to write to
d34d 0:212eb977fe10 132 * @param value Value to write into the register
d34d 0:212eb977fe10 133 * @return Value returned from slave when writing the register
d34d 0:212eb977fe10 134 */
d34d 0:212eb977fe10 135 uint8_t writeRegister(uint8_t regAddr, uint8_t value);
d34d 0:212eb977fe10 136
d34d 0:212eb977fe10 137 /**
d34d 0:212eb977fe10 138 * Reads a value from the given register
d34d 0:212eb977fe10 139 *
d34d 0:212eb977fe10 140 * @param regAddr Address of the register to read
d34d 0:212eb977fe10 141 * @return The value of the register
d34d 0:212eb977fe10 142 */
d34d 0:212eb977fe10 143 uint8_t readRegister(uint8_t regAddr);
d34d 0:212eb977fe10 144
d34d 0:212eb977fe10 145 /**
d34d 0:212eb977fe10 146 * Resets the A7105, putting it into standby mode.
d34d 0:212eb977fe10 147 *
d34d 0:212eb977fe10 148 * @return Value returned from the slave after writing 0x00 to the MODE register.
d34d 0:212eb977fe10 149 */
d34d 0:212eb977fe10 150 uint8_t reset();
d34d 0:212eb977fe10 151
d34d 0:212eb977fe10 152 private:
d34d 0:212eb977fe10 153 SPI mSpiMaster;
d34d 0:212eb977fe10 154 DigitalOut mChipSelect;
d34d 0:212eb977fe10 155 };
d34d 0:212eb977fe10 156
d34d 0:212eb977fe10 157 #endif // #ifndef _A7105_TX_RX_H