Library for interfacing with the AMICCOM A7105 2.4GHz FSK/GFSK Transceiver.
a7105txrx.h@3:cd7f899f155f, 2015-01-01 (annotated)
- Committer:
- d34d
- Date:
- Thu Jan 01 05:18:12 2015 +0000
- Revision:
- 3:cd7f899f155f
- Parent:
- 1:2ae040ee7239
Make A7105 class mo-better
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
d34d | 0:212eb977fe10 | 1 | #ifndef _A7105_TX_RX_H |
d34d | 0:212eb977fe10 | 2 | #define _A7105_TX_RX_H |
d34d | 0:212eb977fe10 | 3 | |
d34d | 3:cd7f899f155f | 4 | #define _WRITE(a) ((a) & ~0x40) |
d34d | 3:cd7f899f155f | 5 | #define _READ(a) ((a) | 0x40) |
d34d | 3:cd7f899f155f | 6 | |
d34d | 3:cd7f899f155f | 7 | enum TXRX_State { |
d34d | 3:cd7f899f155f | 8 | TXRX_OFF, |
d34d | 3:cd7f899f155f | 9 | TX_EN, |
d34d | 3:cd7f899f155f | 10 | RX_EN, |
d34d | 3:cd7f899f155f | 11 | }; |
d34d | 3:cd7f899f155f | 12 | |
d34d | 3:cd7f899f155f | 13 | enum A7105_State { |
d34d | 3:cd7f899f155f | 14 | A7105_SLEEP = 0x80, |
d34d | 3:cd7f899f155f | 15 | A7105_IDLE = 0x90, |
d34d | 3:cd7f899f155f | 16 | A7105_STANDBY = 0xA0, |
d34d | 3:cd7f899f155f | 17 | A7105_PLL = 0xB0, |
d34d | 3:cd7f899f155f | 18 | A7105_RX = 0xC0, |
d34d | 3:cd7f899f155f | 19 | A7105_TX = 0xD0, |
d34d | 3:cd7f899f155f | 20 | A7105_RST_WRPTR = 0xE0, |
d34d | 3:cd7f899f155f | 21 | A7105_RST_RDPTR = 0xF0, |
d34d | 3:cd7f899f155f | 22 | }; |
d34d | 3:cd7f899f155f | 23 | |
d34d | 3:cd7f899f155f | 24 | enum { |
d34d | 3:cd7f899f155f | 25 | A7105_00_MODE = 0x00, |
d34d | 3:cd7f899f155f | 26 | A7105_01_MODE_CONTROL = 0x01, |
d34d | 3:cd7f899f155f | 27 | A7105_02_CALC = 0x02, |
d34d | 3:cd7f899f155f | 28 | A7105_03_FIFOI = 0x03, |
d34d | 3:cd7f899f155f | 29 | A7105_04_FIFOII = 0x04, |
d34d | 3:cd7f899f155f | 30 | A7105_05_FIFO_DATA = 0x05, |
d34d | 3:cd7f899f155f | 31 | A7105_06_ID_DATA = 0x06, |
d34d | 3:cd7f899f155f | 32 | A7105_07_RC_OSC_I = 0x07, |
d34d | 3:cd7f899f155f | 33 | A7105_08_RC_OSC_II = 0x08, |
d34d | 3:cd7f899f155f | 34 | A7105_09_RC_OSC_III = 0x09, |
d34d | 3:cd7f899f155f | 35 | A7105_0A_CK0_PIN = 0x0A, |
d34d | 3:cd7f899f155f | 36 | A7105_0B_GPIO1_PIN_I = 0x0B, |
d34d | 3:cd7f899f155f | 37 | A7105_0C_GPIO2_PIN_II = 0x0C, |
d34d | 3:cd7f899f155f | 38 | A7105_0D_CLOCK = 0x0D, |
d34d | 3:cd7f899f155f | 39 | A7105_0E_DATA_RATE = 0x0E, |
d34d | 3:cd7f899f155f | 40 | A7105_0F_PLL_I = 0x0F, |
d34d | 3:cd7f899f155f | 41 | A7105_10_PLL_II = 0x10, |
d34d | 3:cd7f899f155f | 42 | A7105_11_PLL_III = 0x11, |
d34d | 3:cd7f899f155f | 43 | A7105_12_PLL_IV = 0x12, |
d34d | 3:cd7f899f155f | 44 | A7105_13_PLL_V = 0x13, |
d34d | 3:cd7f899f155f | 45 | A7105_14_TX_I = 0x14, |
d34d | 3:cd7f899f155f | 46 | A7105_15_TX_II = 0x15, |
d34d | 3:cd7f899f155f | 47 | A7105_16_DELAY_I = 0x16, |
d34d | 3:cd7f899f155f | 48 | A7105_17_DELAY_II = 0x17, |
d34d | 3:cd7f899f155f | 49 | A7105_18_RX = 0x18, |
d34d | 3:cd7f899f155f | 50 | A7105_19_RX_GAIN_I = 0x19, |
d34d | 3:cd7f899f155f | 51 | A7105_1A_RX_GAIN_II = 0x1A, |
d34d | 3:cd7f899f155f | 52 | A7105_1B_RX_GAIN_III = 0x1B, |
d34d | 3:cd7f899f155f | 53 | A7105_1C_RX_GAIN_IV = 0x1C, |
d34d | 3:cd7f899f155f | 54 | A7105_1D_RSSI_THOLD = 0x1D, |
d34d | 3:cd7f899f155f | 55 | A7105_1E_ADC = 0x1E, |
d34d | 3:cd7f899f155f | 56 | A7105_1F_CODE_I = 0x1F, |
d34d | 3:cd7f899f155f | 57 | A7105_20_CODE_II = 0x20, |
d34d | 3:cd7f899f155f | 58 | A7105_21_CODE_III = 0x21, |
d34d | 3:cd7f899f155f | 59 | A7105_22_IF_CALIB_I = 0x22, |
d34d | 3:cd7f899f155f | 60 | A7105_23_IF_CALIB_II = 0x23, |
d34d | 3:cd7f899f155f | 61 | A7105_24_VCO_CURCAL = 0x24, |
d34d | 3:cd7f899f155f | 62 | A7105_25_VCO_SBCAL_I = 0x25, |
d34d | 3:cd7f899f155f | 63 | A7105_26_VCO_SBCAL_II = 0x26, |
d34d | 3:cd7f899f155f | 64 | A7105_27_BATTERY_DET = 0x27, |
d34d | 3:cd7f899f155f | 65 | A7105_28_TX_TEST = 0x28, |
d34d | 3:cd7f899f155f | 66 | A7105_29_RX_DEM_TEST_I = 0x29, |
d34d | 3:cd7f899f155f | 67 | A7105_2A_RX_DEM_TEST_II = 0x2A, |
d34d | 3:cd7f899f155f | 68 | A7105_2B_CPC = 0x2B, |
d34d | 3:cd7f899f155f | 69 | A7105_2C_XTAL_TEST = 0x2C, |
d34d | 3:cd7f899f155f | 70 | A7105_2D_PLL_TEST = 0x2D, |
d34d | 3:cd7f899f155f | 71 | A7105_2E_VCO_TEST_I = 0x2E, |
d34d | 3:cd7f899f155f | 72 | A7105_2F_VCO_TEST_II = 0x2F, |
d34d | 3:cd7f899f155f | 73 | A7105_30_IFAT = 0x30, |
d34d | 3:cd7f899f155f | 74 | A7105_31_RSCALE = 0x31, |
d34d | 3:cd7f899f155f | 75 | A7105_32_FILTER_TEST = 0x32, |
d34d | 3:cd7f899f155f | 76 | }; |
d34d | 3:cd7f899f155f | 77 | #define A7105_0F_CHANNEL A7105_0F_PLL_I |
d34d | 3:cd7f899f155f | 78 | |
d34d | 3:cd7f899f155f | 79 | enum A7105_MASK { |
d34d | 3:cd7f899f155f | 80 | A7105_MASK_FBCF = 1 << 4, |
d34d | 3:cd7f899f155f | 81 | A7105_MASK_VBCF = 1 << 3, |
d34d | 3:cd7f899f155f | 82 | }; |
d34d | 0:212eb977fe10 | 83 | |
d34d | 0:212eb977fe10 | 84 | /** |
d34d | 0:212eb977fe10 | 85 | * Class for interfacing with the AMICCOM A7105 2.4G FSK/GFSK Transceiver |
d34d | 0:212eb977fe10 | 86 | * |
d34d | 0:212eb977fe10 | 87 | * See the A7105 datasheet for complete documentation on this part |
d34d | 0:212eb977fe10 | 88 | * http://www.avantcom.com.tw/AVANTCOM/TC/DATA/PRODUCT/SOLVE/18_3.pdf |
d34d | 1:2ae040ee7239 | 89 | * |
d34d | 1:2ae040ee7239 | 90 | * |
d34d | 1:2ae040ee7239 | 91 | * Example: |
d34d | 1:2ae040ee7239 | 92 | * @code |
d34d | 1:2ae040ee7239 | 93 | * #include "mbed.h" |
d34d | 1:2ae040ee7239 | 94 | * #include "a7105txrx.h" |
d34d | 1:2ae040ee7239 | 95 | * |
d34d | 1:2ae040ee7239 | 96 | * #define A7105_SPI_FREQUENCY 10000000 // 10MHz |
d34d | 1:2ae040ee7239 | 97 | * |
d34d | 1:2ae040ee7239 | 98 | * A7105 txrx(D4, D5, D3, D6, A7105_SPI_FREQUENCY); |
d34d | 1:2ae040ee7239 | 99 | * |
d34d | 1:2ae040ee7239 | 100 | * int main() { |
d34d | 1:2ae040ee7239 | 101 | * // reset |
d34d | 1:2ae040ee7239 | 102 | * ret = txrx.reset(); |
d34d | 1:2ae040ee7239 | 103 | * // use GPIO1 as miso |
d34d | 1:2ae040ee7239 | 104 | * ret = txrx.writeRegister(GPIO1, 0x19); |
d34d | 1:2ae040ee7239 | 105 | * // set various radio options |
d34d | 1:2ae040ee7239 | 106 | * ret = txrx.writeRegister(MODE_CONTROL, 0x63); |
d34d | 1:2ae040ee7239 | 107 | * // set packet length (FIFO end pointer) to 0x0f + 1 == 16 |
d34d | 1:2ae040ee7239 | 108 | * ret = txrx.writeRegister(FIFO_1, 0x0f); |
d34d | 1:2ae040ee7239 | 109 | * // select crystal oscillator and system clock divider of 1/2 |
d34d | 1:2ae040ee7239 | 110 | * ret = txrx.writeRegister(CLOCK, 0x05); |
d34d | 1:2ae040ee7239 | 111 | * |
d34d | 1:2ae040ee7239 | 112 | * // sanity check |
d34d | 1:2ae040ee7239 | 113 | * ret = txrx.readRegister(CLOCK); |
d34d | 1:2ae040ee7239 | 114 | * if (ret != 0x05) { |
d34d | 1:2ae040ee7239 | 115 | * // do something :) |
d34d | 1:2ae040ee7239 | 116 | * } |
d34d | 1:2ae040ee7239 | 117 | * } |
d34d | 1:2ae040ee7239 | 118 | * @endcode |
d34d | 0:212eb977fe10 | 119 | */ |
d34d | 0:212eb977fe10 | 120 | class A7105 { |
d34d | 0:212eb977fe10 | 121 | public: |
d34d | 0:212eb977fe10 | 122 | /** |
d34d | 0:212eb977fe10 | 123 | * @param mosi Pin used to transmit data to the slave |
d34d | 0:212eb977fe10 | 124 | * @param miso Pin used to receive data from the slave |
d34d | 0:212eb977fe10 | 125 | * @param clk Pin used for the clock |
d34d | 0:212eb977fe10 | 126 | * @param cs Pin used for the chip select |
d34d | 0:212eb977fe10 | 127 | * @param freqHz Frequency used to clock data in and out |
d34d | 0:212eb977fe10 | 128 | */ |
d34d | 0:212eb977fe10 | 129 | A7105(PinName mosi, PinName miso, PinName clk, PinName cs, uint32_t freqHz); |
d34d | 0:212eb977fe10 | 130 | ~A7105(); |
d34d | 0:212eb977fe10 | 131 | |
d34d | 0:212eb977fe10 | 132 | /** |
d34d | 0:212eb977fe10 | 133 | * Writes a value to the given register |
d34d | 0:212eb977fe10 | 134 | * |
d34d | 0:212eb977fe10 | 135 | * @param regAddr Address of the register to write to |
d34d | 0:212eb977fe10 | 136 | * @param value Value to write into the register |
d34d | 0:212eb977fe10 | 137 | * @return Value returned from slave when writing the register |
d34d | 0:212eb977fe10 | 138 | */ |
d34d | 0:212eb977fe10 | 139 | uint8_t writeRegister(uint8_t regAddr, uint8_t value); |
d34d | 0:212eb977fe10 | 140 | |
d34d | 0:212eb977fe10 | 141 | /** |
d34d | 0:212eb977fe10 | 142 | * Reads a value from the given register |
d34d | 0:212eb977fe10 | 143 | * |
d34d | 0:212eb977fe10 | 144 | * @param regAddr Address of the register to read |
d34d | 0:212eb977fe10 | 145 | * @return The value of the register |
d34d | 0:212eb977fe10 | 146 | */ |
d34d | 0:212eb977fe10 | 147 | uint8_t readRegister(uint8_t regAddr); |
d34d | 0:212eb977fe10 | 148 | |
d34d | 3:cd7f899f155f | 149 | uint8_t strobe(enum A7105_State state); |
d34d | 3:cd7f899f155f | 150 | |
d34d | 3:cd7f899f155f | 151 | /** |
d34d | 3:cd7f899f155f | 152 | * Send a packate of data to the A7105 |
d34d | 3:cd7f899f155f | 153 | * |
d34d | 3:cd7f899f155f | 154 | * @param data Byte array to send |
d34d | 3:cd7f899f155f | 155 | * @param len Length of the byte array |
d34d | 3:cd7f899f155f | 156 | */ |
d34d | 3:cd7f899f155f | 157 | void writeData(uint8_t* data, size_t len); |
d34d | 3:cd7f899f155f | 158 | |
d34d | 3:cd7f899f155f | 159 | void readData(uint8_t* buffer, size_t len); |
d34d | 3:cd7f899f155f | 160 | |
d34d | 3:cd7f899f155f | 161 | void setId(uint32_t id); |
d34d | 3:cd7f899f155f | 162 | |
d34d | 3:cd7f899f155f | 163 | void setPower(int32_t power); |
d34d | 3:cd7f899f155f | 164 | |
d34d | 3:cd7f899f155f | 165 | void setTxRxMode(enum TXRX_State mode); |
d34d | 3:cd7f899f155f | 166 | |
d34d | 0:212eb977fe10 | 167 | /** |
d34d | 0:212eb977fe10 | 168 | * Resets the A7105, putting it into standby mode. |
d34d | 0:212eb977fe10 | 169 | */ |
d34d | 3:cd7f899f155f | 170 | int8_t reset(); |
d34d | 0:212eb977fe10 | 171 | |
d34d | 0:212eb977fe10 | 172 | private: |
d34d | 0:212eb977fe10 | 173 | SPI mSpiMaster; |
d34d | 0:212eb977fe10 | 174 | DigitalOut mChipSelect; |
d34d | 0:212eb977fe10 | 175 | }; |
d34d | 0:212eb977fe10 | 176 | |
d34d | 0:212eb977fe10 | 177 | #endif // #ifndef _A7105_TX_RX_H |