clemente di caprio / FRDM_MMA8451Q

Added code to manage Orientation, FreeFall and Motion Detection. Data is also available via IRQ.

Dependents:   Test_FRDM_MMA8451Q AccelTest FRDM-KL46-Template KL25Z_Demo ... more

Fork of MMA8451Q by Emilio Monti

MMA8451Q.cpp@11:13e2af71e2cf, 2013-08-25 (annotated)

Committer:
clemente
Date:
Sun Aug 25 21:53:40 2013 +0000
Revision:
11:13e2af71e2cf
Parent:
10:fa532bf396fb 
changed the name of the pointer to user callback function.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
samux 1:d2630136d51e 1 /* Copyright (c) 2010-2011 mbed.org, MIT License
samux 1:d2630136d51e 2 *
samux 1:d2630136d51e 3 * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
samux 1:d2630136d51e 4 * and associated documentation files (the "Software"), to deal in the Software without
samux 1:d2630136d51e 5 * restriction, including without limitation the rights to use, copy, modify, merge, publish,
samux 1:d2630136d51e 6 * distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
samux 1:d2630136d51e 7 * Software is furnished to do so, subject to the following conditions:
samux 1:d2630136d51e 8 *
samux 1:d2630136d51e 9 * The above copyright notice and this permission notice shall be included in all copies or
samux 1:d2630136d51e 10 * substantial portions of the Software.
samux 1:d2630136d51e 11 *
samux 1:d2630136d51e 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
samux 1:d2630136d51e 13 * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
samux 1:d2630136d51e 14 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
samux 1:d2630136d51e 15 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
samux 1:d2630136d51e 16 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
samux 1:d2630136d51e 17 */
samux 1:d2630136d51e 18
emilmont 0:6149091f755d 19 #include "MMA8451Q.h"
emilmont 0:6149091f755d 20
clemente 10:fa532bf396fb 21 #define REG_STATUS 0x00
samux 1:d2630136d51e 22 #define REG_WHO_AM_I 0x0D
samux 1:d2630136d51e 23 #define REG_CTRL_REG_1 0x2A
clemente 8:7e6013f11b10 24 #define REG_CTRL_REG_2 0x2B
clemente 5:695063448f2a 25 #define REG_CTRL_REG_4 0x2D
clemente 5:695063448f2a 26 #define REG_CTRL_REG_5 0x2E
clemente 5:695063448f2a 27 #define REG_INT_SRC 0x0C
clemente 5:695063448f2a 28 #define REG_FF_MT_CFG 0x15
clemente 5:695063448f2a 29 #define REG_FF_MT_SRC 0x16
clemente 5:695063448f2a 30 #define REG_FF_MT_THS 0x17
clemente 5:695063448f2a 31 #define REG_FF_MT_CNT 0x18
clemente 6:c52175d13e0a 32 #define REG_DBCNTM 0x11
clemente 6:c52175d13e0a 33 #define REG_DBNCE 0x12
clemente 6:c52175d13e0a 34 #define REG_BKFR 0x13
clemente 6:c52175d13e0a 35 #define REG_P_L_THS 0x14
clemente 7:ba0016258d5d 36 #define REG_PL_STATUS 0x10
clemente 7:ba0016258d5d 37
clemente 5:695063448f2a 38 //
emilmont 0:6149091f755d 39 #define REG_OUT_X_MSB 0x01
emilmont 0:6149091f755d 40 #define REG_OUT_Y_MSB 0x03
emilmont 0:6149091f755d 41 #define REG_OUT_Z_MSB 0x05
emilmont 0:6149091f755d 42
samux 1:d2630136d51e 43 #define UINT14_MAX 16383
emilmont 0:6149091f755d 44
clemente 10:fa532bf396fb 45 //
clemente 10:fa532bf396fb 46 #define ZYXDR 0x08
clemente 10:fa532bf396fb 47 #define ZDR 0x04
clemente 10:fa532bf396fb 48 #define YDR 0x02
clemente 10:fa532bf396fb 49 #define XDR 0x01
clemente 10:fa532bf396fb 50
clemente 7:ba0016258d5d 51 /** Interrupt schema
clemente 8:7e6013f11b10 52 *
clemente 8:7e6013f11b10 53 * :: The FreeFall and Motion detection share the same IRQ2.
clemente 8:7e6013f11b10 54 *
clemente 8:7e6013f11b10 55 * FreeFall --+ +-- Fall_IRQ -----+
clemente 8:7e6013f11b10 56 * \ / \
clemente 11:13e2af71e2cf 57 * +-- MMA8451Q_Int2.fall ---+ +--- MMA8451Q_usr2_fptr
clemente 8:7e6013f11b10 58 * / \ /
clemente 8:7e6013f11b10 59 * Motion ----+ +-- Motion_IRQ ---+
clemente 8:7e6013f11b10 60 *
clemente 8:7e6013f11b10 61 * :: The Orientation Detect use the IRQ1
clemente 8:7e6013f11b10 62 *
clemente 11:13e2af71e2cf 63 * Orientation Detect -- MMA8451Q_Int1.fall --- Orientation_IRQ --- MMA8451Q_usr1_fptr
clemente 8:7e6013f11b10 64 *
clemente 9:2aa9b1668d14 65 *
clemente 9:2aa9b1668d14 66 * :: The data ready use the IRQ2
clemente 9:2aa9b1668d14 67 *
clemente 9:2aa9b1668d14 68 * Data Ready -- MMA8451Q_Int2.fall --- DataReady_IRQ --- usr2_fptr
clemente 9:2aa9b1668d14 69 *
clemente 8:7e6013f11b10 70 */
clemente 11:13e2af71e2cf 71 void (*MMA8451Q_usr2_fptr)(void); // Pointers to user function called after
clemente 11:13e2af71e2cf 72 void (*MMA8451Q_usr1_fptr)(void); // IRQ assertion.
clemente 5:695063448f2a 73
clemente 5:695063448f2a 74 //
clemente 8:7e6013f11b10 75 InterruptIn MMA8451Q_Int1( PTA14); // INT1
clemente 8:7e6013f11b10 76 InterruptIn MMA8451Q_Int2( PTA15); // INT2
clemente 5:695063448f2a 77
emilmont 0:6149091f755d 78 MMA8451Q::MMA8451Q(PinName sda, PinName scl, int addr) : m_i2c(sda, scl), m_addr(addr) {
clemente 8:7e6013f11b10 79
clemente 8:7e6013f11b10 80 MMA8451Q_Int1.fall( NULL);
clemente 8:7e6013f11b10 81 MMA8451Q_Int2.fall( NULL);
clemente 11:13e2af71e2cf 82 MMA8451Q_usr2_fptr = NULL;
clemente 11:13e2af71e2cf 83 MMA8451Q_usr1_fptr = NULL;
clemente 8:7e6013f11b10 84
clemente 8:7e6013f11b10 85 Reset();
clemente 8:7e6013f11b10 86 Active();
emilmont 0:6149091f755d 87 }
emilmont 0:6149091f755d 88
clemente 5:695063448f2a 89 MMA8451Q::~MMA8451Q()
clemente 5:695063448f2a 90 {
clemente 5:695063448f2a 91 MMA8451Q_Int1.fall( NULL);
clemente 5:695063448f2a 92 MMA8451Q_Int2.fall( NULL);
clemente 11:13e2af71e2cf 93 MMA8451Q_usr2_fptr = NULL;
clemente 11:13e2af71e2cf 94 MMA8451Q_usr1_fptr = NULL;
clemente 5:695063448f2a 95 }
clemente 5:695063448f2a 96
clemente 8:7e6013f11b10 97 void MMA8451Q::Reset( void)
clemente 5:695063448f2a 98 {
clemente 8:7e6013f11b10 99 // Soft reset
clemente 8:7e6013f11b10 100 uint8_t data[2] = {REG_CTRL_REG_2, 0x40};
clemente 8:7e6013f11b10 101 writeRegs(data, 2);
clemente 8:7e6013f11b10 102 wait( 0.1);
clemente 8:7e6013f11b10 103 }
clemente 8:7e6013f11b10 104
clemente 8:7e6013f11b10 105 void MMA8451Q::FreeFallDetection( void(*fptr)(void))
clemente 8:7e6013f11b10 106 {
clemente 8:7e6013f11b10 107 // Soft Reset
clemente 8:7e6013f11b10 108 Reset();
clemente 8:7e6013f11b10 109
clemente 5:695063448f2a 110 // Example Steps for Configuring Linear Freefall Detection
clemente 5:695063448f2a 111 // X AND Y AND Z < 0.2g using MFF Function, 50 Hz ODR
clemente 5:695063448f2a 112 // Step 1: Put the device in Standby Mode: Register 0x2A CTRL_REG1
clemente 5:695063448f2a 113 unsigned char data[2] = {REG_CTRL_REG_1, 0x20};
clemente 5:695063448f2a 114 writeRegs(data, 2);
clemente 5:695063448f2a 115
clemente 5:695063448f2a 116 // Step 2: Configuration Register set for Freefall Detection enabling “AND” condition, OAE = 0, Enabling X,
clemente 5:695063448f2a 117 // Y, Z and the Latch
clemente 5:695063448f2a 118 data[0] = REG_FF_MT_CFG;
clemente 5:695063448f2a 119 data[1] = 0x01;
clemente 5:695063448f2a 120 writeRegs(data, 2);
clemente 5:695063448f2a 121
clemente 5:695063448f2a 122 // Step 3: Threshold Setting Value for the resulting acceleration < 0.2g
clemente 5:695063448f2a 123 // Note: The step count is 0.063g/count
clemente 5:695063448f2a 124 // • 0.2g/0.063g = 3.17 counts //Round to 3 counts
clemente 5:695063448f2a 125 data[0] = REG_FF_MT_THS;
clemente 5:695063448f2a 126 data[1] = 0x03;
clemente 5:695063448f2a 127 writeRegs(data, 2);
clemente 5:695063448f2a 128
clemente 5:695063448f2a 129 // Step 4: Set the debounce counter to eliminate false positive readings for 50Hz sample rate with a
clemente 5:695063448f2a 130 // requirement of 120 ms timer, assuming Normal Mode.
clemente 5:695063448f2a 131 // Note: 120 ms/20 ms (steps) = 6 counts
clemente 5:695063448f2a 132 data[0] = REG_FF_MT_CNT;
clemente 5:695063448f2a 133 data[1] = 0x06;
clemente 5:695063448f2a 134 writeRegs(data, 2);
clemente 5:695063448f2a 135
clemente 5:695063448f2a 136 // Step 5: Enable Motion/Freefall Interrupt Function in the System (CTRL_REG4)
clemente 5:695063448f2a 137 data[0] = REG_CTRL_REG_4;
clemente 5:695063448f2a 138 data[1] = 0x04;
clemente 5:695063448f2a 139 writeRegs(data, 2);
clemente 5:695063448f2a 140
clemente 5:695063448f2a 141 // Step 6: Route the Motion/Freefall Interrupt Function to INT2 hardware pin (CTRL_REG5)
clemente 5:695063448f2a 142 data[0] = REG_CTRL_REG_5;
clemente 5:695063448f2a 143 data[1] = 0x00;
clemente 5:695063448f2a 144 writeRegs(data, 2);
clemente 5:695063448f2a 145
clemente 5:695063448f2a 146 // Step 7: Put the device in Active Mode, 50 Hz
clemente 5:695063448f2a 147 data[0] = REG_CTRL_REG_1;
clemente 5:695063448f2a 148 data[1] = 0x21;
clemente 5:695063448f2a 149 writeRegs(data, 2);
clemente 5:695063448f2a 150
clemente 11:13e2af71e2cf 151 MMA8451Q_usr2_fptr = fptr;
clemente 5:695063448f2a 152 MMA8451Q_Int2.fall( this, &MMA8451Q::Fall_IRQ);
clemente 5:695063448f2a 153 }
clemente 5:695063448f2a 154
clemente 5:695063448f2a 155 void MMA8451Q::Fall_IRQ( void)
clemente 5:695063448f2a 156 {
clemente 5:695063448f2a 157 unsigned char t;
clemente 5:695063448f2a 158
clemente 5:695063448f2a 159 // Determine source of the interrupt by first reading the system interrupt
clemente 5:695063448f2a 160 readRegs( REG_INT_SRC, &t, 1);
clemente 5:695063448f2a 161 //
clemente 5:695063448f2a 162 if ( (t & 0x04) == 0x04) {
clemente 5:695063448f2a 163 // Read the Motion/Freefall Function to clear the interrupt
clemente 5:695063448f2a 164 readRegs( REG_FF_MT_SRC, &t, 1);
clemente 5:695063448f2a 165 // Run the user supplied function
clemente 11:13e2af71e2cf 166 MMA8451Q_usr2_fptr();
clemente 5:695063448f2a 167 }
clemente 5:695063448f2a 168 }
clemente 5:695063448f2a 169
clemente 5:695063448f2a 170 void MMA8451Q::MotionDetection( void(*fptr)(void))
clemente 5:695063448f2a 171 {
clemente 8:7e6013f11b10 172 // Soft Reset
clemente 8:7e6013f11b10 173 Reset();
clemente 8:7e6013f11b10 174
clemente 5:695063448f2a 175 // 6.1 Example Steps for Configuring Motion Detection
clemente 5:695063448f2a 176 // X or Y > 3g using MFF Function 4g, 100 Hz ODR, Normal Mode
clemente 5:695063448f2a 177 // Step 1: Put the device into Standby Mode: Register 0x2A CTRL_REG1
clemente 5:695063448f2a 178 unsigned char data[2] = {REG_CTRL_REG_1, 0x18}; // Set the device in 100 Hz ODR, Standby
clemente 5:695063448f2a 179 writeRegs(data, 2);
clemente 5:695063448f2a 180
clemente 5:695063448f2a 181
clemente 5:695063448f2a 182 // Step 2: Set Configuration Register for Motion Detection by setting the “OR” condition OAE = 1, enabling
clemente 5:695063448f2a 183 // X, Y, and the latch
clemente 5:695063448f2a 184 data[0] = REG_FF_MT_CFG;
clemente 5:695063448f2a 185 data[1] = 0xD8;
clemente 5:695063448f2a 186 writeRegs(data, 2);
clemente 5:695063448f2a 187
clemente 5:695063448f2a 188 // Step 3: Threshold Setting Value for the Motion detection of > 2g
clemente 5:695063448f2a 189 // Note: The step count is 0.063g/ count
clemente 8:7e6013f11b10 190 // • 1g/0.063g = 15.8; //Round up to 16
clemente 5:695063448f2a 191 data[0] = REG_FF_MT_THS;
clemente 8:7e6013f11b10 192 data[1] = 0x10;
clemente 5:695063448f2a 193 writeRegs(data, 2);
clemente 5:695063448f2a 194
clemente 5:695063448f2a 195 // Step 4: Set the debounce counter to eliminate false readings for 100 Hz sample rate with a requirement
clemente 5:695063448f2a 196 // of 100 ms timer.
clemente 5:695063448f2a 197 // Note: 100 ms/10 ms (steps) = 10 counts
clemente 5:695063448f2a 198 data[0] = REG_FF_MT_CNT;
clemente 5:695063448f2a 199 data[1] = 0x0A;
clemente 5:695063448f2a 200 writeRegs(data, 2);
clemente 5:695063448f2a 201
clemente 5:695063448f2a 202 // Step 5: Enable Motion/Freefall Interrupt Function in the System (CTRL_REG4)
clemente 5:695063448f2a 203 data[0] = REG_CTRL_REG_4;
clemente 5:695063448f2a 204 data[1] = 0x04;
clemente 5:695063448f2a 205 writeRegs(data, 2);
clemente 5:695063448f2a 206
clemente 7:ba0016258d5d 207 // Step 6: Route the Motion/Freefall Interrupt Function to INT2 hardware pin (CTRL_REG5)
clemente 5:695063448f2a 208 data[0] = REG_CTRL_REG_5;
clemente 7:ba0016258d5d 209 data[1] = 0x00;
clemente 5:695063448f2a 210 writeRegs(data, 2);
clemente 5:695063448f2a 211
clemente 5:695063448f2a 212 // Step 7: Put the device in Active Mode
clemente 5:695063448f2a 213 data[0] = REG_CTRL_REG_1;
clemente 5:695063448f2a 214 data[1] = 0x19;
clemente 5:695063448f2a 215 writeRegs(data, 2);
clemente 5:695063448f2a 216
clemente 11:13e2af71e2cf 217 MMA8451Q_usr2_fptr = fptr;
clemente 7:ba0016258d5d 218 MMA8451Q_Int2.fall( this, &MMA8451Q::Motion_IRQ);
clemente 5:695063448f2a 219
clemente 5:695063448f2a 220 }
clemente 5:695063448f2a 221
clemente 5:695063448f2a 222 void MMA8451Q::Motion_IRQ( void)
clemente 5:695063448f2a 223 {
clemente 5:695063448f2a 224 unsigned char t;
clemente 5:695063448f2a 225
clemente 5:695063448f2a 226 // Determine source of the interrupt by first reading the system interrupt
clemente 5:695063448f2a 227 readRegs( REG_INT_SRC, &t, 1);
clemente 5:695063448f2a 228 //
clemente 5:695063448f2a 229 if ( (t & 0x04) == 0x04) {
clemente 5:695063448f2a 230 // Read the Motion/Freefall Function to clear the interrupt
clemente 5:695063448f2a 231 readRegs( REG_FF_MT_SRC, &t, 1);
clemente 5:695063448f2a 232 // Run the user supplied function
clemente 11:13e2af71e2cf 233 MMA8451Q_usr2_fptr();
clemente 5:695063448f2a 234 }
clemente 5:695063448f2a 235 }
clemente 5:695063448f2a 236
clemente 7:ba0016258d5d 237 void MMA8451Q::OrientationDetect( void(*fptr)(void))
clemente 6:c52175d13e0a 238 {
clemente 7:ba0016258d5d 239 OrientationDetect( fptr, Z_LOCKOUT_14, Z_BKFR_80, PL_THS_15, PL_HYS_0);
clemente 6:c52175d13e0a 240 }
clemente 6:c52175d13e0a 241
clemente 7:ba0016258d5d 242 void MMA8451Q::OrientationDetect( void(*fptr)(void), unsigned int Z_LockOut, unsigned int Z_BkFr, unsigned int PL_Thsld, unsigned int PL_Hyst)
clemente 6:c52175d13e0a 243 {
clemente 6:c52175d13e0a 244 unsigned char t;
clemente 8:7e6013f11b10 245
clemente 8:7e6013f11b10 246 // Soft Reset
clemente 8:7e6013f11b10 247 Reset();
clemente 8:7e6013f11b10 248
clemente 8:7e6013f11b10 249 // Reset orientation value.
clemente 8:7e6013f11b10 250 OrientationState = 0;
clemente 8:7e6013f11b10 251 OrientationStateUpdated = 0;
clemente 6:c52175d13e0a 252
clemente 6:c52175d13e0a 253 // Step 1: Put the part into Standby Mode
clemente 6:c52175d13e0a 254 Standby();
clemente 6:c52175d13e0a 255
clemente 6:c52175d13e0a 256 // Step 2: Set the data rate to 50 Hz (for example, but can choose any sample rate).
clemente 6:c52175d13e0a 257 readRegs( REG_CTRL_REG_1, &t, 1); // Note: Can combine this step with above
clemente 6:c52175d13e0a 258 t &= 0xC7; // Clear the sample rate bits
clemente 6:c52175d13e0a 259 t |= 0x20; // Set the sample rate bits to 50 Hz
clemente 6:c52175d13e0a 260 unsigned char data[2] = {REG_CTRL_REG_1, t};
clemente 6:c52175d13e0a 261 writeRegs(data, 2); // Write updated value into the register.
clemente 6:c52175d13e0a 262
clemente 6:c52175d13e0a 263
clemente 6:c52175d13e0a 264 // Step 3: Set the PL_EN bit in Register 0x11 PL_CFG. This will enable the orientation detection.
clemente 6:c52175d13e0a 265 readRegs( REG_DBCNTM, &t, 1);
clemente 6:c52175d13e0a 266 data[0] = REG_DBCNTM;
clemente 6:c52175d13e0a 267 data[1] = t | 0x40;
clemente 6:c52175d13e0a 268 writeRegs(data, 2);
clemente 6:c52175d13e0a 269
clemente 6:c52175d13e0a 270 // Step 4: Set the Back/Front Angle trip points in register 0x13 following the table in the data sheet.
clemente 6:c52175d13e0a 271 // NOTE: This register is readable in all versions of MMA845xQ but it is only modifiable in the
clemente 6:c52175d13e0a 272 // MMA8451Q.
clemente 6:c52175d13e0a 273 readRegs( REG_BKFR, &t, 1);
clemente 6:c52175d13e0a 274 t &= 0x3F; // Clear bit 7 and 6
clemente 6:c52175d13e0a 275 data[0] = REG_BKFR;
clemente 6:c52175d13e0a 276 data[1] = t | Z_BkFr;
clemente 6:c52175d13e0a 277 writeRegs(data, 2); // Write in the updated Back/Front Angle
clemente 6:c52175d13e0a 278
clemente 6:c52175d13e0a 279 // Step 5: Set the Z-Lockout angle trip point in register 0x13 following the table in the data sheet.
clemente 6:c52175d13e0a 280 // NOTE: This register is readable in all versions of MMA845xQ but it is only modifiable in the
clemente 6:c52175d13e0a 281 // MMA8451Q.
clemente 6:c52175d13e0a 282 readRegs( REG_BKFR, &t, 1);
clemente 6:c52175d13e0a 283 t &= 0xF8; // Clear the last three bits of the register
clemente 6:c52175d13e0a 284 data[0] = REG_BKFR;
clemente 6:c52175d13e0a 285 data[1] = t | Z_LockOut;
clemente 6:c52175d13e0a 286 writeRegs(data, 2); // Write in the updated Z-lockout angle
clemente 6:c52175d13e0a 287
clemente 6:c52175d13e0a 288 // Step 6: Set the Trip Threshold Angle
clemente 6:c52175d13e0a 289 // NOTE: This register is readable in all versions of MMA845xQ but it is only modifiable in the
clemente 6:c52175d13e0a 290 // MMA8451Q.
clemente 6:c52175d13e0a 291 // Select the angle desired in the table, and,
clemente 6:c52175d13e0a 292 // Enter in the values given in the table for the corresponding angle.
clemente 6:c52175d13e0a 293 // Refer to Figure 7 for the reference frame of the trip angles.
clemente 6:c52175d13e0a 294 readRegs( REG_P_L_THS, &t, 1);
clemente 6:c52175d13e0a 295 t &= 0x07; // Clear the Threshold values
clemente 6:c52175d13e0a 296 data[0] = REG_P_L_THS;
clemente 6:c52175d13e0a 297 data[1] = t | (PL_Thsld<<3);
clemente 6:c52175d13e0a 298 writeRegs(data, 2);
clemente 6:c52175d13e0a 299
clemente 6:c52175d13e0a 300 // Step 7: Set the Hysteresis Angle
clemente 6:c52175d13e0a 301 // NOTE: This register is readable in all versions of MMA845xQ but it is only modifiable in the
clemente 6:c52175d13e0a 302 // MMA8451Q.
clemente 6:c52175d13e0a 303 // Select the hysteresis value based on the desired final trip points (threshold + hysteresis)
clemente 6:c52175d13e0a 304 // Enter in the values given in the table for that corresponding angle.
clemente 6:c52175d13e0a 305 // Note: Care must be taken. Review the final resulting angles. Make sure there isn’t a resulting trip value
clemente 6:c52175d13e0a 306 // greater than 90 or less than 0.
clemente 6:c52175d13e0a 307 // The following are the options for setting the hysteresis.
clemente 6:c52175d13e0a 308 readRegs( REG_P_L_THS, &t, 1);
clemente 6:c52175d13e0a 309 t &= 0xF8; // Clear the Hysteresis values
clemente 6:c52175d13e0a 310 data[0] = REG_P_L_THS;
clemente 6:c52175d13e0a 311 data[1] = t | PL_Hyst;
clemente 6:c52175d13e0a 312 writeRegs(data, 2);
clemente 6:c52175d13e0a 313
clemente 6:c52175d13e0a 314 // Step 8: Register 0x2D, Control Register 4 configures all embedded features for interrupt
clemente 6:c52175d13e0a 315 // detection.
clemente 6:c52175d13e0a 316 // To set this device up to run an interrupt service routine:
clemente 6:c52175d13e0a 317 // Program the Orientation Detection bit in Control Register 4.
clemente 6:c52175d13e0a 318 // Set bit 4 to enable the orientation detection “INT_EN_LNDPRT”.
clemente 6:c52175d13e0a 319 readRegs( REG_CTRL_REG_4, &t, 1);
clemente 6:c52175d13e0a 320 data[0] = REG_CTRL_REG_4;
clemente 6:c52175d13e0a 321 data[1] = t | 0x10; // Set bit 4
clemente 6:c52175d13e0a 322 writeRegs(data, 2);
clemente 6:c52175d13e0a 323
clemente 6:c52175d13e0a 324 // Step 9: Register 0x2E is Control Register 5 which gives the option of routing the interrupt to
clemente 6:c52175d13e0a 325 // either INT1 or INT2
clemente 6:c52175d13e0a 326 // Depending on which interrupt pin is enabled and configured to the processor:
clemente 6:c52175d13e0a 327 // Set bit 4 “INT_CFG_LNDPRT” to configure INT1, or,
clemente 6:c52175d13e0a 328 // Leave the bit clear to configure INT2.
clemente 6:c52175d13e0a 329 readRegs( REG_CTRL_REG_5, &t, 1);
clemente 6:c52175d13e0a 330 data[0] = REG_CTRL_REG_5;
clemente 6:c52175d13e0a 331 data[1] = t | 0x10; // Set bit 4 to choose the interrupt to route to INT1
clemente 6:c52175d13e0a 332 writeRegs(data, 2);
clemente 6:c52175d13e0a 333
clemente 6:c52175d13e0a 334 // Step 10: Set the debounce counter in register 0x12
clemente 6:c52175d13e0a 335 // This value will scale depending on the application-specific required ODR.
clemente 6:c52175d13e0a 336 // If the device is set to go to sleep, reset the debounce counter before the device goes to sleep. This setting
clemente 6:c52175d13e0a 337 // helps avoid long delays since the debounce will always scale with the current sample rate. The debounce
clemente 6:c52175d13e0a 338 // can be set between 50 ms - 100 ms to avoid long delays.
clemente 6:c52175d13e0a 339 data[0] = REG_DBNCE;
clemente 6:c52175d13e0a 340 data[1] = 0x05; // This sets the debounce counter to 100 ms at 50 Hz
clemente 6:c52175d13e0a 341 writeRegs(data, 2);
clemente 6:c52175d13e0a 342
clemente 6:c52175d13e0a 343 // Step 11: Put the device in Active Mode
clemente 6:c52175d13e0a 344 Active();
clemente 7:ba0016258d5d 345
clemente 11:13e2af71e2cf 346 MMA8451Q_usr1_fptr = fptr;
clemente 7:ba0016258d5d 347 MMA8451Q_Int1.fall( this, &MMA8451Q::Orientation_IRQ);
clemente 7:ba0016258d5d 348
clemente 7:ba0016258d5d 349 }
clemente 7:ba0016258d5d 350
clemente 7:ba0016258d5d 351 void MMA8451Q::Orientation_IRQ( void)
clemente 7:ba0016258d5d 352 {
clemente 7:ba0016258d5d 353 unsigned char t;
clemente 6:c52175d13e0a 354
clemente 7:ba0016258d5d 355 // Determine source of the interrupt by first reading the system interrupt
clemente 7:ba0016258d5d 356 readRegs( REG_INT_SRC, &t, 1);
clemente 7:ba0016258d5d 357 //
clemente 7:ba0016258d5d 358 if ( (t & 0x10) == 0x10) {
clemente 7:ba0016258d5d 359 // Read the PL State from the Status Register, clear the interrupt
clemente 7:ba0016258d5d 360 readRegs( REG_PL_STATUS, &t, 1);
clemente 8:7e6013f11b10 361 // Set the orientation state variable
clemente 8:7e6013f11b10 362 OrientationState = t;
clemente 8:7e6013f11b10 363 OrientationStateUpdated = 1;
clemente 7:ba0016258d5d 364 // Run the user supplied function
clemente 11:13e2af71e2cf 365 MMA8451Q_usr1_fptr();
clemente 7:ba0016258d5d 366 }
clemente 6:c52175d13e0a 367 }
clemente 6:c52175d13e0a 368
clemente 8:7e6013f11b10 369 unsigned char MMA8451Q::GetOrientationState( void)
clemente 8:7e6013f11b10 370 {
clemente 8:7e6013f11b10 371 if ( OrientationStateUpdated) {
clemente 8:7e6013f11b10 372 OrientationStateUpdated = 0;
clemente 8:7e6013f11b10 373 return OrientationState;
clemente 8:7e6013f11b10 374 }
clemente 8:7e6013f11b10 375 //
clemente 8:7e6013f11b10 376 return 0;
clemente 8:7e6013f11b10 377 }
clemente 8:7e6013f11b10 378
clemente 9:2aa9b1668d14 379 void MMA8451Q::DataReady( void(*fptr)(void), unsigned char ODR)
clemente 9:2aa9b1668d14 380 {
clemente 9:2aa9b1668d14 381 // Soft Reset
clemente 9:2aa9b1668d14 382 Reset();
clemente 9:2aa9b1668d14 383
clemente 9:2aa9b1668d14 384 // Step 1: Put the device into Standby Mode: Register 0x2A CTRL_REG1
clemente 9:2aa9b1668d14 385 // Set the device ODR value and Standby
clemente 9:2aa9b1668d14 386 unsigned char data[2] = {REG_CTRL_REG_1, ((ODR<<3) & 0xFE)};
clemente 9:2aa9b1668d14 387 writeRegs(data, 2);
clemente 9:2aa9b1668d14 388
clemente 9:2aa9b1668d14 389 // Step 2: Enable Data Ready Interrupt Function in the System (CTRL_REG4)
clemente 9:2aa9b1668d14 390 data[0] = REG_CTRL_REG_4;
clemente 9:2aa9b1668d14 391 data[1] = 0x01;
clemente 9:2aa9b1668d14 392 writeRegs(data, 2);
clemente 9:2aa9b1668d14 393
clemente 9:2aa9b1668d14 394 // Step 6: Route the Data Ready Interrupt Function to INT2 hardware pin (CTRL_REG5)
clemente 9:2aa9b1668d14 395 data[0] = REG_CTRL_REG_5;
clemente 9:2aa9b1668d14 396 data[1] = 0x00;
clemente 9:2aa9b1668d14 397 writeRegs(data, 2);
clemente 9:2aa9b1668d14 398
clemente 9:2aa9b1668d14 399 // Step 7: Put the device in Active Mode
clemente 9:2aa9b1668d14 400 data[0] = REG_CTRL_REG_1;
clemente 9:2aa9b1668d14 401 data[1] = ((ODR<<3) | 0x01);
clemente 9:2aa9b1668d14 402 writeRegs(data, 2);
clemente 9:2aa9b1668d14 403
clemente 11:13e2af71e2cf 404 MMA8451Q_usr2_fptr = fptr;
clemente 9:2aa9b1668d14 405 MMA8451Q_Int2.fall( this, &MMA8451Q::DataReady_IRQ);
clemente 9:2aa9b1668d14 406
clemente 9:2aa9b1668d14 407 }
clemente 9:2aa9b1668d14 408
clemente 9:2aa9b1668d14 409 void MMA8451Q::DataReady_IRQ( void)
clemente 9:2aa9b1668d14 410 {
clemente 9:2aa9b1668d14 411 unsigned char t;
clemente 9:2aa9b1668d14 412
clemente 9:2aa9b1668d14 413 // Determine source of the interrupt by first reading the system interrupt
clemente 9:2aa9b1668d14 414 readRegs( REG_INT_SRC, &t, 1);
clemente 9:2aa9b1668d14 415 //
clemente 9:2aa9b1668d14 416 if ( (t & 0x01) == 0x01) {
clemente 9:2aa9b1668d14 417 // Read the DataReady_IRQ Function to clear the interrupt
clemente 9:2aa9b1668d14 418 readRegs( REG_FF_MT_SRC, &t, 1);
clemente 9:2aa9b1668d14 419 // Run the user supplied function
clemente 11:13e2af71e2cf 420 MMA8451Q_usr2_fptr();
clemente 9:2aa9b1668d14 421 }
clemente 9:2aa9b1668d14 422 }
clemente 9:2aa9b1668d14 423
clemente 9:2aa9b1668d14 424
clemente 5:695063448f2a 425 void MMA8451Q::Active( void)
clemente 5:695063448f2a 426 {
clemente 5:695063448f2a 427 unsigned char t;
clemente 5:695063448f2a 428
clemente 5:695063448f2a 429 // Activate the peripheral
clemente 5:695063448f2a 430 readRegs(REG_CTRL_REG_1, &t, 1);
clemente 5:695063448f2a 431 unsigned char data[2] = {REG_CTRL_REG_1, t|0x01};
clemente 5:695063448f2a 432 writeRegs(data, 2);
clemente 5:695063448f2a 433 }
clemente 5:695063448f2a 434
clemente 5:695063448f2a 435 void MMA8451Q::Standby( void)
clemente 5:695063448f2a 436 {
clemente 5:695063448f2a 437 unsigned char t;
clemente 5:695063448f2a 438
clemente 5:695063448f2a 439 // Standby
clemente 5:695063448f2a 440 readRegs(REG_CTRL_REG_1, &t, 1);
clemente 5:695063448f2a 441 unsigned char data[2] = {REG_CTRL_REG_1, t&0xFE};
clemente 5:695063448f2a 442 writeRegs(data, 2);
clemente 5:695063448f2a 443 }
emilmont 0:6149091f755d 444
emilmont 0:6149091f755d 445 uint8_t MMA8451Q::getWhoAmI() {
emilmont 0:6149091f755d 446 uint8_t who_am_i = 0;
samux 1:d2630136d51e 447 readRegs(REG_WHO_AM_I, &who_am_i, 1);
emilmont 0:6149091f755d 448 return who_am_i;
emilmont 0:6149091f755d 449 }
emilmont 0:6149091f755d 450
chris 3:db7126dbd63f 451 float MMA8451Q::getAccX() {
chris 3:db7126dbd63f 452 return (float(getAccAxis(REG_OUT_X_MSB))/4096.0);
emilmont 0:6149091f755d 453 }
emilmont 0:6149091f755d 454
chris 3:db7126dbd63f 455 float MMA8451Q::getAccY() {
chris 3:db7126dbd63f 456 return (float(getAccAxis(REG_OUT_Y_MSB))/4096.0);
emilmont 0:6149091f755d 457 }
emilmont 0:6149091f755d 458
chris 3:db7126dbd63f 459 float MMA8451Q::getAccZ() {
chris 3:db7126dbd63f 460 return (float(getAccAxis(REG_OUT_Z_MSB))/4096.0);
emilmont 0:6149091f755d 461 }
emilmont 0:6149091f755d 462
chris 3:db7126dbd63f 463 void MMA8451Q::getAccAllAxis(float * res) {
emilmont 0:6149091f755d 464 res[0] = getAccX();
emilmont 0:6149091f755d 465 res[1] = getAccY();
emilmont 0:6149091f755d 466 res[2] = getAccZ();
emilmont 0:6149091f755d 467 }
emilmont 0:6149091f755d 468
emilmont 0:6149091f755d 469 int16_t MMA8451Q::getAccAxis(uint8_t addr) {
emilmont 0:6149091f755d 470 int16_t acc;
emilmont 0:6149091f755d 471 uint8_t res[2];
samux 1:d2630136d51e 472 readRegs(addr, res, 2);
emilmont 0:6149091f755d 473
emilmont 0:6149091f755d 474 acc = (res[0] << 6) | (res[1] >> 2);
emilmont 0:6149091f755d 475 if (acc > UINT14_MAX/2)
emilmont 0:6149091f755d 476 acc -= UINT14_MAX;
emilmont 0:6149091f755d 477
emilmont 0:6149091f755d 478 return acc;
emilmont 0:6149091f755d 479 }
emilmont 0:6149091f755d 480
clemente 10:fa532bf396fb 481 unsigned int MMA8451Q::getAccRawAllAxis( int16_t * res)
clemente 10:fa532bf396fb 482 {
clemente 10:fa532bf396fb 483 if ( isDataAvailable() & ZYXDR)
clemente 10:fa532bf396fb 484 {
clemente 10:fa532bf396fb 485 getAccRawX( &res[0]);
clemente 10:fa532bf396fb 486 getAccRawY( &res[1]);
clemente 10:fa532bf396fb 487 getAccRawZ( &res[2]);
clemente 10:fa532bf396fb 488 return 1;
clemente 10:fa532bf396fb 489 } else
clemente 10:fa532bf396fb 490 return 0;
clemente 10:fa532bf396fb 491 }
clemente 10:fa532bf396fb 492
clemente 10:fa532bf396fb 493 int16_t MMA8451Q::getAccRawX( int16_t * res)
clemente 10:fa532bf396fb 494 {
clemente 10:fa532bf396fb 495 if ( isDataAvailable() & XDR)
clemente 10:fa532bf396fb 496 {
clemente 10:fa532bf396fb 497 *res = getAccAxis(REG_OUT_X_MSB);
clemente 10:fa532bf396fb 498 return 1;
clemente 10:fa532bf396fb 499 } else
clemente 10:fa532bf396fb 500 return 0;
clemente 10:fa532bf396fb 501 }
clemente 10:fa532bf396fb 502
clemente 10:fa532bf396fb 503 int16_t MMA8451Q::getAccRawY( int16_t * res)
clemente 10:fa532bf396fb 504 {
clemente 10:fa532bf396fb 505 if ( isDataAvailable() & YDR)
clemente 10:fa532bf396fb 506 {
clemente 10:fa532bf396fb 507 *res = getAccAxis(REG_OUT_Y_MSB);
clemente 10:fa532bf396fb 508 return 1;
clemente 10:fa532bf396fb 509 } else
clemente 10:fa532bf396fb 510 return 0;
clemente 10:fa532bf396fb 511 }
clemente 10:fa532bf396fb 512
clemente 10:fa532bf396fb 513 int16_t MMA8451Q::getAccRawZ( int16_t * res)
clemente 10:fa532bf396fb 514 {
clemente 10:fa532bf396fb 515 if ( isDataAvailable() & ZDR)
clemente 10:fa532bf396fb 516 {
clemente 10:fa532bf396fb 517 *res = getAccAxis(REG_OUT_Z_MSB);
clemente 10:fa532bf396fb 518 return 1;
clemente 10:fa532bf396fb 519 } else
clemente 10:fa532bf396fb 520 return 0;
clemente 10:fa532bf396fb 521 }
clemente 10:fa532bf396fb 522
clemente 10:fa532bf396fb 523 unsigned int MMA8451Q::isDataAvailable( void)
clemente 10:fa532bf396fb 524 {
clemente 10:fa532bf396fb 525 unsigned char status;
clemente 10:fa532bf396fb 526
clemente 10:fa532bf396fb 527 readRegs( REG_STATUS, &status, 1);
clemente 10:fa532bf396fb 528
clemente 10:fa532bf396fb 529 return (status);
clemente 10:fa532bf396fb 530
clemente 10:fa532bf396fb 531 }
clemente 10:fa532bf396fb 532
samux 1:d2630136d51e 533 void MMA8451Q::readRegs(int addr, uint8_t * data, int len) {
emilmont 0:6149091f755d 534 char t[1] = {addr};
emilmont 0:6149091f755d 535 m_i2c.write(m_addr, t, 1, true);
emilmont 0:6149091f755d 536 m_i2c.read(m_addr, (char *)data, len);
emilmont 0:6149091f755d 537 }
emilmont 0:6149091f755d 538
samux 1:d2630136d51e 539 void MMA8451Q::writeRegs(uint8_t * data, int len) {
emilmont 0:6149091f755d 540 m_i2c.write(m_addr, (char *)data, len);
emilmont 0:6149091f755d 541 }