clemente di caprio / FRDM_MMA8451Q

Added code to manage Orientation, FreeFall and Motion Detection. Data is also available via IRQ.

Dependents:   Test_FRDM_MMA8451Q AccelTest FRDM-KL46-Template KL25Z_Demo ... more

Fork of MMA8451Q by Emilio Monti

MMA8451Q.cpp@8:7e6013f11b10, 2013-05-28 (annotated)

Committer:
clemente
Date:
Tue May 28 17:18:30 2013 +0000
Revision:
8:7e6013f11b10
Parent:
7:ba0016258d5d
Child:
9:2aa9b1668d14
Orientation tested. Freefall need some more tests.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
samux 1:d2630136d51e 1 /* Copyright (c) 2010-2011 mbed.org, MIT License
samux 1:d2630136d51e 2 *
samux 1:d2630136d51e 3 * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
samux 1:d2630136d51e 4 * and associated documentation files (the "Software"), to deal in the Software without
samux 1:d2630136d51e 5 * restriction, including without limitation the rights to use, copy, modify, merge, publish,
samux 1:d2630136d51e 6 * distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
samux 1:d2630136d51e 7 * Software is furnished to do so, subject to the following conditions:
samux 1:d2630136d51e 8 *
samux 1:d2630136d51e 9 * The above copyright notice and this permission notice shall be included in all copies or
samux 1:d2630136d51e 10 * substantial portions of the Software.
samux 1:d2630136d51e 11 *
samux 1:d2630136d51e 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
samux 1:d2630136d51e 13 * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
samux 1:d2630136d51e 14 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
samux 1:d2630136d51e 15 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
samux 1:d2630136d51e 16 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
samux 1:d2630136d51e 17 */
samux 1:d2630136d51e 18
emilmont 0:6149091f755d 19 #include "MMA8451Q.h"
emilmont 0:6149091f755d 20
samux 1:d2630136d51e 21 #define REG_WHO_AM_I 0x0D
samux 1:d2630136d51e 22 #define REG_CTRL_REG_1 0x2A
clemente 8:7e6013f11b10 23 #define REG_CTRL_REG_2 0x2B
clemente 5:695063448f2a 24 #define REG_CTRL_REG_4 0x2D
clemente 5:695063448f2a 25 #define REG_CTRL_REG_5 0x2E
clemente 5:695063448f2a 26 #define REG_INT_SRC 0x0C
clemente 5:695063448f2a 27 #define REG_FF_MT_CFG 0x15
clemente 5:695063448f2a 28 #define REG_FF_MT_SRC 0x16
clemente 5:695063448f2a 29 #define REG_FF_MT_THS 0x17
clemente 5:695063448f2a 30 #define REG_FF_MT_CNT 0x18
clemente 6:c52175d13e0a 31 #define REG_DBCNTM 0x11
clemente 6:c52175d13e0a 32 #define REG_DBNCE 0x12
clemente 6:c52175d13e0a 33 #define REG_BKFR 0x13
clemente 6:c52175d13e0a 34 #define REG_P_L_THS 0x14
clemente 7:ba0016258d5d 35 #define REG_PL_STATUS 0x10
clemente 7:ba0016258d5d 36
clemente 5:695063448f2a 37 //
emilmont 0:6149091f755d 38 #define REG_OUT_X_MSB 0x01
emilmont 0:6149091f755d 39 #define REG_OUT_Y_MSB 0x03
emilmont 0:6149091f755d 40 #define REG_OUT_Z_MSB 0x05
emilmont 0:6149091f755d 41
samux 1:d2630136d51e 42 #define UINT14_MAX 16383
emilmont 0:6149091f755d 43
clemente 7:ba0016258d5d 44 /** Interrupt schema
clemente 8:7e6013f11b10 45 *
clemente 8:7e6013f11b10 46 * :: The FreeFall and Motion detection share the same IRQ2.
clemente 8:7e6013f11b10 47 *
clemente 8:7e6013f11b10 48 * FreeFall --+ +-- Fall_IRQ -----+
clemente 8:7e6013f11b10 49 * \ / \
clemente 8:7e6013f11b10 50 * +-- MMA8451Q_Int2.fall ---+ +--- user2_fptr
clemente 8:7e6013f11b10 51 * / \ /
clemente 8:7e6013f11b10 52 * Motion ----+ +-- Motion_IRQ ---+
clemente 8:7e6013f11b10 53 *
clemente 8:7e6013f11b10 54 * :: The Orientation Detect use the IRQ1
clemente 8:7e6013f11b10 55 *
clemente 8:7e6013f11b10 56 * Orientation Detect -- MMA8451Q_Int1.fall --- Orientation_IRQ --- user1_fptr
clemente 8:7e6013f11b10 57 *
clemente 8:7e6013f11b10 58 */
clemente 8:7e6013f11b10 59 void (*user2_fptr)(void); // Pointers to user function called after
clemente 8:7e6013f11b10 60 void (*user1_fptr)(void); // IRQ assertion.
clemente 5:695063448f2a 61
clemente 5:695063448f2a 62 //
clemente 8:7e6013f11b10 63 InterruptIn MMA8451Q_Int1( PTA14); // INT1
clemente 8:7e6013f11b10 64 InterruptIn MMA8451Q_Int2( PTA15); // INT2
clemente 5:695063448f2a 65
emilmont 0:6149091f755d 66 MMA8451Q::MMA8451Q(PinName sda, PinName scl, int addr) : m_i2c(sda, scl), m_addr(addr) {
clemente 8:7e6013f11b10 67
clemente 8:7e6013f11b10 68 MMA8451Q_Int1.fall( NULL);
clemente 8:7e6013f11b10 69 MMA8451Q_Int2.fall( NULL);
clemente 8:7e6013f11b10 70 user2_fptr = NULL;
clemente 8:7e6013f11b10 71 user1_fptr = NULL;
clemente 8:7e6013f11b10 72
clemente 8:7e6013f11b10 73 Reset();
clemente 8:7e6013f11b10 74 Active();
emilmont 0:6149091f755d 75 }
emilmont 0:6149091f755d 76
clemente 5:695063448f2a 77 MMA8451Q::~MMA8451Q()
clemente 5:695063448f2a 78 {
clemente 5:695063448f2a 79 MMA8451Q_Int1.fall( NULL);
clemente 5:695063448f2a 80 MMA8451Q_Int2.fall( NULL);
clemente 7:ba0016258d5d 81 user2_fptr = NULL;
clemente 7:ba0016258d5d 82 user1_fptr = NULL;
clemente 5:695063448f2a 83 }
clemente 5:695063448f2a 84
clemente 8:7e6013f11b10 85 void MMA8451Q::Reset( void)
clemente 5:695063448f2a 86 {
clemente 8:7e6013f11b10 87 // Soft reset
clemente 8:7e6013f11b10 88 uint8_t data[2] = {REG_CTRL_REG_2, 0x40};
clemente 8:7e6013f11b10 89 writeRegs(data, 2);
clemente 8:7e6013f11b10 90 wait( 0.1);
clemente 8:7e6013f11b10 91 }
clemente 8:7e6013f11b10 92
clemente 8:7e6013f11b10 93 void MMA8451Q::FreeFallDetection( void(*fptr)(void))
clemente 8:7e6013f11b10 94 {
clemente 8:7e6013f11b10 95 // Soft Reset
clemente 8:7e6013f11b10 96 Reset();
clemente 8:7e6013f11b10 97
clemente 5:695063448f2a 98 // Example Steps for Configuring Linear Freefall Detection
clemente 5:695063448f2a 99 // X AND Y AND Z < 0.2g using MFF Function, 50 Hz ODR
clemente 5:695063448f2a 100 // Step 1: Put the device in Standby Mode: Register 0x2A CTRL_REG1
clemente 5:695063448f2a 101 unsigned char data[2] = {REG_CTRL_REG_1, 0x20};
clemente 5:695063448f2a 102 writeRegs(data, 2);
clemente 5:695063448f2a 103
clemente 5:695063448f2a 104 // Step 2: Configuration Register set for Freefall Detection enabling “AND” condition, OAE = 0, Enabling X,
clemente 5:695063448f2a 105 // Y, Z and the Latch
clemente 5:695063448f2a 106 data[0] = REG_FF_MT_CFG;
clemente 5:695063448f2a 107 data[1] = 0x01;
clemente 5:695063448f2a 108 writeRegs(data, 2);
clemente 5:695063448f2a 109
clemente 5:695063448f2a 110 // Step 3: Threshold Setting Value for the resulting acceleration < 0.2g
clemente 5:695063448f2a 111 // Note: The step count is 0.063g/count
clemente 5:695063448f2a 112 // • 0.2g/0.063g = 3.17 counts //Round to 3 counts
clemente 5:695063448f2a 113 data[0] = REG_FF_MT_THS;
clemente 5:695063448f2a 114 data[1] = 0x03;
clemente 5:695063448f2a 115 writeRegs(data, 2);
clemente 5:695063448f2a 116
clemente 5:695063448f2a 117 // Step 4: Set the debounce counter to eliminate false positive readings for 50Hz sample rate with a
clemente 5:695063448f2a 118 // requirement of 120 ms timer, assuming Normal Mode.
clemente 5:695063448f2a 119 // Note: 120 ms/20 ms (steps) = 6 counts
clemente 5:695063448f2a 120 data[0] = REG_FF_MT_CNT;
clemente 5:695063448f2a 121 data[1] = 0x06;
clemente 5:695063448f2a 122 writeRegs(data, 2);
clemente 5:695063448f2a 123
clemente 5:695063448f2a 124 // Step 5: Enable Motion/Freefall Interrupt Function in the System (CTRL_REG4)
clemente 5:695063448f2a 125 data[0] = REG_CTRL_REG_4;
clemente 5:695063448f2a 126 data[1] = 0x04;
clemente 5:695063448f2a 127 writeRegs(data, 2);
clemente 5:695063448f2a 128
clemente 5:695063448f2a 129 // Step 6: Route the Motion/Freefall Interrupt Function to INT2 hardware pin (CTRL_REG5)
clemente 5:695063448f2a 130 data[0] = REG_CTRL_REG_5;
clemente 5:695063448f2a 131 data[1] = 0x00;
clemente 5:695063448f2a 132 writeRegs(data, 2);
clemente 5:695063448f2a 133
clemente 5:695063448f2a 134 // Step 7: Put the device in Active Mode, 50 Hz
clemente 5:695063448f2a 135 data[0] = REG_CTRL_REG_1;
clemente 5:695063448f2a 136 data[1] = 0x21;
clemente 5:695063448f2a 137 writeRegs(data, 2);
clemente 5:695063448f2a 138
clemente 7:ba0016258d5d 139 user2_fptr = fptr;
clemente 5:695063448f2a 140 MMA8451Q_Int2.fall( this, &MMA8451Q::Fall_IRQ);
clemente 5:695063448f2a 141 }
clemente 5:695063448f2a 142
clemente 5:695063448f2a 143 void MMA8451Q::Fall_IRQ( void)
clemente 5:695063448f2a 144 {
clemente 5:695063448f2a 145 unsigned char t;
clemente 5:695063448f2a 146
clemente 5:695063448f2a 147 // Determine source of the interrupt by first reading the system interrupt
clemente 5:695063448f2a 148 readRegs( REG_INT_SRC, &t, 1);
clemente 5:695063448f2a 149 //
clemente 5:695063448f2a 150 if ( (t & 0x04) == 0x04) {
clemente 5:695063448f2a 151 // Read the Motion/Freefall Function to clear the interrupt
clemente 5:695063448f2a 152 readRegs( REG_FF_MT_SRC, &t, 1);
clemente 5:695063448f2a 153 // Run the user supplied function
clemente 7:ba0016258d5d 154 user2_fptr();
clemente 5:695063448f2a 155 }
clemente 5:695063448f2a 156 }
clemente 5:695063448f2a 157
clemente 5:695063448f2a 158 void MMA8451Q::MotionDetection( void(*fptr)(void))
clemente 5:695063448f2a 159 {
clemente 8:7e6013f11b10 160 // Soft Reset
clemente 8:7e6013f11b10 161 Reset();
clemente 8:7e6013f11b10 162
clemente 5:695063448f2a 163 // 6.1 Example Steps for Configuring Motion Detection
clemente 5:695063448f2a 164 // X or Y > 3g using MFF Function 4g, 100 Hz ODR, Normal Mode
clemente 5:695063448f2a 165 // Step 1: Put the device into Standby Mode: Register 0x2A CTRL_REG1
clemente 5:695063448f2a 166 unsigned char data[2] = {REG_CTRL_REG_1, 0x18}; // Set the device in 100 Hz ODR, Standby
clemente 5:695063448f2a 167 writeRegs(data, 2);
clemente 5:695063448f2a 168
clemente 5:695063448f2a 169
clemente 5:695063448f2a 170 // Step 2: Set Configuration Register for Motion Detection by setting the “OR” condition OAE = 1, enabling
clemente 5:695063448f2a 171 // X, Y, and the latch
clemente 5:695063448f2a 172 data[0] = REG_FF_MT_CFG;
clemente 5:695063448f2a 173 data[1] = 0xD8;
clemente 5:695063448f2a 174 writeRegs(data, 2);
clemente 5:695063448f2a 175
clemente 5:695063448f2a 176 // Step 3: Threshold Setting Value for the Motion detection of > 2g
clemente 5:695063448f2a 177 // Note: The step count is 0.063g/ count
clemente 8:7e6013f11b10 178 // • 1g/0.063g = 15.8; //Round up to 16
clemente 5:695063448f2a 179 data[0] = REG_FF_MT_THS;
clemente 8:7e6013f11b10 180 data[1] = 0x10;
clemente 5:695063448f2a 181 writeRegs(data, 2);
clemente 5:695063448f2a 182
clemente 5:695063448f2a 183 // Step 4: Set the debounce counter to eliminate false readings for 100 Hz sample rate with a requirement
clemente 5:695063448f2a 184 // of 100 ms timer.
clemente 5:695063448f2a 185 // Note: 100 ms/10 ms (steps) = 10 counts
clemente 5:695063448f2a 186 data[0] = REG_FF_MT_CNT;
clemente 5:695063448f2a 187 data[1] = 0x0A;
clemente 5:695063448f2a 188 writeRegs(data, 2);
clemente 5:695063448f2a 189
clemente 5:695063448f2a 190 // Step 5: Enable Motion/Freefall Interrupt Function in the System (CTRL_REG4)
clemente 5:695063448f2a 191 data[0] = REG_CTRL_REG_4;
clemente 5:695063448f2a 192 data[1] = 0x04;
clemente 5:695063448f2a 193 writeRegs(data, 2);
clemente 5:695063448f2a 194
clemente 7:ba0016258d5d 195 // Step 6: Route the Motion/Freefall Interrupt Function to INT2 hardware pin (CTRL_REG5)
clemente 5:695063448f2a 196 data[0] = REG_CTRL_REG_5;
clemente 7:ba0016258d5d 197 data[1] = 0x00;
clemente 5:695063448f2a 198 writeRegs(data, 2);
clemente 5:695063448f2a 199
clemente 5:695063448f2a 200 // Step 7: Put the device in Active Mode
clemente 5:695063448f2a 201 data[0] = REG_CTRL_REG_1;
clemente 5:695063448f2a 202 data[1] = 0x19;
clemente 5:695063448f2a 203 writeRegs(data, 2);
clemente 5:695063448f2a 204
clemente 7:ba0016258d5d 205 user2_fptr = fptr;
clemente 7:ba0016258d5d 206 MMA8451Q_Int2.fall( this, &MMA8451Q::Motion_IRQ);
clemente 5:695063448f2a 207
clemente 5:695063448f2a 208 }
clemente 5:695063448f2a 209
clemente 5:695063448f2a 210 void MMA8451Q::Motion_IRQ( void)
clemente 5:695063448f2a 211 {
clemente 5:695063448f2a 212 unsigned char t;
clemente 5:695063448f2a 213
clemente 5:695063448f2a 214 // Determine source of the interrupt by first reading the system interrupt
clemente 5:695063448f2a 215 readRegs( REG_INT_SRC, &t, 1);
clemente 5:695063448f2a 216 //
clemente 5:695063448f2a 217 if ( (t & 0x04) == 0x04) {
clemente 5:695063448f2a 218 // Read the Motion/Freefall Function to clear the interrupt
clemente 5:695063448f2a 219 readRegs( REG_FF_MT_SRC, &t, 1);
clemente 5:695063448f2a 220 // Run the user supplied function
clemente 7:ba0016258d5d 221 user2_fptr();
clemente 5:695063448f2a 222 }
clemente 5:695063448f2a 223 }
clemente 5:695063448f2a 224
clemente 7:ba0016258d5d 225 void MMA8451Q::OrientationDetect( void(*fptr)(void))
clemente 6:c52175d13e0a 226 {
clemente 7:ba0016258d5d 227 OrientationDetect( fptr, Z_LOCKOUT_14, Z_BKFR_80, PL_THS_15, PL_HYS_0);
clemente 6:c52175d13e0a 228 }
clemente 6:c52175d13e0a 229
clemente 7:ba0016258d5d 230 void MMA8451Q::OrientationDetect( void(*fptr)(void), unsigned int Z_LockOut, unsigned int Z_BkFr, unsigned int PL_Thsld, unsigned int PL_Hyst)
clemente 6:c52175d13e0a 231 {
clemente 6:c52175d13e0a 232 unsigned char t;
clemente 8:7e6013f11b10 233
clemente 8:7e6013f11b10 234 // Soft Reset
clemente 8:7e6013f11b10 235 Reset();
clemente 8:7e6013f11b10 236
clemente 8:7e6013f11b10 237 // Reset orientation value.
clemente 8:7e6013f11b10 238 OrientationState = 0;
clemente 8:7e6013f11b10 239 OrientationStateUpdated = 0;
clemente 6:c52175d13e0a 240
clemente 6:c52175d13e0a 241 // Step 1: Put the part into Standby Mode
clemente 6:c52175d13e0a 242 Standby();
clemente 6:c52175d13e0a 243
clemente 6:c52175d13e0a 244 // Step 2: Set the data rate to 50 Hz (for example, but can choose any sample rate).
clemente 6:c52175d13e0a 245 readRegs( REG_CTRL_REG_1, &t, 1); // Note: Can combine this step with above
clemente 6:c52175d13e0a 246 t &= 0xC7; // Clear the sample rate bits
clemente 6:c52175d13e0a 247 t |= 0x20; // Set the sample rate bits to 50 Hz
clemente 6:c52175d13e0a 248 unsigned char data[2] = {REG_CTRL_REG_1, t};
clemente 6:c52175d13e0a 249 writeRegs(data, 2); // Write updated value into the register.
clemente 6:c52175d13e0a 250
clemente 6:c52175d13e0a 251
clemente 6:c52175d13e0a 252 // Step 3: Set the PL_EN bit in Register 0x11 PL_CFG. This will enable the orientation detection.
clemente 6:c52175d13e0a 253 readRegs( REG_DBCNTM, &t, 1);
clemente 6:c52175d13e0a 254 data[0] = REG_DBCNTM;
clemente 6:c52175d13e0a 255 data[1] = t | 0x40;
clemente 6:c52175d13e0a 256 writeRegs(data, 2);
clemente 6:c52175d13e0a 257
clemente 6:c52175d13e0a 258 // Step 4: Set the Back/Front Angle trip points in register 0x13 following the table in the data sheet.
clemente 6:c52175d13e0a 259 // NOTE: This register is readable in all versions of MMA845xQ but it is only modifiable in the
clemente 6:c52175d13e0a 260 // MMA8451Q.
clemente 6:c52175d13e0a 261 readRegs( REG_BKFR, &t, 1);
clemente 6:c52175d13e0a 262 t &= 0x3F; // Clear bit 7 and 6
clemente 6:c52175d13e0a 263 data[0] = REG_BKFR;
clemente 6:c52175d13e0a 264 data[1] = t | Z_BkFr;
clemente 6:c52175d13e0a 265 writeRegs(data, 2); // Write in the updated Back/Front Angle
clemente 6:c52175d13e0a 266
clemente 6:c52175d13e0a 267 // Step 5: Set the Z-Lockout angle trip point in register 0x13 following the table in the data sheet.
clemente 6:c52175d13e0a 268 // NOTE: This register is readable in all versions of MMA845xQ but it is only modifiable in the
clemente 6:c52175d13e0a 269 // MMA8451Q.
clemente 6:c52175d13e0a 270 readRegs( REG_BKFR, &t, 1);
clemente 6:c52175d13e0a 271 t &= 0xF8; // Clear the last three bits of the register
clemente 6:c52175d13e0a 272 data[0] = REG_BKFR;
clemente 6:c52175d13e0a 273 data[1] = t | Z_LockOut;
clemente 6:c52175d13e0a 274 writeRegs(data, 2); // Write in the updated Z-lockout angle
clemente 6:c52175d13e0a 275
clemente 6:c52175d13e0a 276 // Step 6: Set the Trip Threshold Angle
clemente 6:c52175d13e0a 277 // NOTE: This register is readable in all versions of MMA845xQ but it is only modifiable in the
clemente 6:c52175d13e0a 278 // MMA8451Q.
clemente 6:c52175d13e0a 279 // Select the angle desired in the table, and,
clemente 6:c52175d13e0a 280 // Enter in the values given in the table for the corresponding angle.
clemente 6:c52175d13e0a 281 // Refer to Figure 7 for the reference frame of the trip angles.
clemente 6:c52175d13e0a 282 readRegs( REG_P_L_THS, &t, 1);
clemente 6:c52175d13e0a 283 t &= 0x07; // Clear the Threshold values
clemente 6:c52175d13e0a 284 data[0] = REG_P_L_THS;
clemente 6:c52175d13e0a 285 data[1] = t | (PL_Thsld<<3);
clemente 6:c52175d13e0a 286 writeRegs(data, 2);
clemente 6:c52175d13e0a 287
clemente 6:c52175d13e0a 288 // Step 7: Set the Hysteresis Angle
clemente 6:c52175d13e0a 289 // NOTE: This register is readable in all versions of MMA845xQ but it is only modifiable in the
clemente 6:c52175d13e0a 290 // MMA8451Q.
clemente 6:c52175d13e0a 291 // Select the hysteresis value based on the desired final trip points (threshold + hysteresis)
clemente 6:c52175d13e0a 292 // Enter in the values given in the table for that corresponding angle.
clemente 6:c52175d13e0a 293 // Note: Care must be taken. Review the final resulting angles. Make sure there isn’t a resulting trip value
clemente 6:c52175d13e0a 294 // greater than 90 or less than 0.
clemente 6:c52175d13e0a 295 // The following are the options for setting the hysteresis.
clemente 6:c52175d13e0a 296 readRegs( REG_P_L_THS, &t, 1);
clemente 6:c52175d13e0a 297 t &= 0xF8; // Clear the Hysteresis values
clemente 6:c52175d13e0a 298 data[0] = REG_P_L_THS;
clemente 6:c52175d13e0a 299 data[1] = t | PL_Hyst;
clemente 6:c52175d13e0a 300 writeRegs(data, 2);
clemente 6:c52175d13e0a 301
clemente 6:c52175d13e0a 302 // Step 8: Register 0x2D, Control Register 4 configures all embedded features for interrupt
clemente 6:c52175d13e0a 303 // detection.
clemente 6:c52175d13e0a 304 // To set this device up to run an interrupt service routine:
clemente 6:c52175d13e0a 305 // Program the Orientation Detection bit in Control Register 4.
clemente 6:c52175d13e0a 306 // Set bit 4 to enable the orientation detection “INT_EN_LNDPRT”.
clemente 6:c52175d13e0a 307 readRegs( REG_CTRL_REG_4, &t, 1);
clemente 6:c52175d13e0a 308 data[0] = REG_CTRL_REG_4;
clemente 6:c52175d13e0a 309 data[1] = t | 0x10; // Set bit 4
clemente 6:c52175d13e0a 310 writeRegs(data, 2);
clemente 6:c52175d13e0a 311
clemente 6:c52175d13e0a 312 // Step 9: Register 0x2E is Control Register 5 which gives the option of routing the interrupt to
clemente 6:c52175d13e0a 313 // either INT1 or INT2
clemente 6:c52175d13e0a 314 // Depending on which interrupt pin is enabled and configured to the processor:
clemente 6:c52175d13e0a 315 // Set bit 4 “INT_CFG_LNDPRT” to configure INT1, or,
clemente 6:c52175d13e0a 316 // Leave the bit clear to configure INT2.
clemente 6:c52175d13e0a 317 readRegs( REG_CTRL_REG_5, &t, 1);
clemente 6:c52175d13e0a 318 data[0] = REG_CTRL_REG_5;
clemente 6:c52175d13e0a 319 data[1] = t | 0x10; // Set bit 4 to choose the interrupt to route to INT1
clemente 6:c52175d13e0a 320 writeRegs(data, 2);
clemente 6:c52175d13e0a 321
clemente 6:c52175d13e0a 322 // Step 10: Set the debounce counter in register 0x12
clemente 6:c52175d13e0a 323 // This value will scale depending on the application-specific required ODR.
clemente 6:c52175d13e0a 324 // If the device is set to go to sleep, reset the debounce counter before the device goes to sleep. This setting
clemente 6:c52175d13e0a 325 // helps avoid long delays since the debounce will always scale with the current sample rate. The debounce
clemente 6:c52175d13e0a 326 // can be set between 50 ms - 100 ms to avoid long delays.
clemente 6:c52175d13e0a 327 data[0] = REG_DBNCE;
clemente 6:c52175d13e0a 328 data[1] = 0x05; // This sets the debounce counter to 100 ms at 50 Hz
clemente 6:c52175d13e0a 329 writeRegs(data, 2);
clemente 6:c52175d13e0a 330
clemente 6:c52175d13e0a 331 // Step 11: Put the device in Active Mode
clemente 6:c52175d13e0a 332 Active();
clemente 7:ba0016258d5d 333
clemente 7:ba0016258d5d 334 user1_fptr = fptr;
clemente 7:ba0016258d5d 335 MMA8451Q_Int1.fall( this, &MMA8451Q::Orientation_IRQ);
clemente 7:ba0016258d5d 336
clemente 7:ba0016258d5d 337 }
clemente 7:ba0016258d5d 338
clemente 7:ba0016258d5d 339 void MMA8451Q::Orientation_IRQ( void)
clemente 7:ba0016258d5d 340 {
clemente 7:ba0016258d5d 341 unsigned char t;
clemente 6:c52175d13e0a 342
clemente 7:ba0016258d5d 343 // Determine source of the interrupt by first reading the system interrupt
clemente 7:ba0016258d5d 344 readRegs( REG_INT_SRC, &t, 1);
clemente 7:ba0016258d5d 345 //
clemente 7:ba0016258d5d 346 if ( (t & 0x10) == 0x10) {
clemente 7:ba0016258d5d 347 // Read the PL State from the Status Register, clear the interrupt
clemente 7:ba0016258d5d 348 readRegs( REG_PL_STATUS, &t, 1);
clemente 8:7e6013f11b10 349 // Set the orientation state variable
clemente 8:7e6013f11b10 350 OrientationState = t;
clemente 8:7e6013f11b10 351 OrientationStateUpdated = 1;
clemente 7:ba0016258d5d 352 // Run the user supplied function
clemente 7:ba0016258d5d 353 user1_fptr();
clemente 7:ba0016258d5d 354 }
clemente 6:c52175d13e0a 355 }
clemente 6:c52175d13e0a 356
clemente 8:7e6013f11b10 357 unsigned char MMA8451Q::GetOrientationState( void)
clemente 8:7e6013f11b10 358 {
clemente 8:7e6013f11b10 359 if ( OrientationStateUpdated) {
clemente 8:7e6013f11b10 360 OrientationStateUpdated = 0;
clemente 8:7e6013f11b10 361 return OrientationState;
clemente 8:7e6013f11b10 362 }
clemente 8:7e6013f11b10 363 //
clemente 8:7e6013f11b10 364 return 0;
clemente 8:7e6013f11b10 365 }
clemente 8:7e6013f11b10 366
clemente 5:695063448f2a 367 void MMA8451Q::Active( void)
clemente 5:695063448f2a 368 {
clemente 5:695063448f2a 369 unsigned char t;
clemente 5:695063448f2a 370
clemente 5:695063448f2a 371 // Activate the peripheral
clemente 5:695063448f2a 372 readRegs(REG_CTRL_REG_1, &t, 1);
clemente 5:695063448f2a 373 unsigned char data[2] = {REG_CTRL_REG_1, t|0x01};
clemente 5:695063448f2a 374 writeRegs(data, 2);
clemente 5:695063448f2a 375 }
clemente 5:695063448f2a 376
clemente 5:695063448f2a 377 void MMA8451Q::Standby( void)
clemente 5:695063448f2a 378 {
clemente 5:695063448f2a 379 unsigned char t;
clemente 5:695063448f2a 380
clemente 5:695063448f2a 381 // Standby
clemente 5:695063448f2a 382 readRegs(REG_CTRL_REG_1, &t, 1);
clemente 5:695063448f2a 383 unsigned char data[2] = {REG_CTRL_REG_1, t&0xFE};
clemente 5:695063448f2a 384 writeRegs(data, 2);
clemente 5:695063448f2a 385 }
emilmont 0:6149091f755d 386
emilmont 0:6149091f755d 387 uint8_t MMA8451Q::getWhoAmI() {
emilmont 0:6149091f755d 388 uint8_t who_am_i = 0;
samux 1:d2630136d51e 389 readRegs(REG_WHO_AM_I, &who_am_i, 1);
emilmont 0:6149091f755d 390 return who_am_i;
emilmont 0:6149091f755d 391 }
emilmont 0:6149091f755d 392
chris 3:db7126dbd63f 393 float MMA8451Q::getAccX() {
chris 3:db7126dbd63f 394 return (float(getAccAxis(REG_OUT_X_MSB))/4096.0);
emilmont 0:6149091f755d 395 }
emilmont 0:6149091f755d 396
chris 3:db7126dbd63f 397 float MMA8451Q::getAccY() {
chris 3:db7126dbd63f 398 return (float(getAccAxis(REG_OUT_Y_MSB))/4096.0);
emilmont 0:6149091f755d 399 }
emilmont 0:6149091f755d 400
chris 3:db7126dbd63f 401 float MMA8451Q::getAccZ() {
chris 3:db7126dbd63f 402 return (float(getAccAxis(REG_OUT_Z_MSB))/4096.0);
emilmont 0:6149091f755d 403 }
emilmont 0:6149091f755d 404
chris 3:db7126dbd63f 405 void MMA8451Q::getAccAllAxis(float * res) {
emilmont 0:6149091f755d 406 res[0] = getAccX();
emilmont 0:6149091f755d 407 res[1] = getAccY();
emilmont 0:6149091f755d 408 res[2] = getAccZ();
emilmont 0:6149091f755d 409 }
emilmont 0:6149091f755d 410
emilmont 0:6149091f755d 411 int16_t MMA8451Q::getAccAxis(uint8_t addr) {
emilmont 0:6149091f755d 412 int16_t acc;
emilmont 0:6149091f755d 413 uint8_t res[2];
samux 1:d2630136d51e 414 readRegs(addr, res, 2);
emilmont 0:6149091f755d 415
emilmont 0:6149091f755d 416 acc = (res[0] << 6) | (res[1] >> 2);
emilmont 0:6149091f755d 417 if (acc > UINT14_MAX/2)
emilmont 0:6149091f755d 418 acc -= UINT14_MAX;
emilmont 0:6149091f755d 419
emilmont 0:6149091f755d 420 return acc;
emilmont 0:6149091f755d 421 }
emilmont 0:6149091f755d 422
samux 1:d2630136d51e 423 void MMA8451Q::readRegs(int addr, uint8_t * data, int len) {
emilmont 0:6149091f755d 424 char t[1] = {addr};
emilmont 0:6149091f755d 425 m_i2c.write(m_addr, t, 1, true);
emilmont 0:6149091f755d 426 m_i2c.read(m_addr, (char *)data, len);
emilmont 0:6149091f755d 427 }
emilmont 0:6149091f755d 428
samux 1:d2630136d51e 429 void MMA8451Q::writeRegs(uint8_t * data, int len) {
emilmont 0:6149091f755d 430 m_i2c.write(m_addr, (char *)data, len);
emilmont 0:6149091f755d 431 }