clemente di caprio / FRDM_MMA8451Q

Added code to manage Orientation, FreeFall and Motion Detection. Data is also available via IRQ.

Dependents:   Test_FRDM_MMA8451Q AccelTest FRDM-KL46-Template KL25Z_Demo ... more

Fork of MMA8451Q by Emilio Monti

MMA8451Q.cpp@7:ba0016258d5d, 2013-05-28 (annotated)

Committer:
clemente
Date:
Tue May 28 10:33:50 2013 +0000
Revision:
7:ba0016258d5d
Parent:
6:c52175d13e0a
Child:
8:7e6013f11b10
Orientation detection added. To be tested.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
samux 1:d2630136d51e 1 /* Copyright (c) 2010-2011 mbed.org, MIT License
samux 1:d2630136d51e 2 *
samux 1:d2630136d51e 3 * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
samux 1:d2630136d51e 4 * and associated documentation files (the "Software"), to deal in the Software without
samux 1:d2630136d51e 5 * restriction, including without limitation the rights to use, copy, modify, merge, publish,
samux 1:d2630136d51e 6 * distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
samux 1:d2630136d51e 7 * Software is furnished to do so, subject to the following conditions:
samux 1:d2630136d51e 8 *
samux 1:d2630136d51e 9 * The above copyright notice and this permission notice shall be included in all copies or
samux 1:d2630136d51e 10 * substantial portions of the Software.
samux 1:d2630136d51e 11 *
samux 1:d2630136d51e 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
samux 1:d2630136d51e 13 * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
samux 1:d2630136d51e 14 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
samux 1:d2630136d51e 15 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
samux 1:d2630136d51e 16 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
samux 1:d2630136d51e 17 */
samux 1:d2630136d51e 18
emilmont 0:6149091f755d 19 #include "MMA8451Q.h"
emilmont 0:6149091f755d 20
samux 1:d2630136d51e 21 #define REG_WHO_AM_I 0x0D
samux 1:d2630136d51e 22 #define REG_CTRL_REG_1 0x2A
clemente 5:695063448f2a 23 #define REG_CTRL_REG_4 0x2D
clemente 5:695063448f2a 24 #define REG_CTRL_REG_5 0x2E
clemente 5:695063448f2a 25 #define REG_INT_SRC 0x0C
clemente 5:695063448f2a 26 #define REG_FF_MT_CFG 0x15
clemente 5:695063448f2a 27 #define REG_FF_MT_SRC 0x16
clemente 5:695063448f2a 28 #define REG_FF_MT_THS 0x17
clemente 5:695063448f2a 29 #define REG_FF_MT_CNT 0x18
clemente 6:c52175d13e0a 30 #define REG_DBCNTM 0x11
clemente 6:c52175d13e0a 31 #define REG_DBNCE 0x12
clemente 6:c52175d13e0a 32 #define REG_BKFR 0x13
clemente 6:c52175d13e0a 33 #define REG_P_L_THS 0x14
clemente 7:ba0016258d5d 34 #define REG_PL_STATUS 0x10
clemente 7:ba0016258d5d 35
clemente 5:695063448f2a 36 //
emilmont 0:6149091f755d 37 #define REG_OUT_X_MSB 0x01
emilmont 0:6149091f755d 38 #define REG_OUT_Y_MSB 0x03
emilmont 0:6149091f755d 39 #define REG_OUT_Z_MSB 0x05
emilmont 0:6149091f755d 40
samux 1:d2630136d51e 41 #define UINT14_MAX 16383
emilmont 0:6149091f755d 42
clemente 7:ba0016258d5d 43 /** Interrupt schema
clemente 7:ba0016258d5d 44 *
clemente 7:ba0016258d5d 45 * :: The FreeFall and Motion detection share the same IRQ.
clemente 7:ba0016258d5d 46 *
clemente 7:ba0016258d5d 47 * FreeFall --+ +-- Fall_IRQ -----+
clemente 7:ba0016258d5d 48 * \ / \
clemente 7:ba0016258d5d 49 * +-- MMA8451Q_Int2.fall ---+ +--- user2_fptr
clemente 7:ba0016258d5d 50 * / \ /
clemente 7:ba0016258d5d 51 * Motion ----+ +-- Motion_IRQ ---+
clemente 7:ba0016258d5d 52 *
clemente 7:ba0016258d5d 53 * :: The Orientation Detect use the IRQ1
clemente 7:ba0016258d5d 54 *
clemente 7:ba0016258d5d 55 * Orientation Detect -- MMA8451Q_Int1.fall --- Orientation_IRQ --- user1_fptr
clemente 7:ba0016258d5d 56 *
clemente 7:ba0016258d5d 57 */
clemente 7:ba0016258d5d 58 void (*user2_fptr)(void);
clemente 7:ba0016258d5d 59 void (*user1_fptr)(void);
clemente 5:695063448f2a 60
clemente 5:695063448f2a 61 //
clemente 5:695063448f2a 62 InterruptIn MMA8451Q_Int1( PTA14);
clemente 5:695063448f2a 63 InterruptIn MMA8451Q_Int2( PTA15);
clemente 5:695063448f2a 64
emilmont 0:6149091f755d 65 MMA8451Q::MMA8451Q(PinName sda, PinName scl, int addr) : m_i2c(sda, scl), m_addr(addr) {
emilmont 0:6149091f755d 66 // activate the peripheral
emilmont 0:6149091f755d 67 uint8_t data[2] = {REG_CTRL_REG_1, 0x01};
samux 1:d2630136d51e 68 writeRegs(data, 2);
emilmont 0:6149091f755d 69 }
emilmont 0:6149091f755d 70
clemente 5:695063448f2a 71 MMA8451Q::~MMA8451Q()
clemente 5:695063448f2a 72 {
clemente 5:695063448f2a 73 MMA8451Q_Int1.fall( NULL);
clemente 5:695063448f2a 74 MMA8451Q_Int2.fall( NULL);
clemente 7:ba0016258d5d 75 user2_fptr = NULL;
clemente 7:ba0016258d5d 76 user1_fptr = NULL;
clemente 5:695063448f2a 77 }
clemente 5:695063448f2a 78
clemente 5:695063448f2a 79 void MMA8451Q::FreFallDetection( void(*fptr)(void))
clemente 5:695063448f2a 80 {
clemente 5:695063448f2a 81 // Example Steps for Configuring Linear Freefall Detection
clemente 5:695063448f2a 82 // X AND Y AND Z < 0.2g using MFF Function, 50 Hz ODR
clemente 5:695063448f2a 83 // Step 1: Put the device in Standby Mode: Register 0x2A CTRL_REG1
clemente 5:695063448f2a 84 unsigned char data[2] = {REG_CTRL_REG_1, 0x20};
clemente 5:695063448f2a 85 writeRegs(data, 2);
clemente 5:695063448f2a 86
clemente 5:695063448f2a 87 // Step 2: Configuration Register set for Freefall Detection enabling “AND” condition, OAE = 0, Enabling X,
clemente 5:695063448f2a 88 // Y, Z and the Latch
clemente 5:695063448f2a 89 data[0] = REG_FF_MT_CFG;
clemente 5:695063448f2a 90 data[1] = 0x01;
clemente 5:695063448f2a 91 writeRegs(data, 2);
clemente 5:695063448f2a 92
clemente 5:695063448f2a 93 // Step 3: Threshold Setting Value for the resulting acceleration < 0.2g
clemente 5:695063448f2a 94 // Note: The step count is 0.063g/count
clemente 5:695063448f2a 95 // • 0.2g/0.063g = 3.17 counts //Round to 3 counts
clemente 5:695063448f2a 96 data[0] = REG_FF_MT_THS;
clemente 5:695063448f2a 97 data[1] = 0x03;
clemente 5:695063448f2a 98 writeRegs(data, 2);
clemente 5:695063448f2a 99
clemente 5:695063448f2a 100 // Step 4: Set the debounce counter to eliminate false positive readings for 50Hz sample rate with a
clemente 5:695063448f2a 101 // requirement of 120 ms timer, assuming Normal Mode.
clemente 5:695063448f2a 102 // Note: 120 ms/20 ms (steps) = 6 counts
clemente 5:695063448f2a 103 data[0] = REG_FF_MT_CNT;
clemente 5:695063448f2a 104 data[1] = 0x06;
clemente 5:695063448f2a 105 writeRegs(data, 2);
clemente 5:695063448f2a 106
clemente 5:695063448f2a 107 // Step 5: Enable Motion/Freefall Interrupt Function in the System (CTRL_REG4)
clemente 5:695063448f2a 108 data[0] = REG_CTRL_REG_4;
clemente 5:695063448f2a 109 data[1] = 0x04;
clemente 5:695063448f2a 110 writeRegs(data, 2);
clemente 5:695063448f2a 111
clemente 5:695063448f2a 112 // Step 6: Route the Motion/Freefall Interrupt Function to INT2 hardware pin (CTRL_REG5)
clemente 5:695063448f2a 113 data[0] = REG_CTRL_REG_5;
clemente 5:695063448f2a 114 data[1] = 0x00;
clemente 5:695063448f2a 115 writeRegs(data, 2);
clemente 5:695063448f2a 116
clemente 5:695063448f2a 117 // Step 7: Put the device in Active Mode, 50 Hz
clemente 5:695063448f2a 118 data[0] = REG_CTRL_REG_1;
clemente 5:695063448f2a 119 data[1] = 0x21;
clemente 5:695063448f2a 120 writeRegs(data, 2);
clemente 5:695063448f2a 121
clemente 7:ba0016258d5d 122 user2_fptr = fptr;
clemente 5:695063448f2a 123 MMA8451Q_Int2.fall( this, &MMA8451Q::Fall_IRQ);
clemente 5:695063448f2a 124 }
clemente 5:695063448f2a 125
clemente 5:695063448f2a 126 void MMA8451Q::Fall_IRQ( void)
clemente 5:695063448f2a 127 {
clemente 5:695063448f2a 128 unsigned char t;
clemente 5:695063448f2a 129
clemente 5:695063448f2a 130 // Determine source of the interrupt by first reading the system interrupt
clemente 5:695063448f2a 131 readRegs( REG_INT_SRC, &t, 1);
clemente 5:695063448f2a 132 //
clemente 5:695063448f2a 133 if ( (t & 0x04) == 0x04) {
clemente 5:695063448f2a 134 // Read the Motion/Freefall Function to clear the interrupt
clemente 5:695063448f2a 135 readRegs( REG_FF_MT_SRC, &t, 1);
clemente 5:695063448f2a 136 // Run the user supplied function
clemente 7:ba0016258d5d 137 user2_fptr();
clemente 5:695063448f2a 138 }
clemente 5:695063448f2a 139 }
clemente 5:695063448f2a 140
clemente 5:695063448f2a 141 void MMA8451Q::MotionDetection( void(*fptr)(void))
clemente 5:695063448f2a 142 {
clemente 5:695063448f2a 143
clemente 5:695063448f2a 144 // 6.1 Example Steps for Configuring Motion Detection
clemente 5:695063448f2a 145 // X or Y > 3g using MFF Function 4g, 100 Hz ODR, Normal Mode
clemente 5:695063448f2a 146 // Step 1: Put the device into Standby Mode: Register 0x2A CTRL_REG1
clemente 5:695063448f2a 147 unsigned char data[2] = {REG_CTRL_REG_1, 0x18}; // Set the device in 100 Hz ODR, Standby
clemente 5:695063448f2a 148 writeRegs(data, 2);
clemente 5:695063448f2a 149
clemente 5:695063448f2a 150
clemente 5:695063448f2a 151 // Step 2: Set Configuration Register for Motion Detection by setting the “OR” condition OAE = 1, enabling
clemente 5:695063448f2a 152 // X, Y, and the latch
clemente 5:695063448f2a 153 data[0] = REG_FF_MT_CFG;
clemente 5:695063448f2a 154 data[1] = 0xD8;
clemente 5:695063448f2a 155 writeRegs(data, 2);
clemente 5:695063448f2a 156
clemente 5:695063448f2a 157 // Step 3: Threshold Setting Value for the Motion detection of > 2g
clemente 5:695063448f2a 158 // Note: The step count is 0.063g/ count
clemente 5:695063448f2a 159 // • 2g/0.063g = 31.7; //Round up to 32
clemente 5:695063448f2a 160 data[0] = REG_FF_MT_THS;
clemente 5:695063448f2a 161 data[1] = 0x20;
clemente 5:695063448f2a 162 writeRegs(data, 2);
clemente 5:695063448f2a 163
clemente 5:695063448f2a 164 // Step 4: Set the debounce counter to eliminate false readings for 100 Hz sample rate with a requirement
clemente 5:695063448f2a 165 // of 100 ms timer.
clemente 5:695063448f2a 166 // Note: 100 ms/10 ms (steps) = 10 counts
clemente 5:695063448f2a 167 data[0] = REG_FF_MT_CNT;
clemente 5:695063448f2a 168 data[1] = 0x0A;
clemente 5:695063448f2a 169 writeRegs(data, 2);
clemente 5:695063448f2a 170
clemente 5:695063448f2a 171 // Step 5: Enable Motion/Freefall Interrupt Function in the System (CTRL_REG4)
clemente 5:695063448f2a 172 data[0] = REG_CTRL_REG_4;
clemente 5:695063448f2a 173 data[1] = 0x04;
clemente 5:695063448f2a 174 writeRegs(data, 2);
clemente 5:695063448f2a 175
clemente 7:ba0016258d5d 176 // Step 6: Route the Motion/Freefall Interrupt Function to INT2 hardware pin (CTRL_REG5)
clemente 5:695063448f2a 177 data[0] = REG_CTRL_REG_5;
clemente 7:ba0016258d5d 178 data[1] = 0x00;
clemente 5:695063448f2a 179 writeRegs(data, 2);
clemente 5:695063448f2a 180
clemente 5:695063448f2a 181 // Step 7: Put the device in Active Mode
clemente 5:695063448f2a 182 data[0] = REG_CTRL_REG_1;
clemente 5:695063448f2a 183 data[1] = 0x19;
clemente 5:695063448f2a 184 writeRegs(data, 2);
clemente 5:695063448f2a 185
clemente 7:ba0016258d5d 186 user2_fptr = fptr;
clemente 7:ba0016258d5d 187 MMA8451Q_Int2.fall( this, &MMA8451Q::Motion_IRQ);
clemente 5:695063448f2a 188
clemente 5:695063448f2a 189 }
clemente 5:695063448f2a 190
clemente 5:695063448f2a 191 void MMA8451Q::Motion_IRQ( void)
clemente 5:695063448f2a 192 {
clemente 5:695063448f2a 193 unsigned char t;
clemente 5:695063448f2a 194
clemente 5:695063448f2a 195 // Determine source of the interrupt by first reading the system interrupt
clemente 5:695063448f2a 196 readRegs( REG_INT_SRC, &t, 1);
clemente 5:695063448f2a 197 //
clemente 5:695063448f2a 198 if ( (t & 0x04) == 0x04) {
clemente 5:695063448f2a 199 // Read the Motion/Freefall Function to clear the interrupt
clemente 5:695063448f2a 200 readRegs( REG_FF_MT_SRC, &t, 1);
clemente 5:695063448f2a 201 // Run the user supplied function
clemente 7:ba0016258d5d 202 user2_fptr();
clemente 5:695063448f2a 203 }
clemente 5:695063448f2a 204 }
clemente 5:695063448f2a 205
clemente 7:ba0016258d5d 206 void MMA8451Q::OrientationDetect( void(*fptr)(void))
clemente 6:c52175d13e0a 207 {
clemente 7:ba0016258d5d 208 OrientationDetect( fptr, Z_LOCKOUT_14, Z_BKFR_80, PL_THS_15, PL_HYS_0);
clemente 6:c52175d13e0a 209 }
clemente 6:c52175d13e0a 210
clemente 7:ba0016258d5d 211 void MMA8451Q::OrientationDetect( void(*fptr)(void), unsigned int Z_LockOut, unsigned int Z_BkFr, unsigned int PL_Thsld, unsigned int PL_Hyst)
clemente 6:c52175d13e0a 212 {
clemente 6:c52175d13e0a 213 unsigned char t;
clemente 6:c52175d13e0a 214
clemente 6:c52175d13e0a 215 // Step 1: Put the part into Standby Mode
clemente 6:c52175d13e0a 216 Standby();
clemente 6:c52175d13e0a 217
clemente 6:c52175d13e0a 218 // Step 2: Set the data rate to 50 Hz (for example, but can choose any sample rate).
clemente 6:c52175d13e0a 219 readRegs( REG_CTRL_REG_1, &t, 1); // Note: Can combine this step with above
clemente 6:c52175d13e0a 220 t &= 0xC7; // Clear the sample rate bits
clemente 6:c52175d13e0a 221 t |= 0x20; // Set the sample rate bits to 50 Hz
clemente 6:c52175d13e0a 222 unsigned char data[2] = {REG_CTRL_REG_1, t};
clemente 6:c52175d13e0a 223 writeRegs(data, 2); // Write updated value into the register.
clemente 6:c52175d13e0a 224
clemente 6:c52175d13e0a 225
clemente 6:c52175d13e0a 226 // Step 3: Set the PL_EN bit in Register 0x11 PL_CFG. This will enable the orientation detection.
clemente 6:c52175d13e0a 227 readRegs( REG_DBCNTM, &t, 1);
clemente 6:c52175d13e0a 228 data[0] = REG_DBCNTM;
clemente 6:c52175d13e0a 229 data[1] = t | 0x40;
clemente 6:c52175d13e0a 230 writeRegs(data, 2);
clemente 6:c52175d13e0a 231
clemente 6:c52175d13e0a 232 // Step 4: Set the Back/Front Angle trip points in register 0x13 following the table in the data sheet.
clemente 6:c52175d13e0a 233 // NOTE: This register is readable in all versions of MMA845xQ but it is only modifiable in the
clemente 6:c52175d13e0a 234 // MMA8451Q.
clemente 6:c52175d13e0a 235 readRegs( REG_BKFR, &t, 1);
clemente 6:c52175d13e0a 236 t &= 0x3F; // Clear bit 7 and 6
clemente 6:c52175d13e0a 237 data[0] = REG_BKFR;
clemente 6:c52175d13e0a 238 data[1] = t | Z_BkFr;
clemente 6:c52175d13e0a 239 writeRegs(data, 2); // Write in the updated Back/Front Angle
clemente 6:c52175d13e0a 240
clemente 6:c52175d13e0a 241 // Step 5: Set the Z-Lockout angle trip point in register 0x13 following the table in the data sheet.
clemente 6:c52175d13e0a 242 // NOTE: This register is readable in all versions of MMA845xQ but it is only modifiable in the
clemente 6:c52175d13e0a 243 // MMA8451Q.
clemente 6:c52175d13e0a 244 readRegs( REG_BKFR, &t, 1);
clemente 6:c52175d13e0a 245 t &= 0xF8; // Clear the last three bits of the register
clemente 6:c52175d13e0a 246 data[0] = REG_BKFR;
clemente 6:c52175d13e0a 247 data[1] = t | Z_LockOut;
clemente 6:c52175d13e0a 248 writeRegs(data, 2); // Write in the updated Z-lockout angle
clemente 6:c52175d13e0a 249
clemente 6:c52175d13e0a 250 // Step 6: Set the Trip Threshold Angle
clemente 6:c52175d13e0a 251 // NOTE: This register is readable in all versions of MMA845xQ but it is only modifiable in the
clemente 6:c52175d13e0a 252 // MMA8451Q.
clemente 6:c52175d13e0a 253 // Select the angle desired in the table, and,
clemente 6:c52175d13e0a 254 // Enter in the values given in the table for the corresponding angle.
clemente 6:c52175d13e0a 255 // Refer to Figure 7 for the reference frame of the trip angles.
clemente 6:c52175d13e0a 256 readRegs( REG_P_L_THS, &t, 1);
clemente 6:c52175d13e0a 257 t &= 0x07; // Clear the Threshold values
clemente 6:c52175d13e0a 258 data[0] = REG_P_L_THS;
clemente 6:c52175d13e0a 259 data[1] = t | (PL_Thsld<<3);
clemente 6:c52175d13e0a 260 writeRegs(data, 2);
clemente 6:c52175d13e0a 261
clemente 6:c52175d13e0a 262 // Step 7: Set the Hysteresis Angle
clemente 6:c52175d13e0a 263 // NOTE: This register is readable in all versions of MMA845xQ but it is only modifiable in the
clemente 6:c52175d13e0a 264 // MMA8451Q.
clemente 6:c52175d13e0a 265 // Select the hysteresis value based on the desired final trip points (threshold + hysteresis)
clemente 6:c52175d13e0a 266 // Enter in the values given in the table for that corresponding angle.
clemente 6:c52175d13e0a 267 // Note: Care must be taken. Review the final resulting angles. Make sure there isn’t a resulting trip value
clemente 6:c52175d13e0a 268 // greater than 90 or less than 0.
clemente 6:c52175d13e0a 269 // The following are the options for setting the hysteresis.
clemente 6:c52175d13e0a 270 readRegs( REG_P_L_THS, &t, 1);
clemente 6:c52175d13e0a 271 t &= 0xF8; // Clear the Hysteresis values
clemente 6:c52175d13e0a 272 data[0] = REG_P_L_THS;
clemente 6:c52175d13e0a 273 data[1] = t | PL_Hyst;
clemente 6:c52175d13e0a 274 writeRegs(data, 2);
clemente 6:c52175d13e0a 275
clemente 6:c52175d13e0a 276 // Step 8: Register 0x2D, Control Register 4 configures all embedded features for interrupt
clemente 6:c52175d13e0a 277 // detection.
clemente 6:c52175d13e0a 278 // To set this device up to run an interrupt service routine:
clemente 6:c52175d13e0a 279 // Program the Orientation Detection bit in Control Register 4.
clemente 6:c52175d13e0a 280 // Set bit 4 to enable the orientation detection “INT_EN_LNDPRT”.
clemente 6:c52175d13e0a 281 readRegs( REG_CTRL_REG_4, &t, 1);
clemente 6:c52175d13e0a 282 data[0] = REG_CTRL_REG_4;
clemente 6:c52175d13e0a 283 data[1] = t | 0x10; // Set bit 4
clemente 6:c52175d13e0a 284 writeRegs(data, 2);
clemente 6:c52175d13e0a 285
clemente 6:c52175d13e0a 286 // Step 9: Register 0x2E is Control Register 5 which gives the option of routing the interrupt to
clemente 6:c52175d13e0a 287 // either INT1 or INT2
clemente 6:c52175d13e0a 288 // Depending on which interrupt pin is enabled and configured to the processor:
clemente 6:c52175d13e0a 289 // Set bit 4 “INT_CFG_LNDPRT” to configure INT1, or,
clemente 6:c52175d13e0a 290 // Leave the bit clear to configure INT2.
clemente 6:c52175d13e0a 291 readRegs( REG_CTRL_REG_5, &t, 1);
clemente 6:c52175d13e0a 292 data[0] = REG_CTRL_REG_5;
clemente 6:c52175d13e0a 293 data[1] = t | 0x10; // Set bit 4 to choose the interrupt to route to INT1
clemente 6:c52175d13e0a 294 writeRegs(data, 2);
clemente 6:c52175d13e0a 295
clemente 6:c52175d13e0a 296 // Step 10: Set the debounce counter in register 0x12
clemente 6:c52175d13e0a 297 // This value will scale depending on the application-specific required ODR.
clemente 6:c52175d13e0a 298 // If the device is set to go to sleep, reset the debounce counter before the device goes to sleep. This setting
clemente 6:c52175d13e0a 299 // helps avoid long delays since the debounce will always scale with the current sample rate. The debounce
clemente 6:c52175d13e0a 300 // can be set between 50 ms - 100 ms to avoid long delays.
clemente 6:c52175d13e0a 301 data[0] = REG_DBNCE;
clemente 6:c52175d13e0a 302 data[1] = 0x05; // This sets the debounce counter to 100 ms at 50 Hz
clemente 6:c52175d13e0a 303 writeRegs(data, 2);
clemente 6:c52175d13e0a 304
clemente 6:c52175d13e0a 305 // Step 11: Put the device in Active Mode
clemente 6:c52175d13e0a 306 Active();
clemente 7:ba0016258d5d 307
clemente 7:ba0016258d5d 308 user1_fptr = fptr;
clemente 7:ba0016258d5d 309 MMA8451Q_Int1.fall( this, &MMA8451Q::Orientation_IRQ);
clemente 7:ba0016258d5d 310
clemente 7:ba0016258d5d 311 }
clemente 7:ba0016258d5d 312
clemente 7:ba0016258d5d 313 void MMA8451Q::Orientation_IRQ( void)
clemente 7:ba0016258d5d 314 {
clemente 7:ba0016258d5d 315 unsigned char t;
clemente 6:c52175d13e0a 316
clemente 7:ba0016258d5d 317 // Determine source of the interrupt by first reading the system interrupt
clemente 7:ba0016258d5d 318 readRegs( REG_INT_SRC, &t, 1);
clemente 7:ba0016258d5d 319 //
clemente 7:ba0016258d5d 320 if ( (t & 0x10) == 0x10) {
clemente 7:ba0016258d5d 321 // Read the PL State from the Status Register, clear the interrupt
clemente 7:ba0016258d5d 322 readRegs( REG_PL_STATUS, &t, 1);
clemente 7:ba0016258d5d 323 // Run the user supplied function
clemente 7:ba0016258d5d 324 user1_fptr();
clemente 7:ba0016258d5d 325 }
clemente 6:c52175d13e0a 326 }
clemente 6:c52175d13e0a 327
clemente 5:695063448f2a 328 void MMA8451Q::Active( void)
clemente 5:695063448f2a 329 {
clemente 5:695063448f2a 330 unsigned char t;
clemente 5:695063448f2a 331
clemente 5:695063448f2a 332 // Activate the peripheral
clemente 5:695063448f2a 333 readRegs(REG_CTRL_REG_1, &t, 1);
clemente 5:695063448f2a 334 unsigned char data[2] = {REG_CTRL_REG_1, t|0x01};
clemente 5:695063448f2a 335 writeRegs(data, 2);
clemente 5:695063448f2a 336 }
clemente 5:695063448f2a 337
clemente 5:695063448f2a 338 void MMA8451Q::Standby( void)
clemente 5:695063448f2a 339 {
clemente 5:695063448f2a 340 unsigned char t;
clemente 5:695063448f2a 341
clemente 5:695063448f2a 342 // Standby
clemente 5:695063448f2a 343 readRegs(REG_CTRL_REG_1, &t, 1);
clemente 5:695063448f2a 344 unsigned char data[2] = {REG_CTRL_REG_1, t&0xFE};
clemente 5:695063448f2a 345 writeRegs(data, 2);
clemente 5:695063448f2a 346 }
emilmont 0:6149091f755d 347
emilmont 0:6149091f755d 348 uint8_t MMA8451Q::getWhoAmI() {
emilmont 0:6149091f755d 349 uint8_t who_am_i = 0;
samux 1:d2630136d51e 350 readRegs(REG_WHO_AM_I, &who_am_i, 1);
emilmont 0:6149091f755d 351 return who_am_i;
emilmont 0:6149091f755d 352 }
emilmont 0:6149091f755d 353
chris 3:db7126dbd63f 354 float MMA8451Q::getAccX() {
chris 3:db7126dbd63f 355 return (float(getAccAxis(REG_OUT_X_MSB))/4096.0);
emilmont 0:6149091f755d 356 }
emilmont 0:6149091f755d 357
chris 3:db7126dbd63f 358 float MMA8451Q::getAccY() {
chris 3:db7126dbd63f 359 return (float(getAccAxis(REG_OUT_Y_MSB))/4096.0);
emilmont 0:6149091f755d 360 }
emilmont 0:6149091f755d 361
chris 3:db7126dbd63f 362 float MMA8451Q::getAccZ() {
chris 3:db7126dbd63f 363 return (float(getAccAxis(REG_OUT_Z_MSB))/4096.0);
emilmont 0:6149091f755d 364 }
emilmont 0:6149091f755d 365
chris 3:db7126dbd63f 366 void MMA8451Q::getAccAllAxis(float * res) {
emilmont 0:6149091f755d 367 res[0] = getAccX();
emilmont 0:6149091f755d 368 res[1] = getAccY();
emilmont 0:6149091f755d 369 res[2] = getAccZ();
emilmont 0:6149091f755d 370 }
emilmont 0:6149091f755d 371
emilmont 0:6149091f755d 372 int16_t MMA8451Q::getAccAxis(uint8_t addr) {
emilmont 0:6149091f755d 373 int16_t acc;
emilmont 0:6149091f755d 374 uint8_t res[2];
samux 1:d2630136d51e 375 readRegs(addr, res, 2);
emilmont 0:6149091f755d 376
emilmont 0:6149091f755d 377 acc = (res[0] << 6) | (res[1] >> 2);
emilmont 0:6149091f755d 378 if (acc > UINT14_MAX/2)
emilmont 0:6149091f755d 379 acc -= UINT14_MAX;
emilmont 0:6149091f755d 380
emilmont 0:6149091f755d 381 return acc;
emilmont 0:6149091f755d 382 }
emilmont 0:6149091f755d 383
samux 1:d2630136d51e 384 void MMA8451Q::readRegs(int addr, uint8_t * data, int len) {
emilmont 0:6149091f755d 385 char t[1] = {addr};
emilmont 0:6149091f755d 386 m_i2c.write(m_addr, t, 1, true);
emilmont 0:6149091f755d 387 m_i2c.read(m_addr, (char *)data, len);
emilmont 0:6149091f755d 388 }
emilmont 0:6149091f755d 389
samux 1:d2630136d51e 390 void MMA8451Q::writeRegs(uint8_t * data, int len) {
emilmont 0:6149091f755d 391 m_i2c.write(m_addr, (char *)data, len);
emilmont 0:6149091f755d 392 }