Bayley Wang / Mbed 2 deprecated qonly_controller

derp

Dependencies:   FastPWM3 mbed

main.cpp@14:10743610ecb5, 2016-04-18 (annotated)

Committer:
bwang
Date:
Mon Apr 18 22:53:35 2016 +0000
Revision:
14:10743610ecb5
Parent:
11:825203ff4371 
working

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bwang 0:bac9c3a3a6ca 1 #include "mbed.h"
bwang 0:bac9c3a3a6ca 2 #include "math.h"
bwang 0:bac9c3a3a6ca 3 #include "PositionSensor.h"
bwang 0:bac9c3a3a6ca 4 #include "FastPWM.h"
bwang 8:314074b56470 5
bwang 8:314074b56470 6 #define PWMA PA_8
bwang 8:314074b56470 7 #define PWMB PA_9
bwang 8:314074b56470 8 #define PWMC PA_10
bwang 8:314074b56470 9 #define EN PB_15
bwang 8:314074b56470 10
bwang 8:314074b56470 11 #define IA PA_4
bwang 8:314074b56470 12 #define IB PB_0
bwang 8:314074b56470 13
bwang 8:314074b56470 14 #define PI 3.141593f
bwang 8:314074b56470 15 #define CPR 4096
bwang 8:314074b56470 16 #define POS_OFFSET 4.5f
bwang 8:314074b56470 17
bwang 8:314074b56470 18 #define I_SCALE_RAW 25.0f //mv/A
bwang 8:314074b56470 19 #define R_UP 12000.0f //ohms
bwang 8:314074b56470 20 #define R_DOWN 3600.0f //ohms
bwang 8:314074b56470 21 #define R_BIAS 3600.0f //ohms
bwang 8:314074b56470 22 #define AVDD 3300.0f //mV
bwang 8:314074b56470 23
bwang 8:314074b56470 24 #define I_OFFSET (AVDD * R_DOWN * R_UP / (R_DOWN * R_UP + R_BIAS * (R_DOWN + R_UP)))
bwang 8:314074b56470 25 #define I_SCALE (R_BIAS * R_DOWN * I_SCALE_RAW / (R_DOWN * R_UP + R_BIAS * (R_DOWN + R_UP)))
bwang 8:314074b56470 26
bwang 8:314074b56470 27 #define K_LOOP 0.02
bwang 10:7624146c5945 28 #define KI_BASE 0.008
bwang 14:10743610ecb5 29 #define BUS_VOLTAGE 200.0
bwang 8:314074b56470 30
bwang 8:314074b56470 31 #define KP (K_LOOP / BUS_VOLTAGE)
bwang 8:314074b56470 32 #define KI (KI_BASE * K_LOOP / BUS_VOLTAGE)
bwang 8:314074b56470 33
bwang 8:314074b56470 34 #define INTEGRAL_MAX 1.0f
bwang 0:bac9c3a3a6ca 35
bwang 11:825203ff4371 36 #define Q_REF_MAX (-200.0)
bwang 10:7624146c5945 37
bwang 1:7b61790f6be9 38 FastPWM *a;
bwang 1:7b61790f6be9 39 FastPWM *b;
bwang 1:7b61790f6be9 40 FastPWM *c;
bwang 0:bac9c3a3a6ca 41 DigitalOut en(EN);
bwang 0:bac9c3a3a6ca 42
bwang 14:10743610ecb5 43 DigitalIn throttle_in(PB_8);
bwang 0:bac9c3a3a6ca 44 PositionSensorEncoder pos(CPR, 0);
bwang 0:bac9c3a3a6ca 45
bwang 1:7b61790f6be9 46 int adval1, adval2;
bwang 8:314074b56470 47 float ia, ib, ic, alpha, beta, q;
bwang 10:7624146c5945 48 double vq = 0.0, q_integral = 0.0, last_q = 0.0;
bwang 10:7624146c5945 49 float throttle = 0.0f;
bwang 10:7624146c5945 50
bwang 10:7624146c5945 51 int edge_seen = 0, watchdog_divider = 0;
bwang 8:314074b56470 52
bwang 1:7b61790f6be9 53 extern "C" void TIM1_UP_TIM10_IRQHandler(void) {
bwang 8:314074b56470 54 if (TIM1->SR & TIM_SR_UIF) {
bwang 8:314074b56470 55 float p = pos.GetElecPosition() - POS_OFFSET;
bwang 8:314074b56470 56 if (p < 0) p += 2 * PI;
bwang 8:314074b56470 57
bwang 8:314074b56470 58 //float pos_dac = 0.85f * p / (2 * PI) + 0.05f;
bwang 8:314074b56470 59 //DAC->DHR12R2 = (unsigned int) (pos_dac * 4096);
bwang 8:314074b56470 60
bwang 8:314074b56470 61 float sin_p = sinf(p);
bwang 8:314074b56470 62 float cos_p = cosf(p);
bwang 8:314074b56470 63
bwang 4:a6669248ce4d 64 ADC1->CR2 |= 0x40000000;
bwang 4:a6669248ce4d 65 volatile int delay;
bwang 4:a6669248ce4d 66 for (delay = 0; delay < 35; delay++);
bwang 1:7b61790f6be9 67 adval1 = ADC1->DR;
bwang 1:7b61790f6be9 68 adval2 = ADC2->DR;
bwang 8:314074b56470 69
bwang 8:314074b56470 70 ia = ((float) adval1 / 4096.0f * AVDD - I_OFFSET) / I_SCALE;
bwang 8:314074b56470 71 ib = ((float) adval2 / 4096.0f * AVDD - I_OFFSET) / I_SCALE;
bwang 8:314074b56470 72 ic = -ia - ib;
bwang 8:314074b56470 73
bwang 8:314074b56470 74 float u = ib;
bwang 8:314074b56470 75 float v = ic;
bwang 8:314074b56470 76
bwang 8:314074b56470 77 alpha = u;
bwang 8:314074b56470 78 beta = 1 / sqrtf(3.0f) * u + 2 / sqrtf(3.0f) * v;
bwang 8:314074b56470 79
bwang 8:314074b56470 80 q = -alpha * sin_p - beta * cos_p;
bwang 8:314074b56470 81
bwang 14:10743610ecb5 82 float throttle_scaler;
bwang 14:10743610ecb5 83
bwang 14:10743610ecb5 84 if (throttle_in.read() == 0) {
bwang 14:10743610ecb5 85 throttle_scaler = 0.0f;
bwang 11:825203ff4371 86 en = 0;
bwang 11:825203ff4371 87 } else {
bwang 14:10743610ecb5 88 throttle_scaler = 1.0f;
bwang 11:825203ff4371 89 en = 1;
bwang 11:825203ff4371 90 }
bwang 8:314074b56470 91
bwang 10:7624146c5945 92 double q_err = Q_REF_MAX * (double) throttle_scaler - q;
bwang 14:10743610ecb5 93
bwang 10:7624146c5945 94 //DAC->DHR12R2 = (unsigned int) (q_err * 20 + 2048);
bwang 8:314074b56470 95
bwang 8:314074b56470 96 q_integral += q_err * KI;
bwang 8:314074b56470 97 if (q_integral > INTEGRAL_MAX) q_integral = INTEGRAL_MAX;
bwang 8:314074b56470 98 if (q_integral < -INTEGRAL_MAX) q_integral = -INTEGRAL_MAX;
bwang 8:314074b56470 99
bwang 8:314074b56470 100 vq = KP * q_err + q_integral;
bwang 8:314074b56470 101 if (vq < -1.0f) vq = -1.0f;
bwang 8:314074b56470 102 if (vq > 1.0f) vq = 1.0f;
bwang 14:10743610ecb5 103
bwang 9:4812c9e932ea 104 //DAC->DHR12R2 = (unsigned int) (vq * 2000 + 2048);
bwang 14:10743610ecb5 105
bwang 8:314074b56470 106 *a = 0.5f + 0.5f * vq * sinf(p);
bwang 8:314074b56470 107 *b = 0.5f + 0.5f * vq * sinf(p + 2 * PI / 3);
bwang 8:314074b56470 108 *c = 0.5f + 0.5f * vq * sinf(p - 2 * PI / 3);
bwang 1:7b61790f6be9 109 }
bwang 1:7b61790f6be9 110 TIM1->SR = 0x00;
bwang 1:7b61790f6be9 111 }
bwang 10:7624146c5945 112
bwang 8:314074b56470 113 int main() {
bwang 1:7b61790f6be9 114 //Enable clocks for GPIOs
bwang 1:7b61790f6be9 115 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN;
bwang 1:7b61790f6be9 116 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN;
bwang 1:7b61790f6be9 117 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOCEN;
bwang 1:7b61790f6be9 118
bwang 1:7b61790f6be9 119 RCC->APB2ENR |= RCC_APB2ENR_TIM1EN; //enable TIM1 clock
bwang 1:7b61790f6be9 120
bwang 1:7b61790f6be9 121 a = new FastPWM(PWMA);
bwang 1:7b61790f6be9 122 b = new FastPWM(PWMB);
bwang 1:7b61790f6be9 123 c = new FastPWM(PWMC);
bwang 1:7b61790f6be9 124
bwang 1:7b61790f6be9 125 NVIC_EnableIRQ(TIM1_UP_TIM10_IRQn); //Enable TIM1 IRQ
bwang 1:7b61790f6be9 126
bwang 1:7b61790f6be9 127 TIM1->DIER |= TIM_DIER_UIE; //enable update interrupt
bwang 8:314074b56470 128 //TIM1->CR1 = 0x40; //CMS = 10, interrupt only when counting up
bwang 1:7b61790f6be9 129 TIM1->CR1 |= TIM_CR1_ARPE; //autoreload on,
bwang 1:7b61790f6be9 130 TIM1->RCR |= 0x01; //update event once per up/down count of tim1
bwang 1:7b61790f6be9 131 TIM1->EGR |= TIM_EGR_UG;
bwang 1:7b61790f6be9 132
bwang 1:7b61790f6be9 133 TIM1->PSC = 0x00; //no prescaler, timer counts up in sync with the peripheral clock
bwang 8:314074b56470 134 TIM1->ARR = 0x2EE0;
bwang 8:314074b56470 135 //TIM1->ARR = 0x1770; //15 Khz
bwang 1:7b61790f6be9 136 TIM1->CCER |= ~(TIM_CCER_CC1NP); //Interupt when low side is on.
bwang 1:7b61790f6be9 137 TIM1->CR1 |= TIM_CR1_CEN;
bwang 1:7b61790f6be9 138
bwang 10:7624146c5945 139 TIM5->CR1 |= TIM_CR1_ARPE;
bwang 10:7624146c5945 140 TIM5->EGR |= TIM_EGR_UG;
bwang 10:7624146c5945 141 TIM5->PSC = 0x00;
bwang 10:7624146c5945 142 TIM5->ARR = 0xFFFFFFFF;
bwang 10:7624146c5945 143 TIM5->CR1 |= TIM_CR1_CEN;
bwang 10:7624146c5945 144
bwang 1:7b61790f6be9 145 //ADC Setup
bwang 1:7b61790f6be9 146 RCC->APB2ENR |= RCC_APB2ENR_ADC1EN; // clock for ADC1
bwang 1:7b61790f6be9 147 RCC->APB2ENR |= RCC_APB2ENR_ADC2EN; // clock for ADC2
bwang 1:7b61790f6be9 148
bwang 1:7b61790f6be9 149 ADC->CCR = 0x00000006; //Regular simultaneous mode, 3 channels
bwang 1:7b61790f6be9 150
bwang 1:7b61790f6be9 151 ADC1->CR2 |= ADC_CR2_ADON; //ADC1 on
bwang 1:7b61790f6be9 152 ADC1->SQR3 = 0x0000004; //PA_4 as ADC1, sequence 0
bwang 0:bac9c3a3a6ca 153
bwang 1:7b61790f6be9 154 ADC2->CR2 |= ADC_CR2_ADON; //ADC2 ON
bwang 1:7b61790f6be9 155 ADC2->SQR3 = 0x00000008; //PB_0 as ADC2, sequence 1
bwang 1:7b61790f6be9 156
bwang 1:7b61790f6be9 157 GPIOA->MODER |= (1 << 8);
bwang 1:7b61790f6be9 158 GPIOA->MODER |= (1 << 9);
bwang 1:7b61790f6be9 159
bwang 1:7b61790f6be9 160 GPIOA->MODER |= (1 << 2);
bwang 1:7b61790f6be9 161 GPIOA->MODER |= (1 << 3);
bwang 1:7b61790f6be9 162
bwang 1:7b61790f6be9 163 GPIOA->MODER |= (1 << 0);
bwang 1:7b61790f6be9 164 GPIOA->MODER |= (1 << 1);
bwang 1:7b61790f6be9 165
bwang 1:7b61790f6be9 166 GPIOB->MODER |= (1 << 0);
bwang 1:7b61790f6be9 167 GPIOB->MODER |= (1 << 1);
bwang 1:7b61790f6be9 168
bwang 1:7b61790f6be9 169 GPIOC->MODER |= (1 << 2);
bwang 1:7b61790f6be9 170 GPIOC->MODER |= (1 << 3);
bwang 1:7b61790f6be9 171
bwang 1:7b61790f6be9 172 //DAC setup
bwang 1:7b61790f6be9 173 RCC->APB1ENR |= 0x20000000;
bwang 1:7b61790f6be9 174 DAC->CR |= DAC_CR_EN2;
bwang 1:7b61790f6be9 175
bwang 1:7b61790f6be9 176 GPIOA->MODER |= (1 << 10);
bwang 1:7b61790f6be9 177 GPIOA->MODER |= (1 << 11);
bwang 1:7b61790f6be9 178
bwang 8:314074b56470 179 *a = 0.0f;
bwang 8:314074b56470 180 *b = 0.0f;
bwang 8:314074b56470 181 *c = 0.0f;
bwang 2:eabe8feaaabb 182
bwang 8:314074b56470 183 en = 1;
bwang 0:bac9c3a3a6ca 184
bwang 14:10743610ecb5 185 throttle_in.mode(PullUp);
bwang 10:7624146c5945 186
bwang 0:bac9c3a3a6ca 187 for (;;) {
bwang 0:bac9c3a3a6ca 188 }
bwang 0:bac9c3a3a6ca 189 }