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Fork of Impedance_Fast_Circuitry by
Diff: adc.cpp
- Revision:
- 48:29f14bc30ba6
- Parent:
- 47:54fafe151669
- Child:
- 49:4dcf4717a8bb
--- a/adc.cpp Sat Jan 31 16:44:40 2015 +0000 +++ b/adc.cpp Sat Jan 31 18:38:17 2015 +0000 @@ -2,7 +2,7 @@ /* TODO: remove interrupt handlers - add calibration + finish calibration change clock speed Possible causes of the triggering problem: @@ -30,8 +30,9 @@ SIM_SCGC3 |= SIM_SCGC3_ADC1_MASK; // Set ADC hardware trigger to PDB0 - SIM_SOPT7 = SIM_SOPT7_ADC0TRGSEL(0); - SIM_SOPT7 = SIM_SOPT7_ADC1TRGSEL(0); + SIM_SOPT7 = SIM_SOPT7_ADC0TRGSEL(0); // Select triggering by PDB and select pre-trigger A + SIM_SOPT7 = SIM_SOPT7_ADC1TRGSEL(0); // Select triggering by PDB and select pre-trigger A + debug.printf("SIM_SOPT7: 0x%08x\r\n",SIM_SOPT7); //(0x00000000) // Setup Configuration Register 1 ADC0_CFG1 = 0; // clear register @@ -111,17 +112,17 @@ ADC1_SC2 |= ADC_SC2_ADTRG_MASK; // select hardware trigger now that calibration is complete // Setup Status and Control Register 1A - ADC0_SC1A = 0; // clear register - ADC0_SC1A &= ~ADC_SC1_DIFF_MASK; // select single-ended mode - ADC0_SC1A |= ADC_SC1_AIEN_MASK; // enable interrupt (for debugging) - ADC0_SC1A |= ADC_SC1_ADCH(13); // select channel 13 + ADC0_SC1B = 0; // clear register + ADC0_SC1B &= ~ADC_SC1_DIFF_MASK; // select single-ended mode + ADC0_SC1B |= ADC_SC1_AIEN_MASK; // enable interrupt (for debugging) + ADC0_SC1B |= ADC_SC1_ADCH(13); // select channel 13 ADC1_SC1A = 0; // clear register ADC1_SC1A &= ~ADC_SC1_DIFF_MASK; // select single-ended mode ADC1_SC1A |= ADC_SC1_AIEN_MASK; // enable interrupt (for debugging) ADC1_SC1A |= ADC_SC1_ADCH(13); // select channel 13 // Check if ADC is finished initializing TODO: This part doesn't seem right, but I did it according to 871 - while( (ADC0_SC1A&ADC_SC1_COCO_MASK)) {} + while( (ADC0_SC1B&ADC_SC1_COCO_MASK)) {} gain = ADC0_RA; // read the register to clear SC1A[COCO] while( (ADC1_SC1A&ADC_SC1_COCO_MASK)) {} gain = ADC1_RA; // read the register to clear SC1A[COCO]