Diff: adc.cpp

Revision:

49:4dcf4717a8bb

Parent:

48:29f14bc30ba6

Child:

50:33524a27e08c

--- a/adc.cpp	Sat Jan 31 18:38:17 2015 +0000
+++ b/adc.cpp	Sat Jan 31 19:16:22 2015 +0000
@@ -52,6 +52,9 @@
     ADC0_CFG2 = 0; // clear register
     ADC0_CFG2 |= ADC_CFG2_ADHSC_MASK ;  // select high-speed conversion
     ADC0_CFG2 &= ~ADC_CFG2_MUXSEL_MASK; // select a channels    
+    ADC1_CFG2 = 0; // clear register
+    ADC1_CFG2 |= ADC_CFG2_ADHSC_MASK ;  // select high-speed conversion
+    ADC1_CFG2 |= ADC_CFG2_MUXSEL_MASK; // select b channels 
     
     // Setup Status and Control Register 2 
     ADC0_SC2 = 0;                    // clear register
@@ -111,21 +114,21 @@
     ADC0_SC2 |= ADC_SC2_ADTRG_MASK; // select hardware trigger now that calibration is complete
     ADC1_SC2 |= ADC_SC2_ADTRG_MASK; // select hardware trigger now that calibration is complete
     
-    // Setup Status and Control Register 1A 
+    // Setup Status and Control Register 1B 
     ADC0_SC1B = 0; // clear register
     ADC0_SC1B &= ~ADC_SC1_DIFF_MASK; // select single-ended mode
     ADC0_SC1B |= ADC_SC1_AIEN_MASK;  // enable interrupt (for debugging)
     ADC0_SC1B |= ADC_SC1_ADCH(13);   // select channel 13
-    ADC1_SC1A = 0; // clear register
-    ADC1_SC1A &= ~ADC_SC1_DIFF_MASK; // select single-ended mode
-    ADC1_SC1A |= ADC_SC1_AIEN_MASK;  // enable interrupt (for debugging)
-    ADC1_SC1A |= ADC_SC1_ADCH(13);   // select channel 13
+    ADC1_SC1B = 0; // clear register
+    ADC1_SC1B &= ~ADC_SC1_DIFF_MASK; // select single-ended mode
+    ADC1_SC1B |= ADC_SC1_AIEN_MASK;  // enable interrupt (for debugging)
+    ADC1_SC1B |= ADC_SC1_ADCH(14);   // select channel 14
     
     // Check if ADC is finished initializing  TODO:  This part doesn't seem right, but I did it according to 871
     while( (ADC0_SC1B&ADC_SC1_COCO_MASK)) {}
-    gain = ADC0_RA; // read the register to clear SC1A[COCO]
-    while( (ADC1_SC1A&ADC_SC1_COCO_MASK)) {}
-    gain = ADC1_RA; // read the register to clear SC1A[COCO]
+    gain = ADC0_RB; // read the register to clear SC1A[COCO]
+    while( (ADC1_SC1B&ADC_SC1_COCO_MASK)) {}
+    gain = ADC1_RB; // read the register to clear SC1A[COCO]
     
     
     // green indicating calibration and initialization complete
@@ -141,6 +144,15 @@
     debug.printf("ADC0_SC2:  %08x\r\n",ADC0_SC2);   //(0x00000044)
     debug.printf("ADC0_SC3:  %08x\r\n\n",ADC0_SC3); //(0x00000000)
     
+    debug.printf("ADC1_SC1a: %08x\r\n",ADC1_SC1A);  //(0x0000004d)
+    debug.printf("ADC1_SC1b: %08x\r\n",ADC1_SC1B);  //(0x0000001f)
+    debug.printf("ADC1_CFG1: %08x\r\n",ADC1_CFG1);  //(0x0000000c)
+    debug.printf("ADC1_CFG2: %08x\r\n",ADC1_CFG2);  //(0x00000004)
+    debug.printf("ADC1_RA:   %08x\r\n",ADC1_RA);    //(0x00000000)
+    debug.printf("ADC1_RB:   %08x\r\n",ADC1_RB);    //(0x00000000)
+    debug.printf("ADC1_SC2:  %08x\r\n",ADC1_SC2);   //(0x00000044)
+    debug.printf("ADC1_SC3:  %08x\r\n\n",ADC1_SC3); //(0x00000000)
+    
     // Enable the ISR vector
     //NVIC_SetVector(ADC0_IRQn, (uint32_t)&ADC0_IRQHandler);
     //NVIC_EnableIRQ(ADC0_IRQn);
@@ -159,8 +171,8 @@
     ADC1_SC2 &= ~ADC_SC2_ADTRG_MASK;
     
     // start ADC conversion (SW trigger)
-    ADC0_SC1A |= ADC_SC1_ADCH(13);   // write to SC1A causing a trigger
-    ADC1_SC1A |= ADC_SC1_ADCH(14);   // write to SC1A causing a trigger
+    ADC0_SC1B |= ADC_SC1_ADCH(13);   // write to SC1B causing a trigger
+    ADC1_SC1B |= ADC_SC1_ADCH(14);   // write to SC1B causing a trigger
 }
 
 void adc_stop() {
@@ -178,8 +190,8 @@
     ADC1_SC3 &= ~ADC_SC3_ADCO_MASK;  // single conversion mode
     ADC0_SC2 &= ~ADC_SC2_ADTRG_MASK; // set ADC to software trigger
     ADC1_SC2 &= ~ADC_SC2_ADTRG_MASK; // set ADC to software trigger
-    ADC0_SC1A |= ADC_SC1_ADCH(13);   // write to SC1A causing a trigger
-    ADC1_SC1A |= ADC_SC1_ADCH(14);   // write to SC1A causing a trigger
+    ADC0_SC1B |= ADC_SC1_ADCH(13);   // write to SC1A causing a trigger
+    ADC1_SC1B |= ADC_SC1_ADCH(14);   // write to SC1A causing a trigger
 }
 
 void ADC0_IRQHandler() {