Jared Baxter / Mbed 2 deprecated Impedance_Fast_Circuitry_print_V_I

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Dependencies:   mbed-dsp mbed

Fork of Impedance_Fast_Circuitry by Jared Baxter

adc.cpp@48:29f14bc30ba6, 2015-01-31 (annotated)

Committer:
timmey9
Date:
Sat Jan 31 18:38:17 2015 +0000
Revision:
48:29f14bc30ba6
Parent:
47:54fafe151669
Child:
49:4dcf4717a8bb
Works if you don't do single sample first.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
timmey9 39:82dc3daecf32 1 #include "adc.h"
timmey9 45:d591d138cdeb 2
timmey9 44:41c262caf898 3 /*
timmey9 44:41c262caf898 4 TODO: remove interrupt handlers
timmey9 48:29f14bc30ba6 5 finish calibration
timmey9 45:d591d138cdeb 6 change clock speed
timmey9 44:41c262caf898 7
timmey9 45:d591d138cdeb 8 Possible causes of the triggering problem:
timmey9 45:d591d138cdeb 9 more multiplexing somehow?
timmey9 45:d591d138cdeb 10 does the ADC interrupt need to be enabled?
timmey9 45:d591d138cdeb 11 clock speed?
timmey9 45:d591d138cdeb 12 hardware/software trigger
timmey9 45:d591d138cdeb 13 channel A or B?
timmey9 45:d591d138cdeb 14 single vs continuous mode
timmey9 45:d591d138cdeb 15 does asynchronous clock have to do with this?
timmey9 44:41c262caf898 16 */
timmey9 45:d591d138cdeb 17 DigitalOut toggle1(PTC16);
timmey9 45:d591d138cdeb 18 DigitalOut green(LED_GREEN);
timmey9 45:d591d138cdeb 19 DigitalOut red(LED_RED);
timmey9 45:d591d138cdeb 20 Serial debug(USBTX,USBRX);
timmey9 39:82dc3daecf32 21
timmey9 45:d591d138cdeb 22 void adc_init()
timmey9 39:82dc3daecf32 23 {
timmey9 45:d591d138cdeb 24 // red, indicating now ready
timmey9 45:d591d138cdeb 25 red = 0;
timmey9 45:d591d138cdeb 26 green = 1;
timmey9 45:d591d138cdeb 27
timmey9 39:82dc3daecf32 28 // Turn on the ADC0 and ADC1 clocks
timmey9 39:82dc3daecf32 29 SIM_SCGC6 |= SIM_SCGC6_ADC0_MASK;
timmey9 39:82dc3daecf32 30 SIM_SCGC3 |= SIM_SCGC3_ADC1_MASK;
timmey9 40:bd6d8c35e822 31
timmey9 45:d591d138cdeb 32 // Set ADC hardware trigger to PDB0
timmey9 48:29f14bc30ba6 33 SIM_SOPT7 = SIM_SOPT7_ADC0TRGSEL(0); // Select triggering by PDB and select pre-trigger A
timmey9 48:29f14bc30ba6 34 SIM_SOPT7 = SIM_SOPT7_ADC1TRGSEL(0); // Select triggering by PDB and select pre-trigger A
timmey9 48:29f14bc30ba6 35 debug.printf("SIM_SOPT7: 0x%08x\r\n",SIM_SOPT7); //(0x00000000)
timmey9 39:82dc3daecf32 36
timmey9 45:d591d138cdeb 37 // Setup Configuration Register 1
timmey9 45:d591d138cdeb 38 ADC0_CFG1 = 0; // clear register
timmey9 45:d591d138cdeb 39 ADC0_CFG1 |= ADC_CFG1_ADICLK(0); // select bus clock
timmey9 45:d591d138cdeb 40 ADC0_CFG1 |= ADC_CFG1_MODE(3); // select 16-bit 2's complement output
timmey9 45:d591d138cdeb 41 ADC0_CFG1 |= ADC_CFG1_ADIV(0); // select short sample time
timmey9 45:d591d138cdeb 42 ADC0_CFG1 &= ~ADC_CFG1_ADLSMP_MASK; // select short sample time
timmey9 45:d591d138cdeb 43 ADC0_CFG1 &= ~ADC_CFG1_ADLPC_MASK; // select normal power configuration
timmey9 46:a015ebf4663b 44 ADC1_CFG1 = 0; // clear register
timmey9 46:a015ebf4663b 45 ADC1_CFG1 |= ADC_CFG1_ADICLK(0); // select bus clock
timmey9 46:a015ebf4663b 46 ADC1_CFG1 |= ADC_CFG1_MODE(3); // select 16-bit 2's complement output
timmey9 46:a015ebf4663b 47 ADC1_CFG1 |= ADC_CFG1_ADIV(0); // select short sample time
timmey9 46:a015ebf4663b 48 ADC1_CFG1 &= ~ADC_CFG1_ADLSMP_MASK; // select short sample time
timmey9 46:a015ebf4663b 49 ADC1_CFG1 &= ~ADC_CFG1_ADLPC_MASK; // select normal power configuration
timmey9 45:d591d138cdeb 50
timmey9 45:d591d138cdeb 51 // Setup Configuration Register 2
timmey9 45:d591d138cdeb 52 ADC0_CFG2 = 0; // clear register
timmey9 47:54fafe151669 53 ADC0_CFG2 |= ADC_CFG2_ADHSC_MASK ; // select high-speed conversion
timmey9 45:d591d138cdeb 54 ADC0_CFG2 &= ~ADC_CFG2_MUXSEL_MASK; // select a channels
timmey9 39:82dc3daecf32 55
timmey9 45:d591d138cdeb 56 // Setup Status and Control Register 2
timmey9 47:54fafe151669 57 ADC0_SC2 = 0; // clear register
timmey9 47:54fafe151669 58 ADC0_SC2 |= ADC_SC2_REFSEL(0); // select external voltage reference
timmey9 47:54fafe151669 59 ADC0_SC2 |= ADC_SC2_DMAEN_MASK; // enable DMA
timmey9 45:d591d138cdeb 60 ADC0_SC2 &= ~ADC_SC2_ADTRG_MASK; // select software trigger until calibration is complete
timmey9 47:54fafe151669 61 ADC1_SC2 = 0; // clear register
timmey9 47:54fafe151669 62 ADC1_SC2 |= ADC_SC2_REFSEL(0); // select external voltage reference
timmey9 47:54fafe151669 63 ADC1_SC2 |= ADC_SC2_DMAEN_MASK; // enable DMA
timmey9 46:a015ebf4663b 64 ADC1_SC2 &= ~ADC_SC2_ADTRG_MASK; // select software trigger until calibration is complete
timmey9 45:d591d138cdeb 65
timmey9 45:d591d138cdeb 66 // Setup Status and Control Register 3
timmey9 45:d591d138cdeb 67 ADC0_SC3 = 0; // Hardware Average set to 4 samples averaged
timmey9 45:d591d138cdeb 68 // Hardware Average Disabled
timmey9 45:d591d138cdeb 69 // select single conversion mode
timmey9 46:a015ebf4663b 70 ADC1_SC3 = 0; // Hardware Average set to 4 samples averaged
timmey9 46:a015ebf4663b 71 // Hardware Average Disabled
timmey9 46:a015ebf4663b 72 // select single conversion mode
timmey9 39:82dc3daecf32 73
timmey9 45:d591d138cdeb 74 // calibrate the ADC
timmey9 45:d591d138cdeb 75 ADC0_SC3 |= ADC_SC3_CAL_MASK; // start calibration
timmey9 45:d591d138cdeb 76 while(ADC0_SC3&ADC_SC3_CALF_MASK) {} // wait for calibration to complete
timmey9 46:a015ebf4663b 77 ADC1_SC3 |= ADC_SC3_CAL_MASK; // start calibration
timmey9 46:a015ebf4663b 78 while(ADC1_SC3&ADC_SC3_CALF_MASK) {} // wait for calibration to complete
timmey9 46:a015ebf4663b 79
timmey9 45:d591d138cdeb 80
timmey9 45:d591d138cdeb 81 // calculate the gains (see user manual page 864)
timmey9 45:d591d138cdeb 82 int16_t gain = (ADC0_CLP0+ADC0_CLP1+ADC0_CLP2+ADC0_CLP3+ADC0_CLP4+ADC0_CLPS);
timmey9 45:d591d138cdeb 83 gain = (gain>>1); // divide by 2
timmey9 45:d591d138cdeb 84 gain |= 0x8000; // set the MSB
timmey9 45:d591d138cdeb 85 ADC0_PG = gain;
timmey9 45:d591d138cdeb 86
timmey9 46:a015ebf4663b 87 gain = (ADC1_CLP0+ADC1_CLP1+ADC1_CLP2+ADC1_CLP3+ADC1_CLP4+ADC1_CLPS);
timmey9 46:a015ebf4663b 88 gain = (gain>>1); // divide by 2
timmey9 46:a015ebf4663b 89 gain |= 0x8000; // set the MSB
timmey9 46:a015ebf4663b 90 ADC1_PG = gain;
timmey9 46:a015ebf4663b 91
timmey9 45:d591d138cdeb 92 gain = (ADC0_CLM0+ADC0_CLM1+ADC0_CLM2+ADC0_CLM3+ADC0_CLM4+ADC0_CLMS);
timmey9 45:d591d138cdeb 93 gain = (gain>>1); // divide by 2
timmey9 45:d591d138cdeb 94 gain |= 0x8000; // set the MSB
timmey9 45:d591d138cdeb 95 ADC0_MG = gain;
timmey9 39:82dc3daecf32 96
timmey9 46:a015ebf4663b 97 gain = (ADC1_CLM0+ADC1_CLM1+ADC1_CLM2+ADC1_CLM3+ADC1_CLM4+ADC1_CLMS);
timmey9 46:a015ebf4663b 98 gain = (gain>>1); // divide by 2
timmey9 46:a015ebf4663b 99 gain |= 0x8000; // set the MSB
timmey9 46:a015ebf4663b 100 ADC1_MG = gain;
timmey9 46:a015ebf4663b 101
timmey9 45:d591d138cdeb 102 ADC0_SC3 &= ~ADC_SC3_CAL_MASK; // stop calibration
timmey9 46:a015ebf4663b 103 ADC1_SC3 &= ~ADC_SC3_CAL_MASK; // stop calibration
timmey9 45:d591d138cdeb 104
timmey9 45:d591d138cdeb 105
timmey9 45:d591d138cdeb 106
timmey9 45:d591d138cdeb 107 // yellow indicating calibration complete
timmey9 45:d591d138cdeb 108 red = 0;
timmey9 45:d591d138cdeb 109 green = 0;
timmey9 45:d591d138cdeb 110
timmey9 45:d591d138cdeb 111 ADC0_SC2 |= ADC_SC2_ADTRG_MASK; // select hardware trigger now that calibration is complete
timmey9 46:a015ebf4663b 112 ADC1_SC2 |= ADC_SC2_ADTRG_MASK; // select hardware trigger now that calibration is complete
timmey9 45:d591d138cdeb 113
timmey9 45:d591d138cdeb 114 // Setup Status and Control Register 1A
timmey9 48:29f14bc30ba6 115 ADC0_SC1B = 0; // clear register
timmey9 48:29f14bc30ba6 116 ADC0_SC1B &= ~ADC_SC1_DIFF_MASK; // select single-ended mode
timmey9 48:29f14bc30ba6 117 ADC0_SC1B |= ADC_SC1_AIEN_MASK; // enable interrupt (for debugging)
timmey9 48:29f14bc30ba6 118 ADC0_SC1B |= ADC_SC1_ADCH(13); // select channel 13
timmey9 46:a015ebf4663b 119 ADC1_SC1A = 0; // clear register
timmey9 46:a015ebf4663b 120 ADC1_SC1A &= ~ADC_SC1_DIFF_MASK; // select single-ended mode
timmey9 46:a015ebf4663b 121 ADC1_SC1A |= ADC_SC1_AIEN_MASK; // enable interrupt (for debugging)
timmey9 46:a015ebf4663b 122 ADC1_SC1A |= ADC_SC1_ADCH(13); // select channel 13
timmey9 45:d591d138cdeb 123
timmey9 45:d591d138cdeb 124 // Check if ADC is finished initializing TODO: This part doesn't seem right, but I did it according to 871
timmey9 48:29f14bc30ba6 125 while( (ADC0_SC1B&ADC_SC1_COCO_MASK)) {}
timmey9 45:d591d138cdeb 126 gain = ADC0_RA; // read the register to clear SC1A[COCO]
timmey9 46:a015ebf4663b 127 while( (ADC1_SC1A&ADC_SC1_COCO_MASK)) {}
timmey9 46:a015ebf4663b 128 gain = ADC1_RA; // read the register to clear SC1A[COCO]
timmey9 45:d591d138cdeb 129
timmey9 45:d591d138cdeb 130
timmey9 45:d591d138cdeb 131 // green indicating calibration and initialization complete
timmey9 45:d591d138cdeb 132 red = 1;
timmey9 45:d591d138cdeb 133 green = 0;
timmey9 45:d591d138cdeb 134
timmey9 45:d591d138cdeb 135 debug.printf("ADC0_SC1a: %08x\r\n",ADC0_SC1A); //(0x0000004d)
timmey9 45:d591d138cdeb 136 debug.printf("ADC0_SC1b: %08x\r\n",ADC0_SC1B); //(0x0000001f)
timmey9 45:d591d138cdeb 137 debug.printf("ADC0_CFG1: %08x\r\n",ADC0_CFG1); //(0x0000000c)
timmey9 45:d591d138cdeb 138 debug.printf("ADC0_CFG2: %08x\r\n",ADC0_CFG2); //(0x00000004)
timmey9 45:d591d138cdeb 139 debug.printf("ADC0_RA: %08x\r\n",ADC0_RA); //(0x00000000)
timmey9 45:d591d138cdeb 140 debug.printf("ADC0_RB: %08x\r\n",ADC0_RB); //(0x00000000)
timmey9 45:d591d138cdeb 141 debug.printf("ADC0_SC2: %08x\r\n",ADC0_SC2); //(0x00000044)
timmey9 45:d591d138cdeb 142 debug.printf("ADC0_SC3: %08x\r\n\n",ADC0_SC3); //(0x00000000)
timmey9 45:d591d138cdeb 143
timmey9 40:bd6d8c35e822 144 // Enable the ISR vector
timmey9 47:54fafe151669 145 //NVIC_SetVector(ADC0_IRQn, (uint32_t)&ADC0_IRQHandler);
timmey9 47:54fafe151669 146 //NVIC_EnableIRQ(ADC0_IRQn);
timmey9 40:bd6d8c35e822 147 }
timmey9 40:bd6d8c35e822 148
timmey9 41:3e0623d81b9a 149 void adc_start() {
timmey9 40:bd6d8c35e822 150 // reset DMA
timmey9 45:d591d138cdeb 151 dma_reset();
timmey9 40:bd6d8c35e822 152
timmey9 40:bd6d8c35e822 153 // set ADC to continuous mode
timmey9 40:bd6d8c35e822 154 ADC0_SC3 |= ADC_SC3_ADCO_MASK;
timmey9 46:a015ebf4663b 155 ADC1_SC3 |= ADC_SC3_ADCO_MASK;
timmey9 45:d591d138cdeb 156
timmey9 45:d591d138cdeb 157 // set ADC to software trigger
timmey9 47:54fafe151669 158 ADC0_SC2 &= ~ADC_SC2_ADTRG_MASK;
timmey9 46:a015ebf4663b 159 ADC1_SC2 &= ~ADC_SC2_ADTRG_MASK;
timmey9 40:bd6d8c35e822 160
timmey9 40:bd6d8c35e822 161 // start ADC conversion (SW trigger)
timmey9 46:a015ebf4663b 162 ADC0_SC1A |= ADC_SC1_ADCH(13); // write to SC1A causing a trigger
timmey9 46:a015ebf4663b 163 ADC1_SC1A |= ADC_SC1_ADCH(14); // write to SC1A causing a trigger
timmey9 40:bd6d8c35e822 164 }
timmey9 40:bd6d8c35e822 165
timmey9 41:3e0623d81b9a 166 void adc_stop() {
timmey9 45:d591d138cdeb 167 // set ADC to hardware trigger
timmey9 45:d591d138cdeb 168 ADC0_SC2 |= ADC_SC2_ADTRG_MASK;
timmey9 46:a015ebf4663b 169 ADC1_SC2 |= ADC_SC2_ADTRG_MASK;
timmey9 45:d591d138cdeb 170
timmey9 45:d591d138cdeb 171 // set to single conversion mode effectively stopping the ADC unless a timer triggers the ADC
timmey9 45:d591d138cdeb 172 ADC0_SC3 &= ~ADC_SC3_ADCO_MASK;
timmey9 46:a015ebf4663b 173 ADC1_SC3 &= ~ADC_SC3_ADCO_MASK;
timmey9 45:d591d138cdeb 174 }
timmey9 45:d591d138cdeb 175
timmey9 45:d591d138cdeb 176 void adc_single_sample() {
timmey9 45:d591d138cdeb 177 ADC0_SC3 &= ~ADC_SC3_ADCO_MASK; // single conversion mode
timmey9 46:a015ebf4663b 178 ADC1_SC3 &= ~ADC_SC3_ADCO_MASK; // single conversion mode
timmey9 45:d591d138cdeb 179 ADC0_SC2 &= ~ADC_SC2_ADTRG_MASK; // set ADC to software trigger
timmey9 46:a015ebf4663b 180 ADC1_SC2 &= ~ADC_SC2_ADTRG_MASK; // set ADC to software trigger
timmey9 45:d591d138cdeb 181 ADC0_SC1A |= ADC_SC1_ADCH(13); // write to SC1A causing a trigger
timmey9 46:a015ebf4663b 182 ADC1_SC1A |= ADC_SC1_ADCH(14); // write to SC1A causing a trigger
timmey9 40:bd6d8c35e822 183 }
timmey9 40:bd6d8c35e822 184
timmey9 40:bd6d8c35e822 185 void ADC0_IRQHandler() {
timmey9 47:54fafe151669 186
timmey9 45:d591d138cdeb 187 toggle1 = !toggle1;
timmey9 39:82dc3daecf32 188 }