Aidan Walton / SGTL5000 Featured

Library to control and transfer data from NXP SGTL5000. As used on the Teensy Audio Shield. It uses DMA to transfer I2S FIFO data.

The Library now supports dual codecs. Allowing all 4 channels of the Teensy I2S interface to RX and TX data to separate SGTL5000 devices.

The ISR routines that handles pointer swaps for double buffering has been fully coded in assembler to reduce overhead and now takes < 800nS per FIFO transfer when using all 4 channels.

Support added for all typical sample rates and system Clock speeds of 96Mhz or 120Mhz.

Pause and Resume functions added to allow quick and simple suppression of IRQs and stream halting and restart. This required software triggered IRQ, in order to ensure accurate word sync control.

sgtl5000.h@10:49bb33f71d32, 2017-09-26 (annotated)

Committer:
aidan1971
Date:
Tue Sep 26 23:03:32 2017 +0000
Revision:
10:49bb33f71d32
Parent:
9:40e0ff8c2ba2
Child:
11:392c09372ae1
Significant re-work.; The library now supports dual codecs. Using channel 0 and channel 1 of the I2S silicon of Teensy 3.2.; replaced c code with inline assembler reduces time of pointer swaps < 800nS.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
aidan1971 3:62c03088f256 1 /*!
aidan1971 0:8f28f25e3435 2 @ author Aidan Walton, aidan.walton@gmail.com
aidan1971 0:8f28f25e3435 3
aidan1971 0:8f28f25e3435 4 @section LICENSE
aidan1971 0:8f28f25e3435 5 * Permission is hereby granted, free of charge, to any person obtaining a copy
aidan1971 0:8f28f25e3435 6 * of this software and associated documentation files (the "Software"), to deal
aidan1971 0:8f28f25e3435 7 * in the Software without restriction, including without limitation the rights
aidan1971 0:8f28f25e3435 8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
aidan1971 0:8f28f25e3435 9 * copies of the Software, and to permit persons to whom the Software is
aidan1971 0:8f28f25e3435 10 * furnished to do so, subject to the following conditions:
aidan1971 0:8f28f25e3435 11 *
aidan1971 0:8f28f25e3435 12 * The above copyright notice, development funding notice, and this permission
aidan1971 0:8f28f25e3435 13 * notice shall be included in all copies or substantial portions of the Software.
aidan1971 0:8f28f25e3435 14 *
aidan1971 0:8f28f25e3435 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
aidan1971 0:8f28f25e3435 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
aidan1971 0:8f28f25e3435 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
aidan1971 0:8f28f25e3435 18 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
aidan1971 0:8f28f25e3435 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
aidan1971 0:8f28f25e3435 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
aidan1971 0:8f28f25e3435 21 * THE SOFTWARE.
aidan1971 0:8f28f25e3435 22
aidan1971 0:8f28f25e3435 23 @section DESCRIPTION
aidan1971 0:8f28f25e3435 24 Library for NXP SGTL5000 Codec
aidan1971 0:8f28f25e3435 25 */
aidan1971 0:8f28f25e3435 26
aidan1971 0:8f28f25e3435 27 #ifndef MBED_SGTL5000_H
aidan1971 0:8f28f25e3435 28 #define MBED_SGTL5000_H
aidan1971 0:8f28f25e3435 29
aidan1971 0:8f28f25e3435 30 #include "mbed.h"
aidan1971 0:8f28f25e3435 31 #include "platform.h"
aidan1971 0:8f28f25e3435 32 #include "Callback.h"
aidan1971 0:8f28f25e3435 33 #include "sgtl5000_defs.h"
aidan1971 0:8f28f25e3435 34
aidan1971 10:49bb33f71d32 35
aidan1971 3:62c03088f256 36 /** SGTL5000 namespace
aidan1971 3:62c03088f256 37 */
aidan1971 0:8f28f25e3435 38 namespace SGTL5000
aidan1971 0:8f28f25e3435 39 {
aidan1971 0:8f28f25e3435 40
aidan1971 10:49bb33f71d32 41
aidan1971 3:62c03088f256 42 /*! SGTL5000 codec driver class
aidan1971 3:62c03088f256 43 */
aidan1971 3:62c03088f256 44 /*! Class for NXP SGTL5000 codec instance.
aidan1971 10:49bb33f71d32 45 * Supports dual codecs. One using I2S TX&RX channel_0 the other I2S TX&RX channel_1. The instance created for codec1 (I2S channel_0) is the master, all ctrl functions are synchronous to this master codec.
aidan1971 3:62c03088f256 46 * @code
aidan1971 3:62c03088f256 47 * #include 'SGTL5000.h'
aidan1971 3:62c03088f256 48 *
aidan1971 3:62c03088f256 49 * SGTL5000::SGTL5000 codec(I2C_SDA, I2C_SCL);
aidan1971 3:62c03088f256 50 *
aidan1971 3:62c03088f256 51 * static q31_t *RX_AudioL = NULL;
aidan1971 3:62c03088f256 52 * static q31_t *RX_AudioR = NULL;
aidan1971 3:62c03088f256 53 * static q31_t *TX_AudioL = NULL;
aidan1971 3:62c03088f256 54 * static q31_t *TX_AudioR = NULL;
aidan1971 3:62c03088f256 55 *
aidan1971 3:62c03088f256 56 * const uint32_t I2S_FIFO_BS = 4;
aidan1971 3:62c03088f256 57 *
aidan1971 3:62c03088f256 58 *
aidan1971 3:62c03088f256 59 * uint32_t main()
aidan1971 3:62c03088f256 60 * {
aidan1971 3:62c03088f256 61 * codec.modify_i2c(SGTL5000_ANA_HP_CTRL, 0x18, SGTL5000_ANA_HP_CTRL_HP_VOL_RIGHT_MASK); // Headphone volume control with 0.5 dB steps.0x00 = +12 dB, 0x01 = +11.5 dB, 0x18 = 0 dB,...0x7F = -51.5 dB
aidan1971 3:62c03088f256 62 * codec.modify_i2c(SGTL5000_ANA_HP_CTRL, 0x18, SGTL5000_ANA_HP_CTRL_HP_VOL_LEFT_MASK);
aidan1971 6:4ab5aaeaa064 63 *
aidan1971 3:62c03088f256 64 * codec.attach_SYNC_NB((uint32_t)&I2S_SYNC_ISR);
aidan1971 3:62c03088f256 65 * codec.freq(96);
aidan1971 3:62c03088f256 66 * codec.start_SYNC((uint32_t)&RX_AudioL, (uint32_t)&RX_AudioR, (uint32_t)&TX_AudioL, (uint32_t)&TX_AudioR, I2S_FIFO_BS)
aidan1971 3:62c03088f256 67 * }
aidan1971 3:62c03088f256 68 *
aidan1971 3:62c03088f256 69 * void I2S_SYNC_ISR(void)
aidan1971 3:62c03088f256 70 * {
aidan1971 3:62c03088f256 71 * for(uint32_t i = 0; i < (I2S_FIFO_BS >> 1); ++i)
aidan1971 3:62c03088f256 72 * {
aidan1971 3:62c03088f256 73 * TX_AudioL[i] = RX_AudioL[i];
aidan1971 3:62c03088f256 74 * TX_AudioR[i] = RX_AudioR[i];
aidan1971 3:62c03088f256 75 * }
aidan1971 3:62c03088f256 76 * }
aidan1971 3:62c03088f256 77 @endcode
aidan1971 3:62c03088f256 78 */
aidan1971 0:8f28f25e3435 79 class SGTL5000
aidan1971 0:8f28f25e3435 80
aidan1971 0:8f28f25e3435 81 {
aidan1971 0:8f28f25e3435 82 public:
aidan1971 3:62c03088f256 83 //Constructor
aidan1971 3:62c03088f256 84 /*!
aidan1971 0:8f28f25e3435 85 @brief Create an SGTL5000 object defined on the I2C port using DMA transfers of I2S data. The class is not defined as a singleton, as future development may require
aidan1971 3:62c03088f256 86 multiple instances. However currently it should only be instantiated once. The class is wrapped in the SGTL5000 namespace to avoid collisions with statics
aidan1971 10:49bb33f71d32 87 needed by the ISRs. Only the CODEC using CTRL_ADR0_CS = 0 can be used to manage the I2S setup and data flow, such as sample_rate, attach, start, stop etc. If a second
aidan1971 10:49bb33f71d32 88 CODEC is available then its data flow is locked to the 1st, TX & RX FIFO buffers of both CODECs will be synchronised and only one DMA channel is used to TX data
aidan1971 10:49bb33f71d32 89 to both codecs and one DMA channel to RX data from both codecs.
aidan1971 0:8f28f25e3435 90
aidan1971 0:8f28f25e3435 91 @param i2c_sda i2c Serial data pin (D18 Teensy 3.2 header / PTB3 MK20DX256)
aidan1971 0:8f28f25e3435 92 @param i2c_scl i2c Serial clock pin (D19 Teensy 3.2 header / PTB2 MK20DX256)
aidan1971 0:8f28f25e3435 93 @param i2c_freq Frequency in Hz at which the i2c codec interface clocks data
aidan1971 0:8f28f25e3435 94 @param i2c_ctrl_adr0_cs State on SGTL5000 CTRL_ADR0_CS pin i2c addr = 0n01010(R/W) :R/W = 1 to write R/W = 0 to read, n = 0 pull down / n = 1 pull up on CTRL_ADR0_CS pin of SGTL5000)
aidan1971 10:49bb33f71d32 95 @param _ctrl_IRQn A system IRQ number used to control the codec. All time sensitive commands are elevated to highest IRQ priority using this IRQ number.
aidan1971 10:49bb33f71d32 96 Note: This is only used by the master codec (which is the codec with CS pin LOW). All commands to control data flow must be issued through the master codec object.
aidan1971 10:49bb33f71d32 97 This includes setting sample rate. Both codecs are linked by default at the same rate. Setting the master codecs rate also sets the same rate for the 2nd codec.
aidan1971 10:49bb33f71d32 98 However each codec instance has fully independent access to all the other codec internal features, through its respective object.
aidan1971 0:8f28f25e3435 99
aidan1971 0:8f28f25e3435 100
aidan1971 0:8f28f25e3435 101 // Pin Configs for i2s hardcoded as follows to match Teensy Audio Shield
aidan1971 0:8f28f25e3435 102 i2s_mclk i2s master clock (D11 Teensy 3.2 header / PTC6 MK20DX256)
aidan1971 0:8f28f25e3435 103 i2s_bclk i2s bit clock (D9 Teensy 3.2 header / PTC3 MK20DX256)
aidan1971 0:8f28f25e3435 104 i2s_fs i2s Frame Sync / L/R clock / WordSelect (D23 Teensy 3.2 header / PTC2 MK20DX256)
aidan1971 0:8f28f25e3435 105 i2s_rx i2s tx_data (from bus master perspective) (D22 Teensy 3.2 header / PTC1 MK20DX256)
aidan1971 0:8f28f25e3435 106 i2s_tx i2s rx_data (from bus master perspective) (D13 Teensy 3.2 header /PTC5 MK20DX256)
aidan1971 0:8f28f25e3435 107
aidan1971 0:8f28f25e3435 108 */
aidan1971 10:49bb33f71d32 109 SGTL5000(PinName i2c_sda, PinName i2c_scl, int _i2c_freq = 100000, bool i2c_ctrl_adr0_cs = 0, IRQn _ctrl_IRQn = Reserved109_IRQn);
aidan1971 0:8f28f25e3435 110
aidan1971 3:62c03088f256 111 /*!
aidan1971 3:62c03088f256 112 @brief Read 16bit register of SGTL5000
aidan1971 3:62c03088f256 113 @param reg_addr 16bit address of the codec control register
aidan1971 3:62c03088f256 114 @param data 16bit data to read from the address
aidan1971 3:62c03088f256 115 @param mask 16bit mask applied over the data read from the codec. The final returned value is the register data automatically shifted to the position of the first masked bit.
aidan1971 10:49bb33f71d32 116 @param _i2c_addr Default = 0. If none zero, overrides the address associated with the current object.
aidan1971 3:62c03088f256 117 @returns 0 = register data, -1 = fail
aidan1971 3:62c03088f256 118 */
aidan1971 10:49bb33f71d32 119 int32_t read_i2c(uint32_t reg_addr, uint32_t mask = 0xFFFF, int _i2c_addr = 0);
aidan1971 6:4ab5aaeaa064 120
aidan1971 3:62c03088f256 121 /*!
aidan1971 3:62c03088f256 122 @brief Write 16bit register of SGTL5000
aidan1971 3:62c03088f256 123 @param reg_addr 16bit address of the codec control register
aidan1971 3:62c03088f256 124 @param data 16bit data to write into the address
aidan1971 10:49bb33f71d32 125 @param _i2c_addr Default = 0. If none zero, overrides the address associated with the current object.
aidan1971 3:62c03088f256 126 @returns 0 = success, -1 = fail
aidan1971 3:62c03088f256 127 */
aidan1971 10:49bb33f71d32 128 int32_t write_i2c(uint32_t reg_addr, uint32_t data, int _i2c_addr = 0);
aidan1971 6:4ab5aaeaa064 129
aidan1971 3:62c03088f256 130 /*!
aidan1971 3:62c03088f256 131 @brief Modify masked bits within 16bit register of SGTL5000
aidan1971 3:62c03088f256 132 @param reg_addr 16bit address of the codec control register
aidan1971 3:62c03088f256 133 @param data 16bit data to write into the address
aidan1971 3:62c03088f256 134 @param mask 16bit mask of the bits to modify.
aidan1971 3:62c03088f256 135 The function automatically shifts the data to the position of the first masked bit.
aidan1971 10:49bb33f71d32 136 @param _i2c_addr Default = 0. If none zero, overrides the address associated with the current object.
aidan1971 3:62c03088f256 137 @returns 0 = success, -1 = fail
aidan1971 3:62c03088f256 138 */
aidan1971 10:49bb33f71d32 139 int32_t modify_i2c(uint32_t reg_addr, uint32_t data, uint32_t mask, int _i2c_addr = 0);
aidan1971 6:4ab5aaeaa064 140
aidan1971 3:62c03088f256 141 /*!
aidan1971 0:8f28f25e3435 142 @brief Attach a callback function to TX
aidan1971 3:62c03088f256 143 @param func Address of the user function to be called from the TX FIFO triggered ISR.
aidan1971 3:62c03088f256 144 This is blocking. If the user function does not complete before the next DMA completes the system will likely crash,
aidan1971 3:62c03088f256 145 however using this function avoids the latency of an IRQ stack push.
aidan1971 3:62c03088f256 146 @returns 0 = success, -1 = fail.
aidan1971 3:62c03088f256 147 Fails if already attached, must detach first.
aidan1971 0:8f28f25e3435 148 */
aidan1971 0:8f28f25e3435 149 int32_t attach_TX(Callback<void()> func);
aidan1971 6:4ab5aaeaa064 150
aidan1971 3:62c03088f256 151 /*!
aidan1971 3:62c03088f256 152 @brief Attach an ISR function to DMA TX
aidan1971 10:49bb33f71d32 153 @param user_ISR User function address pointer to be assigned as the NVIC vector for the DMA TX FIFO triggered user_ISR.
aidan1971 0:8f28f25e3435 154 @param irq_pri Set the system wide priority of the user_ISR.
aidan1971 0:8f28f25e3435 155 @param sw_irq The IRQ assigned. Default uses Reserved54_IRQn. See "MK20DX256.h" for available.
aidan1971 0:8f28f25e3435 156 This is non-blocking provided the priority of the IRQ associated with user_ISR is lower than the priority of the DMA triggered ISR.
aidan1971 0:8f28f25e3435 157 It can be useful to use a non-blocking call, however this involves the extra time needed to push the stack and manageing IRQ priorities
aidan1971 0:8f28f25e3435 158 across the whole system needs consideration.
aidan1971 0:8f28f25e3435 159 */
aidan1971 10:49bb33f71d32 160 int32_t attach_TX_NB(void* user_ISR, uint32_t irq_pri = 1, IRQn sw_irq = Reserved54_IRQn);
aidan1971 6:4ab5aaeaa064 161
aidan1971 3:62c03088f256 162 /*!
aidan1971 0:8f28f25e3435 163 @brief Stop TX channel and flag as detached.
aidan1971 0:8f28f25e3435 164 During running stream, the callback based function can not be changed. However changes to the NB IRQ based attachment can have the vector changed on-the-fly
aidan1971 0:8f28f25e3435 165 */
aidan1971 8:9fdf8501d14b 166 int32_t detach_TX(void);
aidan1971 0:8f28f25e3435 167
aidan1971 3:62c03088f256 168 /*!
aidan1971 10:49bb33f71d32 169 @brief Disables I2S TX function. This stops all DMA requests and supresses any IRQs from the driver and tristates the inbound CODEC I2S interface.
aidan1971 10:49bb33f71d32 170 It also stops bit clocks and word sync clocks.
aidan1971 10:49bb33f71d32 171 Note: Stopping the TX will also stop the RX stream because the RX is synchronous to the TX function. It is recommended that TX is the last enabled and first disabled.
aidan1971 0:8f28f25e3435 172 */
aidan1971 8:9fdf8501d14b 173 int32_t stop_TX(void);
aidan1971 6:4ab5aaeaa064 174
aidan1971 3:62c03088f256 175 /*!
aidan1971 10:49bb33f71d32 176 @brief Pauses I2S TX channels. Halts the TX stream(s) by masking all data words.
aidan1971 10:49bb33f71d32 177 This can be used to suspend the codec when a user wishes to run critical tasks where IRQs must be suppressed. To restart call the resume function.
aidan1971 10:49bb33f71d32 178 */
aidan1971 10:49bb33f71d32 179 int32_t pause_TX(void);
aidan1971 10:49bb33f71d32 180
aidan1971 10:49bb33f71d32 181 /*!
aidan1971 10:49bb33f71d32 182 @brief Resumes a paused I2S TX channels. Resumes the TX stream(s) by un-masking all data words.
aidan1971 10:49bb33f71d32 183 */
aidan1971 10:49bb33f71d32 184 int32_t resume_TX(void);
aidan1971 10:49bb33f71d32 185
aidan1971 10:49bb33f71d32 186 /*!
aidan1971 0:8f28f25e3435 187 @brief Starts the codec I2S interface and begins transferring TX buffers. Transfers use DMA.
aidan1971 10:49bb33f71d32 188 @param _BufTX_L_safe A pointer address to the TX Left channel_0 data.
aidan1971 0:8f28f25e3435 189 The pointer address is managed by the driver and changes to implement a double buffer.
aidan1971 0:8f28f25e3435 190 It is suggested that a suitable declaration in the users code would be in the form: 'q31_t *TX_AudioL = NULL;'
aidan1971 0:8f28f25e3435 191 Although volatile is not strictly necessary both the pointer address and the data pointed to, are changing outside the flow of the user code.
aidan1971 0:8f28f25e3435 192 To pass into the class, dereference this pointer and cast as uint32_t, as follows: 'codec.start_SYNC((uint32_t)&TX_AudioL .....'
aidan1971 10:49bb33f71d32 193 @param _BufTX_R_safe A pointer address to the TX Right channel_0 data.
aidan1971 9:40e0ff8c2ba2 194 @param _block_size 2 | 4 | 8 words of both Left and Right channels combined.
aidan1971 0:8f28f25e3435 195 This defines the number of samples that are transferred to the TX FIFO each time a FIFO demand is detected.
aidan1971 9:40e0ff8c2ba2 196 @param _packed_TX If true 2 * 16bit words for wire transmission are expected packed into a single 32bit word.
aidan1971 4:91354c908416 197 If False each 32bit word from the user should contain a single 16bit word for transmission.
aidan1971 9:40e0ff8c2ba2 198 @param _TX_shift True = The MS16bits of TX buffer are sent to the TX FIFO. Default = true.
aidan1971 0:8f28f25e3435 199 False = The LS16bits of TX buffer are sent to the TX FIFO.
aidan1971 4:91354c908416 200 If packed is true, then shift has no relevance.
aidan1971 9:40e0ff8c2ba2 201 @param _tx_DMAch Defines the system DMA channel to assign to the TX transfer. Default is 15.
aidan1971 0:8f28f25e3435 202 15 is used as default to avoid using channels 0 - 3 which are the only channels available for gated triggers.
aidan1971 0:8f28f25e3435 203 Gated triggering is not needed, so these 4 channels are avoided.
aidan1971 9:40e0ff8c2ba2 204 @param _DMA_irq_pri Default = 0. Highest priority. This is the priority of the I2S TX DMA demands.
aidan1971 10:49bb33f71d32 205 @param _BufTX_L_safe2 A pointer address to the TX Left channel_1 data.
aidan1971 10:49bb33f71d32 206 @param _BufTX_R_safe2 A pointer address to the TX Right channel_1 data.
aidan1971 3:62c03088f256 207 @returns 0 = success, -1 = fail
aidan1971 3:62c03088f256 208 Fails on variable sanity checks.
aidan1971 0:8f28f25e3435 209 */
aidan1971 9:40e0ff8c2ba2 210 int32_t start_TX(uint32_t _BufTX_L_safe, uint32_t _BufTX_R_safe,
aidan1971 10:49bb33f71d32 211 uint32_t _block_size = 4, bool _packed_TX = false, bool _TX_shift = true, uint32_t _TX_DMAch = 15, uint32_t _DMA_irq_pri = 0, uint32_t _BufTX_L_safe2 = NULL, uint32_t _BufTX_R_safe2 = NULL);
aidan1971 0:8f28f25e3435 212
aidan1971 3:62c03088f256 213 /*!
aidan1971 0:8f28f25e3435 214 @brief Attach a callback function to RX
aidan1971 0:8f28f25e3435 215 @param func User function to be called from the RX FIFO triggered ISR.
aidan1971 0:8f28f25e3435 216 This is blocking. If the user function does not complete before the next DMA completes the system will crash,
aidan1971 0:8f28f25e3435 217 however using this function avoids the latency of a stack push.
aidan1971 3:62c03088f256 218 @returns 0 = success, -1 = fail.
aidan1971 3:62c03088f256 219 Fails if already attached, must detach first.
aidan1971 0:8f28f25e3435 220 */
aidan1971 0:8f28f25e3435 221 int32_t attach_RX(Callback<void()> func);
aidan1971 6:4ab5aaeaa064 222
aidan1971 3:62c03088f256 223 /*!
aidan1971 3:62c03088f256 224 @brief Attach an ISR function to DMA RX
aidan1971 10:49bb33f71d32 225 @param user_ISR User function address pointer to be assigned as the NVIC vector for the DMA RX FIFO triggered user_ISR.
aidan1971 0:8f28f25e3435 226 @param irq_pri Set the system wide priority of the user_ISR.
aidan1971 0:8f28f25e3435 227 @param sw_irq The IRQ assigned. Default uses Reserved55_IRQn. See "MK20DX256.h" for available.
aidan1971 0:8f28f25e3435 228 This is non-blocking provided the priority of the IRQ associated with user_ISR is lower than the priority of the DMA triggered ISR.
aidan1971 0:8f28f25e3435 229 It can be useful to use a non-blocking call, however this involves the extra time needed to push the stack and manageing IRQ priorities
aidan1971 0:8f28f25e3435 230 across the whole system needs consideration.
aidan1971 0:8f28f25e3435 231 */
aidan1971 10:49bb33f71d32 232 int32_t attach_RX_NB(void* user_ISR, uint32_t irq_pri = 1, IRQn sw_irq = Reserved55_IRQn);
aidan1971 6:4ab5aaeaa064 233
aidan1971 3:62c03088f256 234 /*!
aidan1971 0:8f28f25e3435 235 @brief Stop RX channel and flag as detached.
aidan1971 9:40e0ff8c2ba2 236 During running stream, the callback based function can not be changed. However changes to the NB IRQ based attachment can have the vector changed on-the-fly
aidan1971 0:8f28f25e3435 237 */
aidan1971 8:9fdf8501d14b 238 int32_t detach_RX(void);
aidan1971 0:8f28f25e3435 239
aidan1971 3:62c03088f256 240 /*!
aidan1971 10:49bb33f71d32 241 @brief Disables I2S RX function. Stops all DMA requests and supresses any IRQs from the driver and tristates the outbound CODEC I2S interface(s).
aidan1971 10:49bb33f71d32 242 Note: Bit clock and Word Sync clock will continue as long as TX is running (started).
aidan1971 0:8f28f25e3435 243 */
aidan1971 8:9fdf8501d14b 244 int32_t stop_RX(void);
aidan1971 6:4ab5aaeaa064 245
aidan1971 3:62c03088f256 246 /*!
aidan1971 10:49bb33f71d32 247 @brief Pauses I2S RX channels. Halts the RX stream(s) by masking all data words.
aidan1971 10:49bb33f71d32 248 This can be used to suspend the codec when a user wishes to run critical tasks where IRQs must be suppressed. To restart call the resume function.
aidan1971 10:49bb33f71d32 249 */
aidan1971 10:49bb33f71d32 250 int32_t pause_RX(void);
aidan1971 10:49bb33f71d32 251
aidan1971 10:49bb33f71d32 252 /*!
aidan1971 10:49bb33f71d32 253 @brief Resumes a paused I2S RX channels. Resumes the RX stream(s) by un-masking all data words.
aidan1971 10:49bb33f71d32 254 */
aidan1971 10:49bb33f71d32 255 int32_t resume_RX(void);
aidan1971 10:49bb33f71d32 256
aidan1971 10:49bb33f71d32 257 /*!
aidan1971 0:8f28f25e3435 258 @brief Starts the codec I2S interface and begins transferring RX buffers. Transfers use DMA.
aidan1971 10:49bb33f71d32 259 @param _BufRX_L_safe A pointer address to the RX Left channel_0 data.
aidan1971 0:8f28f25e3435 260 The pointer address is managed by the driver and changes to implement a double buffer.
aidan1971 0:8f28f25e3435 261 It is suggested that a suitable declaration in the users code would be in the form: 'q31_t *RX_AudioL = NULL;'
aidan1971 0:8f28f25e3435 262 To pass into the class, dereference this pointer and cast as uint32_t, as follows: 'codec.start_SYNC((uint32_t)&RX_AudioL .....'
aidan1971 10:49bb33f71d32 263 @param _BufRX_R_safe A pointer address to the RX Right channel_0 data.
aidan1971 9:40e0ff8c2ba2 264 @param _block_size 2 | 4 | 8 words of both Left and Right channels combined.
aidan1971 0:8f28f25e3435 265 This defines the number of samples that are transferred to the RX FIFO each time a FIFO demand is detected.
aidan1971 9:40e0ff8c2ba2 266 @param _packed_RX If true the 2 * 16bit words from the codec are packed into a single 32bit word towards the user. This allows user code to use SIMD operations on the data
aidan1971 4:91354c908416 267 If False a single 16bit word from the wire is placed into a single 32bit word towards the user.
aidan1971 9:40e0ff8c2ba2 268 @param _RX_shift True = The 16bits of RX FIFO data are shifted to the MSBs of the RX buffer. Default = true
aidan1971 0:8f28f25e3435 269 False = The 16bits of RX FIFO data are placed in the LSBs of the RX buffer
aidan1971 0:8f28f25e3435 270 Note: If data is not shifted, the 32bit word delivered to the user will not be sign extended.
aidan1971 4:91354c908416 271 If packed is true, then shift has no relevance.
aidan1971 9:40e0ff8c2ba2 272 @param _rx_DMAch Defines the system DMA channel to assign to the RX transfer. Default is 14.
aidan1971 0:8f28f25e3435 273 14 is used as default to avoid using channels 0 - 3 which are the only channels available for gated triggers.
aidan1971 0:8f28f25e3435 274 Gated triggering is not needed, so these 4 channels are avoided.
aidan1971 9:40e0ff8c2ba2 275 @param _DMA_irq_pri Default = 0. Highest priority. This is the priority of the I2S RX DMA demands.
aidan1971 10:49bb33f71d32 276 @param _BufRX_L_safe2 A pointer address to the RX Left channel_1 data.
aidan1971 10:49bb33f71d32 277 @param _BufRX_R_safe2 A pointer address to the RX Right channel_1 data.
aidan1971 3:62c03088f256 278 @returns 0 = success, -1 = fail
aidan1971 3:62c03088f256 279 Fails on variable sanity checks.
aidan1971 0:8f28f25e3435 280 */
aidan1971 9:40e0ff8c2ba2 281 int32_t start_RX(uint32_t _BufRX_L_safe, uint32_t _BufRX_R_safe,
aidan1971 10:49bb33f71d32 282 uint32_t _block_size = 4, bool _packed_RX = false, bool _RX_shift = true, uint32_t _RX_DMAch = 14, uint32_t _DMA_irq_pri = 0, uint32_t _BufRX_L_safe2 = NULL, uint32_t _BufRX_R_safe2 = NULL);
aidan1971 0:8f28f25e3435 283
aidan1971 3:62c03088f256 284 /*!
aidan1971 0:8f28f25e3435 285 @brief Attach a callback function to DMA SYNC
aidan1971 0:8f28f25e3435 286 @param func User function to be called from the DMA SYNC FIFO triggered ISR.
aidan1971 0:8f28f25e3435 287 This is blocking. If the user function does not complete before the next DMA triggered IRQ the system will crash,
aidan1971 0:8f28f25e3435 288 however using this function avoids the latency of a stack push.
aidan1971 3:62c03088f256 289 @returns 0 = success, -1 = fail.
aidan1971 3:62c03088f256 290 Fails if already attached, must detach first.
aidan1971 0:8f28f25e3435 291 */
aidan1971 0:8f28f25e3435 292 int32_t attach_SYNC(Callback<void()> func);
aidan1971 6:4ab5aaeaa064 293
aidan1971 10:49bb33f71d32 294
aidan1971 3:62c03088f256 295 /*!
aidan1971 0:8f28f25e3435 296 @brief Attach a ISR function to DMA SYNC
aidan1971 10:49bb33f71d32 297 @param user_ISR User function address pointer to be assigned as the NVIC vector for the DMA SYNC FIFO triggered user_ISR.
aidan1971 0:8f28f25e3435 298 @param irq_pri Set the system wide priority of the user_ISR.
aidan1971 0:8f28f25e3435 299 @param sw_irq The IRQ assigned. Default uses Reserved53_IRQn. See "MK20DX256.h" for available.
aidan1971 0:8f28f25e3435 300 This creates a non-blocking call, which tests to see if the users ISR has completed before calling again.
aidan1971 0:8f28f25e3435 301 It requires that the priority of the IRQ associated with user_ISR is lower than the priority of the DMA triggered ISR.
aidan1971 0:8f28f25e3435 302 It can be useful to use a non-blocking call, however this involves the extra time needed to push the stack and manageing IRQ priorities
aidan1971 0:8f28f25e3435 303 across the whole system needs consideration.
aidan1971 0:8f28f25e3435 304 */
aidan1971 10:49bb33f71d32 305 int32_t attach_SYNC_NB(void* user_ISR, uint32_t irq_pri = 1, IRQn sw_irq = Reserved53_IRQn);
aidan1971 0:8f28f25e3435 306
aidan1971 3:62c03088f256 307 /*!
aidan1971 0:8f28f25e3435 308 @brief Stop both TX & RX channels and flag as detached.
aidan1971 0:8f28f25e3435 309 During running stream, the callback based function can not be changed. However changes to the NB IRQ based attachment can have the vector changed on-the-fly
aidan1971 0:8f28f25e3435 310 */
aidan1971 8:9fdf8501d14b 311 int32_t detach_SYNC(void);
aidan1971 0:8f28f25e3435 312
aidan1971 3:62c03088f256 313 /**
aidan1971 0:8f28f25e3435 314 @brief Starts the codec I2S interface and begins transferring RX and TX buffers. Transfers use DMA.
aidan1971 10:49bb33f71d32 315 @param _BufRX_L_safe A pointer address to the RX Left channel_0 data.
aidan1971 0:8f28f25e3435 316 The pointer address is managed by the driver and changes to implement a double buffer.
aidan1971 0:8f28f25e3435 317 It is suggested that a suitable declaration in the users code would be in the form: 'q31_t *RX_AudioL = NULL;'
aidan1971 0:8f28f25e3435 318 To pass into the class, dereference this pointer and cast as uint32_t, as follows: 'codec.start_SYNC((uint32_t)&RX_AudioL .....'
aidan1971 10:49bb33f71d32 319 @param _BufRX_R_safe A pointer address to the RX Right channel_0 data.
aidan1971 10:49bb33f71d32 320 @param _BufTX_L_safe A pointer address to the TX Left channel_0 data.
aidan1971 10:49bb33f71d32 321 @param _BufTX_R_safe A pointer address to the TX Right channel_0 data.
aidan1971 9:40e0ff8c2ba2 322 @param _block_size 2 | 4 | 8 words of both Left and Right channels combined.
aidan1971 0:8f28f25e3435 323 This defines the number of samples that are transferred to both FIFOs each time a FIFO demand is detected.
aidan1971 9:40e0ff8c2ba2 324 @param _packed_TX If true the 2 * 16bit words for wire transmission are expected packed into a single 32bit word.
aidan1971 4:91354c908416 325 If False each 32bit word from the user should contain a single 16bit word for transmission.
aidan1971 9:40e0ff8c2ba2 326 @param _packed_RX If true the 2 * 16bit words from the codec are packed into a single 32bit word towards the user. This allows user code to use SIMD operations on the data
aidan1971 4:91354c908416 327 If False a single 16bit word from the wire is placed into a single 32bit word towards the user.
aidan1971 0:8f28f25e3435 328 @param _RX_shift True = The 16bits of RX FIFO data are shifted to the MSBs of the RX buffer. Default = true
aidan1971 0:8f28f25e3435 329 False = The 16bits of RX FIFO data are placed in the LSBs of the RX buffer.
aidan1971 0:8f28f25e3435 330 Note: If data is not shifted, the 32bit word delivered to the user will not be sign extended.
aidan1971 4:91354c908416 331 If RX packed is true, then shift has no relevance.
aidan1971 0:8f28f25e3435 332 @param _TX_shift True = The MS16bits of TX buffer are sent to the TX FIFO. Default = true.
aidan1971 0:8f28f25e3435 333 False = The LS16bits of TX buffer are sent to the TX FIFO.
aidan1971 4:91354c908416 334 If TX packed is true, then shift has no relevance.
aidan1971 0:8f28f25e3435 335 @param _RX_DMAch Defines the system DMA channel to assign to the RX transfer. Default is 14.
aidan1971 0:8f28f25e3435 336 @param _TX_DMAch Defines the system DMA channel to assign to the TX transfer. Default is 15.
aidan1971 0:8f28f25e3435 337 14 & 15 are used as default to avoid using channels 0 - 3 which are the only channels available for gated triggers.
aidan1971 0:8f28f25e3435 338 Gated triggering is not needed, so these 4 channels are avoided.
aidan1971 9:40e0ff8c2ba2 339 @param _DMA_irq_pri Default = 0. Highest priority. This is the priority of the I2S DMA demands.
aidan1971 10:49bb33f71d32 340 @param _BufRX_L_safe2 A pointer address to the RX Left channel_1 data.
aidan1971 10:49bb33f71d32 341 @param _BufRX_R_safe2 A pointer address to the RX Right channel_1 data.
aidan1971 10:49bb33f71d32 342 @param _BufTX_L_safe2 A pointer address to the TX Left channel_1 data.
aidan1971 10:49bb33f71d32 343 @param _BufTX_R_safe2 A pointer address to the TX Right channel_1 data.
aidan1971 3:62c03088f256 344 @returns 0 = success, -1 = fail
aidan1971 3:62c03088f256 345 Fails on variable sanity checks.
aidan1971 0:8f28f25e3435 346 */
aidan1971 9:40e0ff8c2ba2 347 int32_t start_SYNC(uint32_t _BufRX_L_safe, uint32_t _BufRX_R_safe, uint32_t _BufTX_L_safe, uint32_t _BufTX_R_safe,
aidan1971 10:49bb33f71d32 348 uint32_t _block_size = 4, bool _packed_RX = false, bool _packed_TX = false, bool _RX_shift = true, bool _TX_shift = true, uint32_t _RX_DMAch = 14, uint32_t _TX_DMAch = 15, uint32_t _DMA_irq_pri = 0, uint32_t _BufRX_L_safe2 = NULL, uint32_t _BufRX_R_safe2 = NULL, uint32_t _BufTX_L_safe2 = NULL, uint32_t _BufTX_R_safe2 = NULL);
aidan1971 0:8f28f25e3435 349
aidan1971 3:62c03088f256 350 /*!
aidan1971 10:49bb33f71d32 351 @brief Stops I2S TX & RX channels. Stops all DMA requests and supresses any IRQs from the driver and tristates the CODEC I2S interface.
aidan1971 0:8f28f25e3435 352 */
aidan1971 8:9fdf8501d14b 353 int32_t stop_SYNC(void);
aidan1971 0:8f28f25e3435 354
aidan1971 3:62c03088f256 355 /*!
aidan1971 10:49bb33f71d32 356 @brief Pauses I2S RX & TX channels. Halts the RX & TX stream(s) by masking all data words.
aidan1971 10:49bb33f71d32 357 This can be used to suspend the codec when a user wishes to run critical tasks where IRQs must be suppressed. To restart call the resume function.
aidan1971 10:49bb33f71d32 358 */
aidan1971 10:49bb33f71d32 359 int32_t pause_SYNC(void);
aidan1971 10:49bb33f71d32 360
aidan1971 10:49bb33f71d32 361 /*!
aidan1971 10:49bb33f71d32 362 @brief Resumes a paused I2S RX & TX channels. Resumes the RX & TX stream(s) by un-masking all data words.
aidan1971 10:49bb33f71d32 363 */
aidan1971 10:49bb33f71d32 364 int32_t resume_SYNC(void);
aidan1971 10:49bb33f71d32 365
aidan1971 10:49bb33f71d32 366 /*!
aidan1971 10:49bb33f71d32 367 @brief Set codec and I2S Sampling frequency
aidan1971 0:8f28f25e3435 368 @param rate 8, 11, 12, 16, 22, 24, 32, 44, 48, 96, 192
aidan1971 0:8f28f25e3435 369 Base sampling rate of the codec
aidan1971 0:8f28f25e3435 370
aidan1971 0:8f28f25e3435 371 In all cases the SGTL5000 is programmed to use MCLK 256 times faster than sampling freq.
aidan1971 0:8f28f25e3435 372 MCU MCLK output = MCLK_Input((FRACT + 1)/(DIVIDE + 1))
aidan1971 0:8f28f25e3435 373 MCU MCLK Divide Register ratio is therefore = (Fs * 256)/PLL Clk
aidan1971 10:49bb33f71d32 374 The Teensy 3.1 & 3.2 have PLL freq @ 96MHz. However 120Mhz is supported dependent on the global 'SystemCoreClock' variable indicating this.
aidan1971 0:8f28f25e3435 375
aidan1971 3:62c03088f256 376 Note: To achieve some of these rates the codec SYS_FS is adjusted.
aidan1971 0:8f28f25e3435 377 This needs to be considered for several internal codec processes such as filter co-efficients and AVC.
aidan1971 3:62c03088f256 378 @returns 0 = success, -1 = fail
aidan1971 0:8f28f25e3435 379 */
aidan1971 10:49bb33f71d32 380 int32_t sample_rate(uint32_t rate);
aidan1971 10:49bb33f71d32 381
aidan1971 8:9fdf8501d14b 382 /*!
aidan1971 8:9fdf8501d14b 383 @brief Initialise codec.
aidan1971 10:49bb33f71d32 384 Resets the codec and sends initial default configuration data to the codec over I2C.
aidan1971 8:9fdf8501d14b 385 This function must be called after instantiation and before most other functions. It allows control over when I2C communications with the codec takes place.
aidan1971 8:9fdf8501d14b 386 Failure to initialize will prevent operation of the codec. However it possible to attach and detach functions before init.
aidan1971 8:9fdf8501d14b 387 @returns 0 = success, -1 = fail
aidan1971 8:9fdf8501d14b 388 */
aidan1971 8:9fdf8501d14b 389 int32_t init(void);
aidan1971 10:49bb33f71d32 390
aidan1971 3:62c03088f256 391 /*!
aidan1971 3:62c03088f256 392 @brief Read debug data from the codec
aidan1971 3:62c03088f256 393 @param index 0-15
aidan1971 10:49bb33f71d32 394 @param finished a simple semaphore, indicating that debug data should be aquired again. (Can be used in combination with the internal bool SGTL5000::debug_read, to gate data collection.)
aidan1971 3:62c03088f256 395 Just a simple way for user code to grab running variables if you need it.
aidan1971 3:62c03088f256 396 @returns 0 = success, -1 = fail
aidan1971 3:62c03088f256 397 */
aidan1971 10:49bb33f71d32 398 int32_t read_debug(uint32_t index, bool finished = false);
aidan1971 10:49bb33f71d32 399 static bool debug_read;
aidan1971 0:8f28f25e3435 400
aidan1971 0:8f28f25e3435 401
aidan1971 0:8f28f25e3435 402 protected:
aidan1971 6:4ab5aaeaa064 403 static uint32_t debug[16];
aidan1971 10:49bb33f71d32 404 static void t_stamp_start(void);
aidan1971 10:49bb33f71d32 405 static void t_stamp_stop(void);
aidan1971 10:49bb33f71d32 406 static uint32_t t1;
aidan1971 10:49bb33f71d32 407 static uint32_t proc_time;
aidan1971 10:49bb33f71d32 408 static uint32_t SYST_CVAL;// = 0xE000E018; // Address of SysTick current value register
aidan1971 0:8f28f25e3435 409
aidan1971 0:8f28f25e3435 410
aidan1971 0:8f28f25e3435 411 private:
aidan1971 10:49bb33f71d32 412
aidan1971 10:49bb33f71d32 413 static IRQn CODEC_CTRL_IRQ; // Default IRQ used to elevate priority of user commands.
aidan1971 10:49bb33f71d32 414 static uint32_t ctrl_command; // Command translation
aidan1971 10:49bb33f71d32 415 #define STOP_SYNC 0x1
aidan1971 10:49bb33f71d32 416 #define STOP_TX 0x2
aidan1971 10:49bb33f71d32 417 #define STOP_RX 0x3
aidan1971 10:49bb33f71d32 418 #define PAUSE_TX 0x4
aidan1971 10:49bb33f71d32 419 #define PAUSE_RX 0x5
aidan1971 10:49bb33f71d32 420 #define PAUSE_SYNC 0x6
aidan1971 10:49bb33f71d32 421 #define RESUME_TX 0x7
aidan1971 10:49bb33f71d32 422 #define RESUME_RX 0x8
aidan1971 10:49bb33f71d32 423 #define RESUME_SYNC 0x9
aidan1971 10:49bb33f71d32 424
aidan1971 10:49bb33f71d32 425 static void stream_ctrl_ISR(void); // High priority control commands trigger by user through software ISR
aidan1971 10:49bb33f71d32 426
aidan1971 10:49bb33f71d32 427
aidan1971 7:d65476c153a4 428 I2C mI2C; // Create I2C instance
aidan1971 10:49bb33f71d32 429
aidan1971 10:49bb33f71d32 430 int i2c_addr;
aidan1971 0:8f28f25e3435 431
aidan1971 10:49bb33f71d32 432 int32_t init_i2s(void); // Configure I2S Default Settings
aidan1971 0:8f28f25e3435 433
aidan1971 8:9fdf8501d14b 434 int32_t init_codec(void); // Configure codec Default Settings
aidan1971 0:8f28f25e3435 435
aidan1971 0:8f28f25e3435 436 void init_DMA(void); // Configure SYNC DMA settings on MK20DX256
aidan1971 0:8f28f25e3435 437
aidan1971 10:49bb33f71d32 438 static void SYNC_TX_dma_ISR(void);
aidan1971 6:4ab5aaeaa064 439
aidan1971 10:49bb33f71d32 440 static void SYNC_RX_dma_ISR(void);
aidan1971 0:8f28f25e3435 441
aidan1971 10:49bb33f71d32 442 static void SYNC_pointer_swap(void);
aidan1971 0:8f28f25e3435 443
aidan1971 10:49bb33f71d32 444 static void TX_dma_ISR(void); // Handle TX DMA transfers complete.
aidan1971 6:4ab5aaeaa064 445
aidan1971 10:49bb33f71d32 446 static void RX_dma_ISR(void); // Handle RX DMA transfers complete using Callback
aidan1971 0:8f28f25e3435 447
aidan1971 9:40e0ff8c2ba2 448 static void tx_I2S_WS_ISR(void); // Handle TX word start allignment
aidan1971 0:8f28f25e3435 449
aidan1971 9:40e0ff8c2ba2 450 static void rx_I2S_WS_ISR(void); // Handle RX word start allignment
aidan1971 0:8f28f25e3435 451
aidan1971 9:40e0ff8c2ba2 452 static void sync_I2S_WS_ISR(void); // Handle SYNC word start allignment
aidan1971 0:8f28f25e3435 453
aidan1971 0:8f28f25e3435 454
aidan1971 10:49bb33f71d32 455 //const uint32_t DMA_INT_ADDR = 0x40008024; // Hard code the DMA->INT address its faster when inline assembler optimises
aidan1971 6:4ab5aaeaa064 456
aidan1971 10:49bb33f71d32 457
aidan1971 10:49bb33f71d32 458 static volatile uint32_t * volatile BufRX_L_safe; // Define statics for ISRs
aidan1971 10:49bb33f71d32 459 static volatile uint32_t * volatile BufRX_R_safe;
aidan1971 10:49bb33f71d32 460 static volatile uint32_t * volatile BufTX_L_safe;
aidan1971 10:49bb33f71d32 461 static volatile uint32_t * volatile BufTX_R_safe;
aidan1971 10:49bb33f71d32 462 static volatile uint32_t * volatile BufRX_L_safe2; // Define statics for ISRs
aidan1971 10:49bb33f71d32 463 static volatile uint32_t * volatile BufRX_R_safe2;
aidan1971 10:49bb33f71d32 464 static volatile uint32_t * volatile BufTX_L_safe2;
aidan1971 10:49bb33f71d32 465 static volatile uint32_t * volatile BufTX_R_safe2;
aidan1971 10:49bb33f71d32 466 static uint32_t BufRX_L_safeA; // Precalculated double buffer addresses
aidan1971 10:49bb33f71d32 467 static uint32_t BufRX_R_safeA;
aidan1971 10:49bb33f71d32 468 static uint32_t BufTX_L_safeA;
aidan1971 10:49bb33f71d32 469 static uint32_t BufTX_R_safeA;
aidan1971 10:49bb33f71d32 470 static uint32_t BufRX_L_safeB; // Precalculated double buffer addresses
aidan1971 10:49bb33f71d32 471 static uint32_t BufRX_R_safeB;
aidan1971 10:49bb33f71d32 472 static uint32_t BufTX_L_safeB;
aidan1971 10:49bb33f71d32 473 static uint32_t BufTX_R_safeB;
aidan1971 10:49bb33f71d32 474 static uint32_t BufRX_L_safeA2; // Precalculated double buffer addresses
aidan1971 10:49bb33f71d32 475 static uint32_t BufRX_R_safeA2;
aidan1971 10:49bb33f71d32 476 static uint32_t BufTX_L_safeA2;
aidan1971 10:49bb33f71d32 477 static uint32_t BufTX_R_safeA2;
aidan1971 10:49bb33f71d32 478 static uint32_t BufRX_L_safeB2; // Precalculated double buffer addresses
aidan1971 10:49bb33f71d32 479 static uint32_t BufRX_R_safeB2;
aidan1971 10:49bb33f71d32 480 static uint32_t BufTX_L_safeB2;
aidan1971 10:49bb33f71d32 481 static uint32_t BufTX_R_safeB2;
aidan1971 10:49bb33f71d32 482 static uint32_t I2S_RX_Buffer[16];
aidan1971 10:49bb33f71d32 483 static uint32_t I2S_TX_Buffer[16];
aidan1971 10:49bb33f71d32 484 static uint32_t I2S_RX_Buffer2[16];
aidan1971 10:49bb33f71d32 485 static uint32_t I2S_TX_Buffer2[16];
aidan1971 10:49bb33f71d32 486 static uint32_t active_RX_DMAch_bm;
aidan1971 10:49bb33f71d32 487 static uint32_t active_TX_DMAch_bm;
aidan1971 10:49bb33f71d32 488 static uint32_t sync_dma_irq_acks;
aidan1971 0:8f28f25e3435 489 static IRQn SYNC_swIRQ;
aidan1971 0:8f28f25e3435 490 static IRQn TX_swIRQ;
aidan1971 0:8f28f25e3435 491 static IRQn RX_swIRQ;
aidan1971 0:8f28f25e3435 492 static Callback<void()> TX_user_func;
aidan1971 0:8f28f25e3435 493 static Callback<void()> RX_user_func;
aidan1971 0:8f28f25e3435 494 static Callback<void()> SYNC_user_func;
aidan1971 9:40e0ff8c2ba2 495 static uint32_t db_phase_sync;
aidan1971 9:40e0ff8c2ba2 496 static uint32_t db_phase_tx;
aidan1971 9:40e0ff8c2ba2 497 static uint32_t db_phase_rx;
aidan1971 10:49bb33f71d32 498 static uint32_t SYNC_attach_type;
aidan1971 10:49bb33f71d32 499 static uint32_t TX_attach_type;
aidan1971 10:49bb33f71d32 500 static uint32_t RX_attach_type;
aidan1971 10:49bb33f71d32 501 static bool i2s_configured;
aidan1971 10:49bb33f71d32 502 static bool codec2_active;
aidan1971 10:49bb33f71d32 503 static bool codec1_active;
aidan1971 10:49bb33f71d32 504 static uint32_t dump;
aidan1971 10:49bb33f71d32 505 static uint32_t NULL_DMA_TX;
aidan1971 10:49bb33f71d32 506 static uint32_t NULL_DMA_RX;
aidan1971 10:49bb33f71d32 507 static uint32_t RX_DMAch;
aidan1971 10:49bb33f71d32 508 static uint32_t TX_DMAch;
aidan1971 10:49bb33f71d32 509 static bool SYNC_run;
aidan1971 10:49bb33f71d32 510 static bool TX_run;
aidan1971 10:49bb33f71d32 511 static bool RX_run;
aidan1971 0:8f28f25e3435 512
aidan1971 10:49bb33f71d32 513 int i2c_freq;
aidan1971 6:4ab5aaeaa064 514 uint32_t TX_block_size;
aidan1971 6:4ab5aaeaa064 515 uint32_t RX_block_size;
aidan1971 0:8f28f25e3435 516 uint32_t TX_bs_bytes;
aidan1971 0:8f28f25e3435 517 uint32_t RX_bs_bytes;
aidan1971 10:49bb33f71d32 518 bool ctrl_codec;
aidan1971 8:9fdf8501d14b 519 bool codec_configured;
aidan1971 9:40e0ff8c2ba2 520 bool codec_I2S_active;
aidan1971 10:49bb33f71d32 521
aidan1971 0:8f28f25e3435 522 bool SYNC_attached;
aidan1971 0:8f28f25e3435 523 bool TX_attached;
aidan1971 0:8f28f25e3435 524 bool RX_attached;
aidan1971 0:8f28f25e3435 525 bool TX_shift;
aidan1971 0:8f28f25e3435 526 bool RX_shift;
aidan1971 4:91354c908416 527 bool packed_RX;
aidan1971 4:91354c908416 528 bool packed_TX;
aidan1971 10:49bb33f71d32 529
aidan1971 10:49bb33f71d32 530
aidan1971 0:8f28f25e3435 531 };
aidan1971 0:8f28f25e3435 532 }
aidan1971 0:8f28f25e3435 533 #endif