Aidan Walton / SGTL5000 Featured

Library to control and transfer data from NXP SGTL5000. As used on the Teensy Audio Shield. It uses DMA to transfer I2S FIFO data.

The Library now supports dual codecs. Allowing all 4 channels of the Teensy I2S interface to RX and TX data to separate SGTL5000 devices.

The ISR routines that handles pointer swaps for double buffering has been fully coded in assembler to reduce overhead and now takes < 800nS per FIFO transfer when using all 4 channels.

Support added for all typical sample rates and system Clock speeds of 96Mhz or 120Mhz.

Pause and Resume functions added to allow quick and simple suppression of IRQs and stream halting and restart. This required software triggered IRQ, in order to ensure accurate word sync control.

sgtl5000.h@0:8f28f25e3435, 2017-06-15 (annotated)

Committer:
aidan1971
Date:
Thu Jun 15 09:27:42 2017 +0000
Revision:
0:8f28f25e3435
Child:
3:62c03088f256
version 0.1

Who changed what in which revision?

UserRevisionLine numberNew contents of line
aidan1971 0:8f28f25e3435 1 /*
aidan1971 0:8f28f25e3435 2 @ author Aidan Walton, aidan.walton@gmail.com
aidan1971 0:8f28f25e3435 3
aidan1971 0:8f28f25e3435 4 @section LICENSE
aidan1971 0:8f28f25e3435 5 * Permission is hereby granted, free of charge, to any person obtaining a copy
aidan1971 0:8f28f25e3435 6 * of this software and associated documentation files (the "Software"), to deal
aidan1971 0:8f28f25e3435 7 * in the Software without restriction, including without limitation the rights
aidan1971 0:8f28f25e3435 8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
aidan1971 0:8f28f25e3435 9 * copies of the Software, and to permit persons to whom the Software is
aidan1971 0:8f28f25e3435 10 * furnished to do so, subject to the following conditions:
aidan1971 0:8f28f25e3435 11 *
aidan1971 0:8f28f25e3435 12 * The above copyright notice, development funding notice, and this permission
aidan1971 0:8f28f25e3435 13 * notice shall be included in all copies or substantial portions of the Software.
aidan1971 0:8f28f25e3435 14 *
aidan1971 0:8f28f25e3435 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
aidan1971 0:8f28f25e3435 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
aidan1971 0:8f28f25e3435 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
aidan1971 0:8f28f25e3435 18 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
aidan1971 0:8f28f25e3435 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
aidan1971 0:8f28f25e3435 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
aidan1971 0:8f28f25e3435 21 * THE SOFTWARE.
aidan1971 0:8f28f25e3435 22
aidan1971 0:8f28f25e3435 23 @section DESCRIPTION
aidan1971 0:8f28f25e3435 24 Library for NXP SGTL5000 Codec
aidan1971 0:8f28f25e3435 25 */
aidan1971 0:8f28f25e3435 26
aidan1971 0:8f28f25e3435 27 #ifndef MBED_SGTL5000_H
aidan1971 0:8f28f25e3435 28 #define MBED_SGTL5000_H
aidan1971 0:8f28f25e3435 29
aidan1971 0:8f28f25e3435 30 #include "mbed.h"
aidan1971 0:8f28f25e3435 31 #include "platform.h"
aidan1971 0:8f28f25e3435 32 #include "Callback.h"
aidan1971 0:8f28f25e3435 33 #include "sgtl5000_defs.h"
aidan1971 0:8f28f25e3435 34
aidan1971 0:8f28f25e3435 35 namespace SGTL5000
aidan1971 0:8f28f25e3435 36 {
aidan1971 0:8f28f25e3435 37
aidan1971 0:8f28f25e3435 38 class SGTL5000
aidan1971 0:8f28f25e3435 39
aidan1971 0:8f28f25e3435 40 {
aidan1971 0:8f28f25e3435 41 public:
aidan1971 0:8f28f25e3435 42 /*constructor
aidan1971 0:8f28f25e3435 43 @brief Create an SGTL5000 object defined on the I2C port using DMA transfers of I2S data. The class is not defined as a singleton, as future development may require
aidan1971 0:8f28f25e3435 44 multiple instances. However currently it should only be instantiated once. The class is wrapped in the SGTL5000 namespace to avoid collisions with statics
aidan1971 0:8f28f25e3435 45 needed by the ISRs. Instantiation within the main code exemplified as follows: 'SGTL5000::SGTL5000 codec(I2C_SDA, I2C_SCL);'
aidan1971 0:8f28f25e3435 46
aidan1971 0:8f28f25e3435 47 @param i2c_sda i2c Serial data pin (D18 Teensy 3.2 header / PTB3 MK20DX256)
aidan1971 0:8f28f25e3435 48 @param i2c_scl i2c Serial clock pin (D19 Teensy 3.2 header / PTB2 MK20DX256)
aidan1971 0:8f28f25e3435 49 @param i2c_freq Frequency in Hz at which the i2c codec interface clocks data
aidan1971 0:8f28f25e3435 50 @param i2c_ctrl_adr0_cs State on SGTL5000 CTRL_ADR0_CS pin i2c addr = 0n01010(R/W) :R/W = 1 to write R/W = 0 to read, n = 0 pull down / n = 1 pull up on CTRL_ADR0_CS pin of SGTL5000)
aidan1971 0:8f28f25e3435 51
aidan1971 0:8f28f25e3435 52
aidan1971 0:8f28f25e3435 53 // Pin Configs for i2s hardcoded as follows to match Teensy Audio Shield
aidan1971 0:8f28f25e3435 54 i2s_mclk i2s master clock (D11 Teensy 3.2 header / PTC6 MK20DX256)
aidan1971 0:8f28f25e3435 55 i2s_bclk i2s bit clock (D9 Teensy 3.2 header / PTC3 MK20DX256)
aidan1971 0:8f28f25e3435 56 i2s_fs i2s Frame Sync / L/R clock / WordSelect (D23 Teensy 3.2 header / PTC2 MK20DX256)
aidan1971 0:8f28f25e3435 57 i2s_rx i2s tx_data (from bus master perspective) (D22 Teensy 3.2 header / PTC1 MK20DX256)
aidan1971 0:8f28f25e3435 58 i2s_tx i2s rx_data (from bus master perspective) (D13 Teensy 3.2 header /PTC5 MK20DX256)
aidan1971 0:8f28f25e3435 59
aidan1971 0:8f28f25e3435 60 */
aidan1971 0:8f28f25e3435 61 SGTL5000(PinName i2c_sda, PinName i2c_scl, int i2c_freq = 100000, bool i2c_ctrl_adr0_cs = 0);
aidan1971 0:8f28f25e3435 62
aidan1971 0:8f28f25e3435 63
aidan1971 0:8f28f25e3435 64 int32_t read_i2c(uint32_t reg_addr, uint32_t mask = 0xFFFF); // Read 16bit register of SGTL5000
aidan1971 0:8f28f25e3435 65 int32_t write_i2c(uint32_t reg_addr, uint32_t data); //Write 16bit register of SGTL5000
aidan1971 0:8f28f25e3435 66 int32_t modify_i2c(uint32_t reg_addr, uint32_t data, uint32_t mask); //Modify masked bits within 16bit register of SGTL5000
aidan1971 0:8f28f25e3435 67 /*
aidan1971 0:8f28f25e3435 68 @brief Attach a callback function to TX
aidan1971 0:8f28f25e3435 69 @param func User function to be called from the TX FIFO triggered ISR.
aidan1971 0:8f28f25e3435 70 This is blocking. If the user function does not complete before the next DMA completes the system will crash,
aidan1971 0:8f28f25e3435 71 however using this function avoids the latency of a stack push.
aidan1971 0:8f28f25e3435 72 */
aidan1971 0:8f28f25e3435 73 int32_t attach_TX(Callback<void()> func);
aidan1971 0:8f28f25e3435 74 /*
aidan1971 0:8f28f25e3435 75 @brief Attach a ISR function to DMA TX
aidan1971 0:8f28f25e3435 76 @param user_ISR User function to be assigned as the NVIC vector for the DMA TX FIFO triggered user_ISR.
aidan1971 0:8f28f25e3435 77 @param irq_pri Set the system wide priority of the user_ISR.
aidan1971 0:8f28f25e3435 78 @param sw_irq The IRQ assigned. Default uses Reserved54_IRQn. See "MK20DX256.h" for available.
aidan1971 0:8f28f25e3435 79 This is non-blocking provided the priority of the IRQ associated with user_ISR is lower than the priority of the DMA triggered ISR.
aidan1971 0:8f28f25e3435 80 It can be useful to use a non-blocking call, however this involves the extra time needed to push the stack and manageing IRQ priorities
aidan1971 0:8f28f25e3435 81 across the whole system needs consideration.
aidan1971 0:8f28f25e3435 82 */
aidan1971 0:8f28f25e3435 83 int32_t attach_TX_NB(uint32_t user_ISR, uint32_t irq_pri = 1, IRQn sw_irq = Reserved54_IRQn);
aidan1971 0:8f28f25e3435 84 /*
aidan1971 0:8f28f25e3435 85 @brief Stop TX channel and flag as detached.
aidan1971 0:8f28f25e3435 86 During running stream, the callback based function can not be changed. However changes to the NB IRQ based attachment can have the vector changed on-the-fly
aidan1971 0:8f28f25e3435 87 */
aidan1971 0:8f28f25e3435 88 void detach_TX(void);
aidan1971 0:8f28f25e3435 89
aidan1971 0:8f28f25e3435 90 /*
aidan1971 0:8f28f25e3435 91 @brief Stops i2s TX channel but maintains clocking.
aidan1971 0:8f28f25e3435 92 */
aidan1971 0:8f28f25e3435 93 int32_t stop_TX(void);
aidan1971 0:8f28f25e3435 94 /*
aidan1971 0:8f28f25e3435 95 @brief Starts the codec I2S interface and begins transferring TX buffers. Transfers use DMA.
aidan1971 0:8f28f25e3435 96 @param BufTX_L_safe A pointer address to the TX Left channel data.
aidan1971 0:8f28f25e3435 97 The pointer address is managed by the driver and changes to implement a double buffer.
aidan1971 0:8f28f25e3435 98 It is suggested that a suitable declaration in the users code would be in the form: 'q31_t *TX_AudioL = NULL;'
aidan1971 0:8f28f25e3435 99 Although volatile is not strictly necessary both the pointer address and the data pointed to, are changing outside the flow of the user code.
aidan1971 0:8f28f25e3435 100 To pass into the class, dereference this pointer and cast as uint32_t, as follows: 'codec.start_SYNC((uint32_t)&TX_AudioL .....'
aidan1971 0:8f28f25e3435 101 @param BufTX_R_safe A pointer address to the TX Right channel data.
aidan1971 0:8f28f25e3435 102 @param block_size 2 | 4 | 8 words of both Left and Right channels combined.
aidan1971 0:8f28f25e3435 103 This defines the number of samples that are transferred to the TX FIFO each time a FIFO demand is detected.
aidan1971 0:8f28f25e3435 104 @param TX_shift True = The MS16bits of TX buffer are sent to the TX FIFO. Default = true.
aidan1971 0:8f28f25e3435 105 False = The LS16bits of TX buffer are sent to the TX FIFO.
aidan1971 0:8f28f25e3435 106 @param tx_DMAch Defines the system DMA channel to assign to the TX transfer. Default is 15.
aidan1971 0:8f28f25e3435 107 15 is used as default to avoid using channels 0 - 3 which are the only channels available for gated triggers.
aidan1971 0:8f28f25e3435 108 Gated triggering is not needed, so these 4 channels are avoided.
aidan1971 0:8f28f25e3435 109 @param DMA_irq_pri Default = 0. Highest priority. This is the priority of the I2S TX DMA demands.
aidan1971 0:8f28f25e3435 110 */
aidan1971 0:8f28f25e3435 111 int32_t start_TX(uint32_t BufTX_L_safe, uint32_t BufTX_R_safe,
aidan1971 0:8f28f25e3435 112 uint32_t block_size = 4, bool _TX_shift = true, uint32_t _TX_DMAch = 15, uint32_t DMA_irq_pri = 0);
aidan1971 0:8f28f25e3435 113
aidan1971 0:8f28f25e3435 114 /*
aidan1971 0:8f28f25e3435 115 @brief Attach a callback function to RX
aidan1971 0:8f28f25e3435 116 @param func User function to be called from the RX FIFO triggered ISR.
aidan1971 0:8f28f25e3435 117 This is blocking. If the user function does not complete before the next DMA completes the system will crash,
aidan1971 0:8f28f25e3435 118 however using this function avoids the latency of a stack push.
aidan1971 0:8f28f25e3435 119 */
aidan1971 0:8f28f25e3435 120 int32_t attach_RX(Callback<void()> func);
aidan1971 0:8f28f25e3435 121 /*
aidan1971 0:8f28f25e3435 122 @brief Attach a ISR function to DMA RX
aidan1971 0:8f28f25e3435 123 @param user_ISR User function to be assigned as the NVIC vector for the DMA RX FIFO triggered user_ISR.
aidan1971 0:8f28f25e3435 124 @param irq_pri Set the system wide priority of the user_ISR.
aidan1971 0:8f28f25e3435 125 @param sw_irq The IRQ assigned. Default uses Reserved55_IRQn. See "MK20DX256.h" for available.
aidan1971 0:8f28f25e3435 126 This is non-blocking provided the priority of the IRQ associated with user_ISR is lower than the priority of the DMA triggered ISR.
aidan1971 0:8f28f25e3435 127 It can be useful to use a non-blocking call, however this involves the extra time needed to push the stack and manageing IRQ priorities
aidan1971 0:8f28f25e3435 128 across the whole system needs consideration.
aidan1971 0:8f28f25e3435 129 */
aidan1971 0:8f28f25e3435 130 int32_t attach_RX_NB(uint32_t user_ISR, uint32_t irq_pri = 1, IRQn sw_irq = Reserved55_IRQn);
aidan1971 0:8f28f25e3435 131 /*
aidan1971 0:8f28f25e3435 132 @brief Stop RX channel and flag as detached.
aidan1971 0:8f28f25e3435 133 During running stream, the callback based function can not be changed. However changes to the NB IRQ based attachment can have the vector changed on-the-fly
aidan1971 0:8f28f25e3435 134 */
aidan1971 0:8f28f25e3435 135 void detach_RX(void);
aidan1971 0:8f28f25e3435 136
aidan1971 0:8f28f25e3435 137 /*
aidan1971 0:8f28f25e3435 138 @brief Stops i2s RX channel but maintains clocking.
aidan1971 0:8f28f25e3435 139 */
aidan1971 0:8f28f25e3435 140 int32_t stop_RX(void);
aidan1971 0:8f28f25e3435 141 /*
aidan1971 0:8f28f25e3435 142 @brief Starts the codec I2S interface and begins transferring RX buffers. Transfers use DMA.
aidan1971 0:8f28f25e3435 143 @param BufRX_L_safe A pointer address to the RX Left channel data.
aidan1971 0:8f28f25e3435 144 The pointer address is managed by the driver and changes to implement a double buffer.
aidan1971 0:8f28f25e3435 145 It is suggested that a suitable declaration in the users code would be in the form: 'q31_t *RX_AudioL = NULL;'
aidan1971 0:8f28f25e3435 146 To pass into the class, dereference this pointer and cast as uint32_t, as follows: 'codec.start_SYNC((uint32_t)&RX_AudioL .....'
aidan1971 0:8f28f25e3435 147 @param BufRX_R_safe A pointer address to the RX Right channel data.
aidan1971 0:8f28f25e3435 148 @param block_size 2 | 4 | 8 words of both Left and Right channels combined.
aidan1971 0:8f28f25e3435 149 This defines the number of samples that are transferred to the RX FIFO each time a FIFO demand is detected.
aidan1971 0:8f28f25e3435 150 @param RX_shift True = The 16bits of RX FIFO data are shifted to the MSBs of the RX buffer. Default = true
aidan1971 0:8f28f25e3435 151 False = The 16bits of RX FIFO data are placed in the LSBs of the RX buffer
aidan1971 0:8f28f25e3435 152 Note: If data is not shifted, the 32bit word delivered to the user will not be sign extended.
aidan1971 0:8f28f25e3435 153 @param rx_DMAch Defines the system DMA channel to assign to the RX transfer. Default is 14.
aidan1971 0:8f28f25e3435 154 14 is used as default to avoid using channels 0 - 3 which are the only channels available for gated triggers.
aidan1971 0:8f28f25e3435 155 Gated triggering is not needed, so these 4 channels are avoided.
aidan1971 0:8f28f25e3435 156 @param DMA_irq_pri Default = 0. Highest priority. This is the priority of the I2S RX DMA demands.
aidan1971 0:8f28f25e3435 157 */
aidan1971 0:8f28f25e3435 158 int32_t start_RX(uint32_t BufRX_L_safe, uint32_t BufRX_R_safe,
aidan1971 0:8f28f25e3435 159 uint32_t block_size = 4, bool _RX_shift = true, uint32_t _RX_DMAch = 14, uint32_t DMA_irq_pri = 0);
aidan1971 0:8f28f25e3435 160
aidan1971 0:8f28f25e3435 161 /*
aidan1971 0:8f28f25e3435 162 @brief Attach a callback function to DMA SYNC
aidan1971 0:8f28f25e3435 163 @param func User function to be called from the DMA SYNC FIFO triggered ISR.
aidan1971 0:8f28f25e3435 164 This is blocking. If the user function does not complete before the next DMA triggered IRQ the system will crash,
aidan1971 0:8f28f25e3435 165 however using this function avoids the latency of a stack push.
aidan1971 0:8f28f25e3435 166 */
aidan1971 0:8f28f25e3435 167 int32_t attach_SYNC(Callback<void()> func);
aidan1971 0:8f28f25e3435 168 /*
aidan1971 0:8f28f25e3435 169 @brief Attach a ISR function to DMA SYNC
aidan1971 0:8f28f25e3435 170 @param user_ISR User function to be assigned as the NVIC vector for the DMA SYNC FIFO triggered user_ISR.
aidan1971 0:8f28f25e3435 171 @param irq_pri Set the system wide priority of the user_ISR.
aidan1971 0:8f28f25e3435 172 @param sw_irq The IRQ assigned. Default uses Reserved53_IRQn. See "MK20DX256.h" for available.
aidan1971 0:8f28f25e3435 173 This creates a non-blocking call, which tests to see if the users ISR has completed before calling again.
aidan1971 0:8f28f25e3435 174 It requires that the priority of the IRQ associated with user_ISR is lower than the priority of the DMA triggered ISR.
aidan1971 0:8f28f25e3435 175 It can be useful to use a non-blocking call, however this involves the extra time needed to push the stack and manageing IRQ priorities
aidan1971 0:8f28f25e3435 176 across the whole system needs consideration.
aidan1971 0:8f28f25e3435 177 */
aidan1971 0:8f28f25e3435 178 int32_t attach_SYNC_NB(uint32_t user_ISR, uint32_t irq_pri = 1, IRQn sw_irq = Reserved53_IRQn);
aidan1971 0:8f28f25e3435 179
aidan1971 0:8f28f25e3435 180 /*
aidan1971 0:8f28f25e3435 181 @brief Stop both TX & RX channels and flag as detached.
aidan1971 0:8f28f25e3435 182 During running stream, the callback based function can not be changed. However changes to the NB IRQ based attachment can have the vector changed on-the-fly
aidan1971 0:8f28f25e3435 183 */
aidan1971 0:8f28f25e3435 184 void detach_SYNC(void);
aidan1971 0:8f28f25e3435 185
aidan1971 0:8f28f25e3435 186
aidan1971 0:8f28f25e3435 187 /*
aidan1971 0:8f28f25e3435 188 @brief Starts the codec I2S interface and begins transferring RX and TX buffers. Transfers use DMA.
aidan1971 0:8f28f25e3435 189 @param BufRX_L_safe A pointer address to the RX Left channel data.
aidan1971 0:8f28f25e3435 190 The pointer address is managed by the driver and changes to implement a double buffer.
aidan1971 0:8f28f25e3435 191 It is suggested that a suitable declaration in the users code would be in the form: 'q31_t *RX_AudioL = NULL;'
aidan1971 0:8f28f25e3435 192 To pass into the class, dereference this pointer and cast as uint32_t, as follows: 'codec.start_SYNC((uint32_t)&RX_AudioL .....'
aidan1971 0:8f28f25e3435 193 @param BufRX_L_safe A pointer address to the RX Right channel data.
aidan1971 0:8f28f25e3435 194 @param BufRX_L_safe A pointer address to the TX Left channel data.
aidan1971 0:8f28f25e3435 195 @param BufRX_L_safe A pointer address to the TX Right channel data.
aidan1971 0:8f28f25e3435 196 @param block_size 2 | 4 | 8 words of both Left and Right channels combined.
aidan1971 0:8f28f25e3435 197 This defines the number of samples that are transferred to both FIFOs each time a FIFO demand is detected.
aidan1971 0:8f28f25e3435 198 @param _RX_shift True = The 16bits of RX FIFO data are shifted to the MSBs of the RX buffer. Default = true
aidan1971 0:8f28f25e3435 199 False = The 16bits of RX FIFO data are placed in the LSBs of the RX buffer.
aidan1971 0:8f28f25e3435 200 Note: If data is not shifted, the 32bit word delivered to the user will not be sign extended.
aidan1971 0:8f28f25e3435 201 @param _TX_shift True = The MS16bits of TX buffer are sent to the TX FIFO. Default = true.
aidan1971 0:8f28f25e3435 202 False = The LS16bits of TX buffer are sent to the TX FIFO.
aidan1971 0:8f28f25e3435 203 @param _RX_DMAch Defines the system DMA channel to assign to the RX transfer. Default is 14.
aidan1971 0:8f28f25e3435 204 @param _TX_DMAch Defines the system DMA channel to assign to the TX transfer. Default is 15.
aidan1971 0:8f28f25e3435 205 14 & 15 are used as default to avoid using channels 0 - 3 which are the only channels available for gated triggers.
aidan1971 0:8f28f25e3435 206 Gated triggering is not needed, so these 4 channels are avoided.
aidan1971 0:8f28f25e3435 207 @param DMA_irq_pri Default = 0. Highest priority. This is the priority of the I2S DMA demands.
aidan1971 0:8f28f25e3435 208 */
aidan1971 0:8f28f25e3435 209 int32_t start_SYNC(uint32_t BufRX_L_safe, uint32_t BufRX_R_safe, uint32_t BufTX_L_safe, uint32_t BufTX_R_safe,
aidan1971 0:8f28f25e3435 210 uint32_t block_size = 4, bool _RX_shift = true, bool _TX_shift = true, uint32_t _RX_DMAch = 14, uint32_t _TX_DMAch = 15, uint32_t DMA_irq_pri = 0);
aidan1971 0:8f28f25e3435 211
aidan1971 0:8f28f25e3435 212 /*
aidan1971 0:8f28f25e3435 213 @brief Stops i2s TX & RX channels but maintains clocking.
aidan1971 0:8f28f25e3435 214 */
aidan1971 0:8f28f25e3435 215 int32_t stop_SYNC(void);
aidan1971 0:8f28f25e3435 216
aidan1971 0:8f28f25e3435 217 /*
aidan1971 0:8f28f25e3435 218 @brief Set codec and i2s Sampling frequency
aidan1971 0:8f28f25e3435 219 @param rate 8, 11, 12, 16, 22, 24, 32, 44, 48, 96, 192
aidan1971 0:8f28f25e3435 220 Base sampling rate of the codec
aidan1971 0:8f28f25e3435 221
aidan1971 0:8f28f25e3435 222 In all cases the SGTL5000 is programmed to use MCLK 256 times faster than sampling freq.
aidan1971 0:8f28f25e3435 223 MCU MCLK output = MCLK_Input((FRACT + 1)/(DIVIDE + 1))
aidan1971 0:8f28f25e3435 224 MCU MCLK Divide Register ratio is therefore = (Fs * 256)/PLL Clk
aidan1971 0:8f28f25e3435 225 The Teensy 3.1 & 3.2 have PLL freq @ 96MHz
aidan1971 0:8f28f25e3435 226
aidan1971 0:8f28f25e3435 227 Note: To achieve some of these rates SYS_FS is adjusted.
aidan1971 0:8f28f25e3435 228 This needs to be considered for several internal codec processes such as filter co-efficients and AVC.
aidan1971 0:8f28f25e3435 229 */
aidan1971 0:8f28f25e3435 230 int32_t freq(uint32_t rate);
aidan1971 0:8f28f25e3435 231
aidan1971 0:8f28f25e3435 232 uint32_t read_debug(uint32_t index);
aidan1971 0:8f28f25e3435 233
aidan1971 0:8f28f25e3435 234
aidan1971 0:8f28f25e3435 235 protected:
aidan1971 0:8f28f25e3435 236
aidan1971 0:8f28f25e3435 237
aidan1971 0:8f28f25e3435 238 static uint32_t volatile debug[16];
aidan1971 0:8f28f25e3435 239
aidan1971 0:8f28f25e3435 240
aidan1971 0:8f28f25e3435 241
aidan1971 0:8f28f25e3435 242
aidan1971 0:8f28f25e3435 243
aidan1971 0:8f28f25e3435 244 private:
aidan1971 0:8f28f25e3435 245 I2C mI2C;
aidan1971 0:8f28f25e3435 246 int i2c_addr;
aidan1971 0:8f28f25e3435 247
aidan1971 0:8f28f25e3435 248 void init_i2s(void); // Configure I2S Default Settings
aidan1971 0:8f28f25e3435 249
aidan1971 0:8f28f25e3435 250 void init_codec(void); // Configure codec Default Settings
aidan1971 0:8f28f25e3435 251
aidan1971 0:8f28f25e3435 252 void init_DMA(void); // Configure SYNC DMA settings on MK20DX256
aidan1971 0:8f28f25e3435 253
aidan1971 0:8f28f25e3435 254 static void tx_dma_ISR(void); // Handle TX DMA transfers complete
aidan1971 0:8f28f25e3435 255
aidan1971 0:8f28f25e3435 256 static void rx_dma_ISR(void); // Handle RX DMA transfers complete
aidan1971 0:8f28f25e3435 257
aidan1971 0:8f28f25e3435 258 static void sync_dma_ISR(void); // Handle SYNC DMA transfers complete
aidan1971 0:8f28f25e3435 259
aidan1971 0:8f28f25e3435 260 static void tx_I2S_ISR(void); // Handle TX word start allignment
aidan1971 0:8f28f25e3435 261
aidan1971 0:8f28f25e3435 262 static void rx_I2S_ISR(void); // Handle RX word start allignment
aidan1971 0:8f28f25e3435 263
aidan1971 0:8f28f25e3435 264 static void sync_I2S_ISR(void); // Handle SYNC word start allignment
aidan1971 0:8f28f25e3435 265
aidan1971 0:8f28f25e3435 266
aidan1971 0:8f28f25e3435 267 static uint32_t I2S_RX_Buffer[]; // Define global statics needed within ISRs
aidan1971 0:8f28f25e3435 268 static uint32_t I2S_TX_Buffer[];
aidan1971 0:8f28f25e3435 269 static uint32_t *BufRX_L_safe;
aidan1971 0:8f28f25e3435 270 static uint32_t *BufRX_R_safe;
aidan1971 0:8f28f25e3435 271 static uint32_t *BufTX_L_safe;
aidan1971 0:8f28f25e3435 272 static uint32_t *BufTX_R_safe;
aidan1971 0:8f28f25e3435 273 static uint32_t TX_block_size;
aidan1971 0:8f28f25e3435 274 static uint32_t RX_block_size;
aidan1971 0:8f28f25e3435 275 static uint32_t SYNC_attach_type;
aidan1971 0:8f28f25e3435 276 static uint32_t TX_attach_type;
aidan1971 0:8f28f25e3435 277 static uint32_t RX_attach_type;
aidan1971 0:8f28f25e3435 278 static uint32_t RX_DMAch;
aidan1971 0:8f28f25e3435 279 static uint32_t TX_DMAch;
aidan1971 0:8f28f25e3435 280 static IRQn SYNC_swIRQ;
aidan1971 0:8f28f25e3435 281 static IRQn TX_swIRQ;
aidan1971 0:8f28f25e3435 282 static IRQn RX_swIRQ;
aidan1971 0:8f28f25e3435 283 static Callback<void()> TX_user_func;
aidan1971 0:8f28f25e3435 284 static Callback<void()> RX_user_func;
aidan1971 0:8f28f25e3435 285 static Callback<void()> SYNC_user_func;
aidan1971 0:8f28f25e3435 286
aidan1971 0:8f28f25e3435 287 uint32_t TX_bs_bytes;
aidan1971 0:8f28f25e3435 288 uint32_t RX_bs_bytes;
aidan1971 0:8f28f25e3435 289 bool SYNC_run;
aidan1971 0:8f28f25e3435 290 bool TX_run;
aidan1971 0:8f28f25e3435 291 bool RX_run;
aidan1971 0:8f28f25e3435 292
aidan1971 0:8f28f25e3435 293 bool SYNC_attached;
aidan1971 0:8f28f25e3435 294 bool TX_attached;
aidan1971 0:8f28f25e3435 295 bool RX_attached;
aidan1971 0:8f28f25e3435 296 bool TX_shift;
aidan1971 0:8f28f25e3435 297 bool RX_shift;
aidan1971 0:8f28f25e3435 298 };
aidan1971 0:8f28f25e3435 299 }
aidan1971 0:8f28f25e3435 300 #endif