Aidan Walton / SGTL5000 Featured

Library to control and transfer data from NXP SGTL5000. As used on the Teensy Audio Shield. It uses DMA to transfer I2S FIFO data.

The Library now supports dual codecs. Allowing all 4 channels of the Teensy I2S interface to RX and TX data to separate SGTL5000 devices.

The ISR routines that handles pointer swaps for double buffering has been fully coded in assembler to reduce overhead and now takes < 800nS per FIFO transfer when using all 4 channels.

Support added for all typical sample rates and system Clock speeds of 96Mhz or 120Mhz.

Pause and Resume functions added to allow quick and simple suppression of IRQs and stream halting and restart. This required software triggered IRQ, in order to ensure accurate word sync control.

sgtl5000.h@3:62c03088f256, 2017-06-16 (annotated)

Committer:
aidan1971
Date:
Fri Jun 16 12:57:54 2017 +0000
Revision:
3:62c03088f256
Parent:
0:8f28f25e3435
Child:
4:91354c908416
Documentation added and function types corrected to match accurate return types

Who changed what in which revision?

UserRevisionLine numberNew contents of line
aidan1971 3:62c03088f256 1 /*!
aidan1971 0:8f28f25e3435 2 @ author Aidan Walton, aidan.walton@gmail.com
aidan1971 0:8f28f25e3435 3
aidan1971 0:8f28f25e3435 4 @section LICENSE
aidan1971 0:8f28f25e3435 5 * Permission is hereby granted, free of charge, to any person obtaining a copy
aidan1971 0:8f28f25e3435 6 * of this software and associated documentation files (the "Software"), to deal
aidan1971 0:8f28f25e3435 7 * in the Software without restriction, including without limitation the rights
aidan1971 0:8f28f25e3435 8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
aidan1971 0:8f28f25e3435 9 * copies of the Software, and to permit persons to whom the Software is
aidan1971 0:8f28f25e3435 10 * furnished to do so, subject to the following conditions:
aidan1971 0:8f28f25e3435 11 *
aidan1971 0:8f28f25e3435 12 * The above copyright notice, development funding notice, and this permission
aidan1971 0:8f28f25e3435 13 * notice shall be included in all copies or substantial portions of the Software.
aidan1971 0:8f28f25e3435 14 *
aidan1971 0:8f28f25e3435 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
aidan1971 0:8f28f25e3435 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
aidan1971 0:8f28f25e3435 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
aidan1971 0:8f28f25e3435 18 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
aidan1971 0:8f28f25e3435 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
aidan1971 0:8f28f25e3435 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
aidan1971 0:8f28f25e3435 21 * THE SOFTWARE.
aidan1971 0:8f28f25e3435 22
aidan1971 0:8f28f25e3435 23 @section DESCRIPTION
aidan1971 0:8f28f25e3435 24 Library for NXP SGTL5000 Codec
aidan1971 0:8f28f25e3435 25 */
aidan1971 0:8f28f25e3435 26
aidan1971 0:8f28f25e3435 27 #ifndef MBED_SGTL5000_H
aidan1971 0:8f28f25e3435 28 #define MBED_SGTL5000_H
aidan1971 0:8f28f25e3435 29
aidan1971 0:8f28f25e3435 30 #include "mbed.h"
aidan1971 0:8f28f25e3435 31 #include "platform.h"
aidan1971 0:8f28f25e3435 32 #include "Callback.h"
aidan1971 0:8f28f25e3435 33 #include "sgtl5000_defs.h"
aidan1971 0:8f28f25e3435 34
aidan1971 3:62c03088f256 35 /** SGTL5000 namespace
aidan1971 3:62c03088f256 36 */
aidan1971 0:8f28f25e3435 37 namespace SGTL5000
aidan1971 0:8f28f25e3435 38 {
aidan1971 0:8f28f25e3435 39
aidan1971 3:62c03088f256 40 /*! SGTL5000 codec driver class
aidan1971 3:62c03088f256 41 */
aidan1971 3:62c03088f256 42 /*! Class for NXP SGTL5000 codec instance.
aidan1971 3:62c03088f256 43 * @code
aidan1971 3:62c03088f256 44 * #include 'SGTL5000.h'
aidan1971 3:62c03088f256 45 *
aidan1971 3:62c03088f256 46 * SGTL5000::SGTL5000 codec(I2C_SDA, I2C_SCL);
aidan1971 3:62c03088f256 47 *
aidan1971 3:62c03088f256 48 * static q31_t *RX_AudioL = NULL;
aidan1971 3:62c03088f256 49 * static q31_t *RX_AudioR = NULL;
aidan1971 3:62c03088f256 50 * static q31_t *TX_AudioL = NULL;
aidan1971 3:62c03088f256 51 * static q31_t *TX_AudioR = NULL;
aidan1971 3:62c03088f256 52 *
aidan1971 3:62c03088f256 53 * const uint32_t I2S_FIFO_BS = 4;
aidan1971 3:62c03088f256 54 *
aidan1971 3:62c03088f256 55 *
aidan1971 3:62c03088f256 56 * uint32_t main()
aidan1971 3:62c03088f256 57 * {
aidan1971 3:62c03088f256 58 * codec.modify_i2c(SGTL5000_ANA_HP_CTRL, 0x18, SGTL5000_ANA_HP_CTRL_HP_VOL_RIGHT_MASK); // Headphone volume control with 0.5 dB steps.0x00 = +12 dB, 0x01 = +11.5 dB, 0x18 = 0 dB,...0x7F = -51.5 dB
aidan1971 3:62c03088f256 59 * codec.modify_i2c(SGTL5000_ANA_HP_CTRL, 0x18, SGTL5000_ANA_HP_CTRL_HP_VOL_LEFT_MASK);
aidan1971 3:62c03088f256 60 *
aidan1971 3:62c03088f256 61 * codec.attach_SYNC_NB((uint32_t)&I2S_SYNC_ISR);
aidan1971 3:62c03088f256 62 * codec.freq(96);
aidan1971 3:62c03088f256 63 * codec.start_SYNC((uint32_t)&RX_AudioL, (uint32_t)&RX_AudioR, (uint32_t)&TX_AudioL, (uint32_t)&TX_AudioR, I2S_FIFO_BS)
aidan1971 3:62c03088f256 64 * }
aidan1971 3:62c03088f256 65 *
aidan1971 3:62c03088f256 66 * void I2S_SYNC_ISR(void)
aidan1971 3:62c03088f256 67 * {
aidan1971 3:62c03088f256 68 * for(uint32_t i = 0; i < (I2S_FIFO_BS >> 1); ++i)
aidan1971 3:62c03088f256 69 * {
aidan1971 3:62c03088f256 70 * TX_AudioL[i] = RX_AudioL[i];
aidan1971 3:62c03088f256 71 * TX_AudioR[i] = RX_AudioR[i];
aidan1971 3:62c03088f256 72 * }
aidan1971 3:62c03088f256 73 * }
aidan1971 3:62c03088f256 74 @endcode
aidan1971 3:62c03088f256 75 */
aidan1971 0:8f28f25e3435 76 class SGTL5000
aidan1971 0:8f28f25e3435 77
aidan1971 0:8f28f25e3435 78 {
aidan1971 0:8f28f25e3435 79 public:
aidan1971 3:62c03088f256 80 //Constructor
aidan1971 3:62c03088f256 81 /*!
aidan1971 0:8f28f25e3435 82 @brief Create an SGTL5000 object defined on the I2C port using DMA transfers of I2S data. The class is not defined as a singleton, as future development may require
aidan1971 3:62c03088f256 83 multiple instances. However currently it should only be instantiated once. The class is wrapped in the SGTL5000 namespace to avoid collisions with statics
aidan1971 3:62c03088f256 84 needed by the ISRs.
aidan1971 0:8f28f25e3435 85
aidan1971 0:8f28f25e3435 86 @param i2c_sda i2c Serial data pin (D18 Teensy 3.2 header / PTB3 MK20DX256)
aidan1971 0:8f28f25e3435 87 @param i2c_scl i2c Serial clock pin (D19 Teensy 3.2 header / PTB2 MK20DX256)
aidan1971 0:8f28f25e3435 88 @param i2c_freq Frequency in Hz at which the i2c codec interface clocks data
aidan1971 0:8f28f25e3435 89 @param i2c_ctrl_adr0_cs State on SGTL5000 CTRL_ADR0_CS pin i2c addr = 0n01010(R/W) :R/W = 1 to write R/W = 0 to read, n = 0 pull down / n = 1 pull up on CTRL_ADR0_CS pin of SGTL5000)
aidan1971 0:8f28f25e3435 90
aidan1971 0:8f28f25e3435 91
aidan1971 0:8f28f25e3435 92 // Pin Configs for i2s hardcoded as follows to match Teensy Audio Shield
aidan1971 0:8f28f25e3435 93 i2s_mclk i2s master clock (D11 Teensy 3.2 header / PTC6 MK20DX256)
aidan1971 0:8f28f25e3435 94 i2s_bclk i2s bit clock (D9 Teensy 3.2 header / PTC3 MK20DX256)
aidan1971 0:8f28f25e3435 95 i2s_fs i2s Frame Sync / L/R clock / WordSelect (D23 Teensy 3.2 header / PTC2 MK20DX256)
aidan1971 0:8f28f25e3435 96 i2s_rx i2s tx_data (from bus master perspective) (D22 Teensy 3.2 header / PTC1 MK20DX256)
aidan1971 0:8f28f25e3435 97 i2s_tx i2s rx_data (from bus master perspective) (D13 Teensy 3.2 header /PTC5 MK20DX256)
aidan1971 0:8f28f25e3435 98
aidan1971 0:8f28f25e3435 99 */
aidan1971 0:8f28f25e3435 100 SGTL5000(PinName i2c_sda, PinName i2c_scl, int i2c_freq = 100000, bool i2c_ctrl_adr0_cs = 0);
aidan1971 0:8f28f25e3435 101
aidan1971 3:62c03088f256 102 /*!
aidan1971 3:62c03088f256 103 @brief Read 16bit register of SGTL5000
aidan1971 3:62c03088f256 104 @param reg_addr 16bit address of the codec control register
aidan1971 3:62c03088f256 105 @param data 16bit data to read from the address
aidan1971 3:62c03088f256 106 @param mask 16bit mask applied over the data read from the codec. The final returned value is the register data automatically shifted to the position of the first masked bit.
aidan1971 3:62c03088f256 107 @returns 0 = register data, -1 = fail
aidan1971 3:62c03088f256 108 */
aidan1971 3:62c03088f256 109 int32_t read_i2c(uint32_t reg_addr, uint32_t mask = 0xFFFF);
aidan1971 3:62c03088f256 110
aidan1971 3:62c03088f256 111 /*!
aidan1971 3:62c03088f256 112 @brief Write 16bit register of SGTL5000
aidan1971 3:62c03088f256 113 @param reg_addr 16bit address of the codec control register
aidan1971 3:62c03088f256 114 @param data 16bit data to write into the address
aidan1971 3:62c03088f256 115 @returns 0 = success, -1 = fail
aidan1971 3:62c03088f256 116 */
aidan1971 3:62c03088f256 117 int32_t write_i2c(uint32_t reg_addr, uint32_t data);
aidan1971 3:62c03088f256 118
aidan1971 3:62c03088f256 119 /*!
aidan1971 3:62c03088f256 120 @brief Modify masked bits within 16bit register of SGTL5000
aidan1971 3:62c03088f256 121 @param reg_addr 16bit address of the codec control register
aidan1971 3:62c03088f256 122 @param data 16bit data to write into the address
aidan1971 3:62c03088f256 123 @param mask 16bit mask of the bits to modify.
aidan1971 3:62c03088f256 124 The function automatically shifts the data to the position of the first masked bit.
aidan1971 3:62c03088f256 125 @returns 0 = success, -1 = fail
aidan1971 3:62c03088f256 126 */
aidan1971 3:62c03088f256 127 int32_t modify_i2c(uint32_t reg_addr, uint32_t data, uint32_t mask);
aidan1971 3:62c03088f256 128
aidan1971 3:62c03088f256 129 /*!
aidan1971 0:8f28f25e3435 130 @brief Attach a callback function to TX
aidan1971 3:62c03088f256 131 @param func Address of the user function to be called from the TX FIFO triggered ISR.
aidan1971 3:62c03088f256 132 This is blocking. If the user function does not complete before the next DMA completes the system will likely crash,
aidan1971 3:62c03088f256 133 however using this function avoids the latency of an IRQ stack push.
aidan1971 3:62c03088f256 134 @returns 0 = success, -1 = fail.
aidan1971 3:62c03088f256 135 Fails if already attached, must detach first.
aidan1971 0:8f28f25e3435 136 */
aidan1971 0:8f28f25e3435 137 int32_t attach_TX(Callback<void()> func);
aidan1971 3:62c03088f256 138
aidan1971 3:62c03088f256 139 /*!
aidan1971 3:62c03088f256 140 @brief Attach an ISR function to DMA TX
aidan1971 3:62c03088f256 141 @param user_ISR Address of the user function to be assigned as the NVIC vector for the DMA TX FIFO triggered user_ISR.
aidan1971 0:8f28f25e3435 142 @param irq_pri Set the system wide priority of the user_ISR.
aidan1971 0:8f28f25e3435 143 @param sw_irq The IRQ assigned. Default uses Reserved54_IRQn. See "MK20DX256.h" for available.
aidan1971 0:8f28f25e3435 144 This is non-blocking provided the priority of the IRQ associated with user_ISR is lower than the priority of the DMA triggered ISR.
aidan1971 0:8f28f25e3435 145 It can be useful to use a non-blocking call, however this involves the extra time needed to push the stack and manageing IRQ priorities
aidan1971 0:8f28f25e3435 146 across the whole system needs consideration.
aidan1971 0:8f28f25e3435 147 */
aidan1971 3:62c03088f256 148 void attach_TX_NB(uint32_t user_ISR, uint32_t irq_pri = 1, IRQn sw_irq = Reserved54_IRQn);
aidan1971 3:62c03088f256 149
aidan1971 3:62c03088f256 150 /*!
aidan1971 0:8f28f25e3435 151 @brief Stop TX channel and flag as detached.
aidan1971 0:8f28f25e3435 152 During running stream, the callback based function can not be changed. However changes to the NB IRQ based attachment can have the vector changed on-the-fly
aidan1971 0:8f28f25e3435 153 */
aidan1971 0:8f28f25e3435 154 void detach_TX(void);
aidan1971 0:8f28f25e3435 155
aidan1971 3:62c03088f256 156 /*!
aidan1971 0:8f28f25e3435 157 @brief Stops i2s TX channel but maintains clocking.
aidan1971 0:8f28f25e3435 158 */
aidan1971 3:62c03088f256 159 void stop_TX(void);
aidan1971 3:62c03088f256 160
aidan1971 3:62c03088f256 161 /*!
aidan1971 0:8f28f25e3435 162 @brief Starts the codec I2S interface and begins transferring TX buffers. Transfers use DMA.
aidan1971 0:8f28f25e3435 163 @param BufTX_L_safe A pointer address to the TX Left channel data.
aidan1971 0:8f28f25e3435 164 The pointer address is managed by the driver and changes to implement a double buffer.
aidan1971 0:8f28f25e3435 165 It is suggested that a suitable declaration in the users code would be in the form: 'q31_t *TX_AudioL = NULL;'
aidan1971 0:8f28f25e3435 166 Although volatile is not strictly necessary both the pointer address and the data pointed to, are changing outside the flow of the user code.
aidan1971 0:8f28f25e3435 167 To pass into the class, dereference this pointer and cast as uint32_t, as follows: 'codec.start_SYNC((uint32_t)&TX_AudioL .....'
aidan1971 0:8f28f25e3435 168 @param BufTX_R_safe A pointer address to the TX Right channel data.
aidan1971 0:8f28f25e3435 169 @param block_size 2 | 4 | 8 words of both Left and Right channels combined.
aidan1971 0:8f28f25e3435 170 This defines the number of samples that are transferred to the TX FIFO each time a FIFO demand is detected.
aidan1971 0:8f28f25e3435 171 @param TX_shift True = The MS16bits of TX buffer are sent to the TX FIFO. Default = true.
aidan1971 0:8f28f25e3435 172 False = The LS16bits of TX buffer are sent to the TX FIFO.
aidan1971 0:8f28f25e3435 173 @param tx_DMAch Defines the system DMA channel to assign to the TX transfer. Default is 15.
aidan1971 0:8f28f25e3435 174 15 is used as default to avoid using channels 0 - 3 which are the only channels available for gated triggers.
aidan1971 0:8f28f25e3435 175 Gated triggering is not needed, so these 4 channels are avoided.
aidan1971 0:8f28f25e3435 176 @param DMA_irq_pri Default = 0. Highest priority. This is the priority of the I2S TX DMA demands.
aidan1971 3:62c03088f256 177 @returns 0 = success, -1 = fail
aidan1971 3:62c03088f256 178 Fails on variable sanity checks.
aidan1971 0:8f28f25e3435 179 */
aidan1971 0:8f28f25e3435 180 int32_t start_TX(uint32_t BufTX_L_safe, uint32_t BufTX_R_safe,
aidan1971 0:8f28f25e3435 181 uint32_t block_size = 4, bool _TX_shift = true, uint32_t _TX_DMAch = 15, uint32_t DMA_irq_pri = 0);
aidan1971 0:8f28f25e3435 182
aidan1971 3:62c03088f256 183 /*!
aidan1971 0:8f28f25e3435 184 @brief Attach a callback function to RX
aidan1971 0:8f28f25e3435 185 @param func User function to be called from the RX FIFO triggered ISR.
aidan1971 0:8f28f25e3435 186 This is blocking. If the user function does not complete before the next DMA completes the system will crash,
aidan1971 0:8f28f25e3435 187 however using this function avoids the latency of a stack push.
aidan1971 3:62c03088f256 188 @returns 0 = success, -1 = fail.
aidan1971 3:62c03088f256 189 Fails if already attached, must detach first.
aidan1971 0:8f28f25e3435 190 */
aidan1971 0:8f28f25e3435 191 int32_t attach_RX(Callback<void()> func);
aidan1971 3:62c03088f256 192
aidan1971 3:62c03088f256 193 /*!
aidan1971 3:62c03088f256 194 @brief Attach an ISR function to DMA RX
aidan1971 0:8f28f25e3435 195 @param user_ISR User function to be assigned as the NVIC vector for the DMA RX FIFO triggered user_ISR.
aidan1971 0:8f28f25e3435 196 @param irq_pri Set the system wide priority of the user_ISR.
aidan1971 0:8f28f25e3435 197 @param sw_irq The IRQ assigned. Default uses Reserved55_IRQn. See "MK20DX256.h" for available.
aidan1971 0:8f28f25e3435 198 This is non-blocking provided the priority of the IRQ associated with user_ISR is lower than the priority of the DMA triggered ISR.
aidan1971 0:8f28f25e3435 199 It can be useful to use a non-blocking call, however this involves the extra time needed to push the stack and manageing IRQ priorities
aidan1971 0:8f28f25e3435 200 across the whole system needs consideration.
aidan1971 0:8f28f25e3435 201 */
aidan1971 3:62c03088f256 202 void attach_RX_NB(uint32_t user_ISR, uint32_t irq_pri = 1, IRQn sw_irq = Reserved55_IRQn);
aidan1971 3:62c03088f256 203
aidan1971 3:62c03088f256 204 /*!
aidan1971 0:8f28f25e3435 205 @brief Stop RX channel and flag as detached.
aidan1971 0:8f28f25e3435 206 During running stream, the callback based function can not be changed. However changes to the NB IRQ based attachment can have the vector changed on-the-fly
aidan1971 0:8f28f25e3435 207 */
aidan1971 0:8f28f25e3435 208 void detach_RX(void);
aidan1971 0:8f28f25e3435 209
aidan1971 3:62c03088f256 210 /*!
aidan1971 0:8f28f25e3435 211 @brief Stops i2s RX channel but maintains clocking.
aidan1971 0:8f28f25e3435 212 */
aidan1971 3:62c03088f256 213 void stop_RX(void);
aidan1971 3:62c03088f256 214
aidan1971 3:62c03088f256 215 /*!
aidan1971 0:8f28f25e3435 216 @brief Starts the codec I2S interface and begins transferring RX buffers. Transfers use DMA.
aidan1971 0:8f28f25e3435 217 @param BufRX_L_safe A pointer address to the RX Left channel data.
aidan1971 0:8f28f25e3435 218 The pointer address is managed by the driver and changes to implement a double buffer.
aidan1971 0:8f28f25e3435 219 It is suggested that a suitable declaration in the users code would be in the form: 'q31_t *RX_AudioL = NULL;'
aidan1971 0:8f28f25e3435 220 To pass into the class, dereference this pointer and cast as uint32_t, as follows: 'codec.start_SYNC((uint32_t)&RX_AudioL .....'
aidan1971 0:8f28f25e3435 221 @param BufRX_R_safe A pointer address to the RX Right channel data.
aidan1971 0:8f28f25e3435 222 @param block_size 2 | 4 | 8 words of both Left and Right channels combined.
aidan1971 0:8f28f25e3435 223 This defines the number of samples that are transferred to the RX FIFO each time a FIFO demand is detected.
aidan1971 0:8f28f25e3435 224 @param RX_shift True = The 16bits of RX FIFO data are shifted to the MSBs of the RX buffer. Default = true
aidan1971 0:8f28f25e3435 225 False = The 16bits of RX FIFO data are placed in the LSBs of the RX buffer
aidan1971 0:8f28f25e3435 226 Note: If data is not shifted, the 32bit word delivered to the user will not be sign extended.
aidan1971 0:8f28f25e3435 227 @param rx_DMAch Defines the system DMA channel to assign to the RX transfer. Default is 14.
aidan1971 0:8f28f25e3435 228 14 is used as default to avoid using channels 0 - 3 which are the only channels available for gated triggers.
aidan1971 0:8f28f25e3435 229 Gated triggering is not needed, so these 4 channels are avoided.
aidan1971 0:8f28f25e3435 230 @param DMA_irq_pri Default = 0. Highest priority. This is the priority of the I2S RX DMA demands.
aidan1971 3:62c03088f256 231 @returns 0 = success, -1 = fail
aidan1971 3:62c03088f256 232 Fails on variable sanity checks.
aidan1971 0:8f28f25e3435 233 */
aidan1971 0:8f28f25e3435 234 int32_t start_RX(uint32_t BufRX_L_safe, uint32_t BufRX_R_safe,
aidan1971 0:8f28f25e3435 235 uint32_t block_size = 4, bool _RX_shift = true, uint32_t _RX_DMAch = 14, uint32_t DMA_irq_pri = 0);
aidan1971 0:8f28f25e3435 236
aidan1971 3:62c03088f256 237 /*!
aidan1971 0:8f28f25e3435 238 @brief Attach a callback function to DMA SYNC
aidan1971 0:8f28f25e3435 239 @param func User function to be called from the DMA SYNC FIFO triggered ISR.
aidan1971 0:8f28f25e3435 240 This is blocking. If the user function does not complete before the next DMA triggered IRQ the system will crash,
aidan1971 0:8f28f25e3435 241 however using this function avoids the latency of a stack push.
aidan1971 3:62c03088f256 242 @returns 0 = success, -1 = fail.
aidan1971 3:62c03088f256 243 Fails if already attached, must detach first.
aidan1971 0:8f28f25e3435 244 */
aidan1971 0:8f28f25e3435 245 int32_t attach_SYNC(Callback<void()> func);
aidan1971 3:62c03088f256 246
aidan1971 3:62c03088f256 247 /*!
aidan1971 0:8f28f25e3435 248 @brief Attach a ISR function to DMA SYNC
aidan1971 0:8f28f25e3435 249 @param user_ISR User function to be assigned as the NVIC vector for the DMA SYNC FIFO triggered user_ISR.
aidan1971 0:8f28f25e3435 250 @param irq_pri Set the system wide priority of the user_ISR.
aidan1971 0:8f28f25e3435 251 @param sw_irq The IRQ assigned. Default uses Reserved53_IRQn. See "MK20DX256.h" for available.
aidan1971 0:8f28f25e3435 252 This creates a non-blocking call, which tests to see if the users ISR has completed before calling again.
aidan1971 0:8f28f25e3435 253 It requires that the priority of the IRQ associated with user_ISR is lower than the priority of the DMA triggered ISR.
aidan1971 0:8f28f25e3435 254 It can be useful to use a non-blocking call, however this involves the extra time needed to push the stack and manageing IRQ priorities
aidan1971 0:8f28f25e3435 255 across the whole system needs consideration.
aidan1971 0:8f28f25e3435 256 */
aidan1971 3:62c03088f256 257 void attach_SYNC_NB(uint32_t user_ISR, uint32_t irq_pri = 1, IRQn sw_irq = Reserved53_IRQn);
aidan1971 0:8f28f25e3435 258
aidan1971 3:62c03088f256 259 /*!
aidan1971 0:8f28f25e3435 260 @brief Stop both TX & RX channels and flag as detached.
aidan1971 0:8f28f25e3435 261 During running stream, the callback based function can not be changed. However changes to the NB IRQ based attachment can have the vector changed on-the-fly
aidan1971 0:8f28f25e3435 262 */
aidan1971 0:8f28f25e3435 263 void detach_SYNC(void);
aidan1971 0:8f28f25e3435 264
aidan1971 3:62c03088f256 265 /**
aidan1971 0:8f28f25e3435 266 @brief Starts the codec I2S interface and begins transferring RX and TX buffers. Transfers use DMA.
aidan1971 0:8f28f25e3435 267 @param BufRX_L_safe A pointer address to the RX Left channel data.
aidan1971 0:8f28f25e3435 268 The pointer address is managed by the driver and changes to implement a double buffer.
aidan1971 0:8f28f25e3435 269 It is suggested that a suitable declaration in the users code would be in the form: 'q31_t *RX_AudioL = NULL;'
aidan1971 0:8f28f25e3435 270 To pass into the class, dereference this pointer and cast as uint32_t, as follows: 'codec.start_SYNC((uint32_t)&RX_AudioL .....'
aidan1971 0:8f28f25e3435 271 @param BufRX_L_safe A pointer address to the RX Right channel data.
aidan1971 0:8f28f25e3435 272 @param BufRX_L_safe A pointer address to the TX Left channel data.
aidan1971 0:8f28f25e3435 273 @param BufRX_L_safe A pointer address to the TX Right channel data.
aidan1971 0:8f28f25e3435 274 @param block_size 2 | 4 | 8 words of both Left and Right channels combined.
aidan1971 0:8f28f25e3435 275 This defines the number of samples that are transferred to both FIFOs each time a FIFO demand is detected.
aidan1971 0:8f28f25e3435 276 @param _RX_shift True = The 16bits of RX FIFO data are shifted to the MSBs of the RX buffer. Default = true
aidan1971 0:8f28f25e3435 277 False = The 16bits of RX FIFO data are placed in the LSBs of the RX buffer.
aidan1971 0:8f28f25e3435 278 Note: If data is not shifted, the 32bit word delivered to the user will not be sign extended.
aidan1971 0:8f28f25e3435 279 @param _TX_shift True = The MS16bits of TX buffer are sent to the TX FIFO. Default = true.
aidan1971 0:8f28f25e3435 280 False = The LS16bits of TX buffer are sent to the TX FIFO.
aidan1971 0:8f28f25e3435 281 @param _RX_DMAch Defines the system DMA channel to assign to the RX transfer. Default is 14.
aidan1971 0:8f28f25e3435 282 @param _TX_DMAch Defines the system DMA channel to assign to the TX transfer. Default is 15.
aidan1971 0:8f28f25e3435 283 14 & 15 are used as default to avoid using channels 0 - 3 which are the only channels available for gated triggers.
aidan1971 0:8f28f25e3435 284 Gated triggering is not needed, so these 4 channels are avoided.
aidan1971 0:8f28f25e3435 285 @param DMA_irq_pri Default = 0. Highest priority. This is the priority of the I2S DMA demands.
aidan1971 3:62c03088f256 286 @returns 0 = success, -1 = fail
aidan1971 3:62c03088f256 287 Fails on variable sanity checks.
aidan1971 0:8f28f25e3435 288 */
aidan1971 0:8f28f25e3435 289 int32_t start_SYNC(uint32_t BufRX_L_safe, uint32_t BufRX_R_safe, uint32_t BufTX_L_safe, uint32_t BufTX_R_safe,
aidan1971 0:8f28f25e3435 290 uint32_t block_size = 4, bool _RX_shift = true, bool _TX_shift = true, uint32_t _RX_DMAch = 14, uint32_t _TX_DMAch = 15, uint32_t DMA_irq_pri = 0);
aidan1971 0:8f28f25e3435 291
aidan1971 3:62c03088f256 292 /*!
aidan1971 0:8f28f25e3435 293 @brief Stops i2s TX & RX channels but maintains clocking.
aidan1971 0:8f28f25e3435 294 */
aidan1971 3:62c03088f256 295 void stop_SYNC(void);
aidan1971 0:8f28f25e3435 296
aidan1971 3:62c03088f256 297 /*!
aidan1971 0:8f28f25e3435 298 @brief Set codec and i2s Sampling frequency
aidan1971 0:8f28f25e3435 299 @param rate 8, 11, 12, 16, 22, 24, 32, 44, 48, 96, 192
aidan1971 0:8f28f25e3435 300 Base sampling rate of the codec
aidan1971 0:8f28f25e3435 301
aidan1971 0:8f28f25e3435 302 In all cases the SGTL5000 is programmed to use MCLK 256 times faster than sampling freq.
aidan1971 0:8f28f25e3435 303 MCU MCLK output = MCLK_Input((FRACT + 1)/(DIVIDE + 1))
aidan1971 0:8f28f25e3435 304 MCU MCLK Divide Register ratio is therefore = (Fs * 256)/PLL Clk
aidan1971 0:8f28f25e3435 305 The Teensy 3.1 & 3.2 have PLL freq @ 96MHz
aidan1971 0:8f28f25e3435 306
aidan1971 3:62c03088f256 307 Note: To achieve some of these rates the codec SYS_FS is adjusted.
aidan1971 0:8f28f25e3435 308 This needs to be considered for several internal codec processes such as filter co-efficients and AVC.
aidan1971 3:62c03088f256 309 @returns 0 = success, -1 = fail
aidan1971 0:8f28f25e3435 310 */
aidan1971 0:8f28f25e3435 311 int32_t freq(uint32_t rate);
aidan1971 3:62c03088f256 312 /*!
aidan1971 3:62c03088f256 313 @brief Read debug data from the codec
aidan1971 3:62c03088f256 314 @param index 0-15
aidan1971 3:62c03088f256 315 Just a simple way for user code to grab running variables if you need it.
aidan1971 3:62c03088f256 316 @returns 0 = success, -1 = fail
aidan1971 3:62c03088f256 317 */
aidan1971 0:8f28f25e3435 318 uint32_t read_debug(uint32_t index);
aidan1971 0:8f28f25e3435 319
aidan1971 0:8f28f25e3435 320
aidan1971 0:8f28f25e3435 321 protected:
aidan1971 0:8f28f25e3435 322
aidan1971 0:8f28f25e3435 323
aidan1971 0:8f28f25e3435 324 static uint32_t volatile debug[16];
aidan1971 0:8f28f25e3435 325
aidan1971 0:8f28f25e3435 326
aidan1971 0:8f28f25e3435 327
aidan1971 0:8f28f25e3435 328
aidan1971 0:8f28f25e3435 329
aidan1971 0:8f28f25e3435 330 private:
aidan1971 0:8f28f25e3435 331 I2C mI2C;
aidan1971 0:8f28f25e3435 332 int i2c_addr;
aidan1971 0:8f28f25e3435 333
aidan1971 0:8f28f25e3435 334 void init_i2s(void); // Configure I2S Default Settings
aidan1971 0:8f28f25e3435 335
aidan1971 0:8f28f25e3435 336 void init_codec(void); // Configure codec Default Settings
aidan1971 0:8f28f25e3435 337
aidan1971 0:8f28f25e3435 338 void init_DMA(void); // Configure SYNC DMA settings on MK20DX256
aidan1971 0:8f28f25e3435 339
aidan1971 0:8f28f25e3435 340 static void tx_dma_ISR(void); // Handle TX DMA transfers complete
aidan1971 0:8f28f25e3435 341
aidan1971 0:8f28f25e3435 342 static void rx_dma_ISR(void); // Handle RX DMA transfers complete
aidan1971 0:8f28f25e3435 343
aidan1971 0:8f28f25e3435 344 static void sync_dma_ISR(void); // Handle SYNC DMA transfers complete
aidan1971 0:8f28f25e3435 345
aidan1971 0:8f28f25e3435 346 static void tx_I2S_ISR(void); // Handle TX word start allignment
aidan1971 0:8f28f25e3435 347
aidan1971 0:8f28f25e3435 348 static void rx_I2S_ISR(void); // Handle RX word start allignment
aidan1971 0:8f28f25e3435 349
aidan1971 0:8f28f25e3435 350 static void sync_I2S_ISR(void); // Handle SYNC word start allignment
aidan1971 0:8f28f25e3435 351
aidan1971 0:8f28f25e3435 352
aidan1971 0:8f28f25e3435 353 static uint32_t I2S_RX_Buffer[]; // Define global statics needed within ISRs
aidan1971 0:8f28f25e3435 354 static uint32_t I2S_TX_Buffer[];
aidan1971 0:8f28f25e3435 355 static uint32_t *BufRX_L_safe;
aidan1971 0:8f28f25e3435 356 static uint32_t *BufRX_R_safe;
aidan1971 0:8f28f25e3435 357 static uint32_t *BufTX_L_safe;
aidan1971 0:8f28f25e3435 358 static uint32_t *BufTX_R_safe;
aidan1971 0:8f28f25e3435 359 static uint32_t TX_block_size;
aidan1971 0:8f28f25e3435 360 static uint32_t RX_block_size;
aidan1971 0:8f28f25e3435 361 static uint32_t SYNC_attach_type;
aidan1971 0:8f28f25e3435 362 static uint32_t TX_attach_type;
aidan1971 0:8f28f25e3435 363 static uint32_t RX_attach_type;
aidan1971 0:8f28f25e3435 364 static uint32_t RX_DMAch;
aidan1971 0:8f28f25e3435 365 static uint32_t TX_DMAch;
aidan1971 0:8f28f25e3435 366 static IRQn SYNC_swIRQ;
aidan1971 0:8f28f25e3435 367 static IRQn TX_swIRQ;
aidan1971 0:8f28f25e3435 368 static IRQn RX_swIRQ;
aidan1971 0:8f28f25e3435 369 static Callback<void()> TX_user_func;
aidan1971 0:8f28f25e3435 370 static Callback<void()> RX_user_func;
aidan1971 0:8f28f25e3435 371 static Callback<void()> SYNC_user_func;
aidan1971 0:8f28f25e3435 372
aidan1971 0:8f28f25e3435 373 uint32_t TX_bs_bytes;
aidan1971 0:8f28f25e3435 374 uint32_t RX_bs_bytes;
aidan1971 0:8f28f25e3435 375 bool SYNC_run;
aidan1971 0:8f28f25e3435 376 bool TX_run;
aidan1971 0:8f28f25e3435 377 bool RX_run;
aidan1971 0:8f28f25e3435 378
aidan1971 0:8f28f25e3435 379 bool SYNC_attached;
aidan1971 0:8f28f25e3435 380 bool TX_attached;
aidan1971 0:8f28f25e3435 381 bool RX_attached;
aidan1971 0:8f28f25e3435 382 bool TX_shift;
aidan1971 0:8f28f25e3435 383 bool RX_shift;
aidan1971 0:8f28f25e3435 384 };
aidan1971 0:8f28f25e3435 385 }
aidan1971 0:8f28f25e3435 386 #endif