Zbigniew Druzbacki / Mbed 2 deprecated SPI_Slave

SPI slave program to enable communication between the FPGA and the STM32L432 board.

Dependencies:   mbed

DMA_SPI.cpp@14:7bbaafa22f8d, 2019-05-05 (annotated)

Committer:
Zbyszek
Date:
Sun May 05 01:08:22 2019 +0000
Revision:
14:7bbaafa22f8d
Parent:
13:c7e8e277f884
Child:
15:791f35b0f220
Commented the code and deleted variables that were not used

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Zbyszek 8:e87027349167 1 #include "mbed.h"
Zbyszek 8:e87027349167 2 #include "DMA_SPI.h"
Zbyszek 8:e87027349167 3
Zbyszek 9:9ed9dffd602a 4 int16_t data_to_transmit[12];
Zbyszek 9:9ed9dffd602a 5 int16_t received_data[12];
Zbyszek 13:c7e8e277f884 6 int16_t IMU_Data_Array[12];
Zbyszek 11:366f1186c121 7
Zbyszek 11:366f1186c121 8
Zbyszek 11:366f1186c121 9 int16_t SampleFIFO[10][12];
Zbyszek 11:366f1186c121 10 extern int pointerOS = 0;
Zbyszek 11:366f1186c121 11 extern int pointerNS = 0;
Zbyszek 11:366f1186c121 12 extern int pointerFS = 0;
Zbyszek 11:366f1186c121 13 extern char newDataFlag = 0;
Zbyszek 13:c7e8e277f884 14 volatile extern char dataRequestFlag = 0;
Zbyszek 13:c7e8e277f884 15 volatile extern char dataLoadedFlag = 0;
Zbyszek 11:366f1186c121 16
Zbyszek 9:9ed9dffd602a 17
Zbyszek 9:9ed9dffd602a 18 void SPI_DMA_init() {
Zbyszek 11:366f1186c121 19
Zbyszek 9:9ed9dffd602a 20
Zbyszek 9:9ed9dffd602a 21 //Deinitialise
Zbyszek 9:9ed9dffd602a 22 SPI_DMA_SLAVE_deinit();
Zbyszek 9:9ed9dffd602a 23 deinitDMA();
Zbyszek 9:9ed9dffd602a 24
Zbyszek 9:9ed9dffd602a 25 //Initialise
Zbyszek 9:9ed9dffd602a 26 initDMA();
Zbyszek 9:9ed9dffd602a 27 SPI_DMA_SLAVE_init();
Zbyszek 9:9ed9dffd602a 28
Zbyszek 9:9ed9dffd602a 29 //Start DMA communication
Zbyszek 9:9ed9dffd602a 30 startCommunication();
Zbyszek 9:9ed9dffd602a 31 }
Zbyszek 9:9ed9dffd602a 32
Zbyszek 9:9ed9dffd602a 33 /* Starting DMA communication according to STM32L432 Reference Manual p1317-p1318*/
Zbyszek 9:9ed9dffd602a 34 void startCommunication() {
Zbyszek 9:9ed9dffd602a 35
Zbyszek 9:9ed9dffd602a 36 SET_SPI1_CR2_RXDMAEN_BIT(); //Enable RX DMA buffer
Zbyszek 9:9ed9dffd602a 37 DMA1_CH3_ENABLE(); //Enable DMA channel 3
Zbyszek 9:9ed9dffd602a 38 DMA1_CH2_ENABLE(); //Enable DMA channel 2
Zbyszek 9:9ed9dffd602a 39 SET_SPI1_CR2_TXDMAEN_BIT(); //Enable TX DMA buffer
Zbyszek 9:9ed9dffd602a 40 SPI1_ENABLE(); //SPI module enabled
Zbyszek 9:9ed9dffd602a 41 }
Zbyszek 9:9ed9dffd602a 42
Zbyszek 9:9ed9dffd602a 43
Zbyszek 9:9ed9dffd602a 44 //====================================================DEINITIALISE=========================================================================
Zbyszek 9:9ed9dffd602a 45 void SPI_DMA_SLAVE_deinit() {
Zbyszek 9:9ed9dffd602a 46 //Disable the clocks
Zbyszek 9:9ed9dffd602a 47 //RCC->AHB2ENR &= ~(RCC_AHB2ENR_GPIOAEN);
Zbyszek 9:9ed9dffd602a 48 //RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN);
Zbyszek 9:9ed9dffd602a 49 //Clear pin settings
Zbyszek 11:366f1186c121 50
Zbyszek 9:9ed9dffd602a 51
Zbyszek 9:9ed9dffd602a 52 GPIOA->MODER&=~( //clear GPIOB
Zbyszek 9:9ed9dffd602a 53 (3u<<(2*SCK_slave))
Zbyszek 9:9ed9dffd602a 54 |(3u<<(2*MISO_slave))
Zbyszek 9:9ed9dffd602a 55 |(3u<<(2*MOSI_slave))
Zbyszek 11:366f1186c121 56 |(3u<<(2*4))
Zbyszek 9:9ed9dffd602a 57 );
Zbyszek 11:366f1186c121 58
Zbyszek 11:366f1186c121 59
Zbyszek 11:366f1186c121 60 GPIOB->MODER &= ~(2u<<0);
Zbyszek 11:366f1186c121 61
Zbyszek 9:9ed9dffd602a 62 GPIOA->AFR[0]&=~( //clear alternate function selector bits
Zbyszek 9:9ed9dffd602a 63 (0x0f<<(4*SCK_slave))
Zbyszek 9:9ed9dffd602a 64 |(0x0f<<(4*MISO_slave))
Zbyszek 9:9ed9dffd602a 65 |(15u<<(4*MOSI_slave))
Zbyszek 11:366f1186c121 66 //|(15u<<(2*4)) //Thhis is why the UART was not working
Zbyszek 9:9ed9dffd602a 67 );
Zbyszek 11:366f1186c121 68
Zbyszek 11:366f1186c121 69 GPIOB->AFR[0] &= ~(15u<<(4*0));
Zbyszek 9:9ed9dffd602a 70
Zbyszek 9:9ed9dffd602a 71 //Clear SPI bits
Zbyszek 9:9ed9dffd602a 72 SPI1_DISABLE();
Zbyszek 9:9ed9dffd602a 73 CLEAR_SPI1_CR1_MSTR_BIT();
Zbyszek 9:9ed9dffd602a 74 CLEAR_SPI1_CR1_BR_BITS();
Zbyszek 9:9ed9dffd602a 75 CLEAR_SPI1_CR1_SSM_BIT();
Zbyszek 9:9ed9dffd602a 76 CLEAR_SPI1_CR1_SSI_BIT();
Zbyszek 9:9ed9dffd602a 77 CLEAR_SPI1_CR1_CPOL_BIT();
Zbyszek 9:9ed9dffd602a 78 CLEAR_SPI1_CR1_CPHA_BIT();
Zbyszek 9:9ed9dffd602a 79
Zbyszek 9:9ed9dffd602a 80
Zbyszek 9:9ed9dffd602a 81 CLEAR_SPI1_CR2_DS_BITS();
Zbyszek 9:9ed9dffd602a 82 CLEAR_SPI1_CR2_RXDMAEN_BIT();
Zbyszek 9:9ed9dffd602a 83 CLEAR_SPI1_CR2_TXDMAEN_BIT();
Zbyszek 9:9ed9dffd602a 84 CLEAR_SPI1_CR2_RXEIE_BIT();
Zbyszek 9:9ed9dffd602a 85 CLEAR_SPI1_CR2_TXEIE_BIT();
Zbyszek 9:9ed9dffd602a 86
Zbyszek 9:9ed9dffd602a 87 CLEAR_SPI1_CR1_CRC_BIT();
Zbyszek 9:9ed9dffd602a 88
Zbyszek 9:9ed9dffd602a 89 RCC->APB2RSTR |= RCC_APB2RSTR_SPI1RST;
Zbyszek 9:9ed9dffd602a 90 RCC->APB2RSTR &= ~RCC_APB2RSTR_SPI1RST;
Zbyszek 9:9ed9dffd602a 91 }
Zbyszek 9:9ed9dffd602a 92
Zbyszek 9:9ed9dffd602a 93 void deinitDMA() {
Zbyszek 9:9ed9dffd602a 94 //RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN); //Disable the DMA1 clock
Zbyszek 9:9ed9dffd602a 95 RCC->AHB1RSTR |= RCC_AHB1RSTR_DMA1RST;
Zbyszek 9:9ed9dffd602a 96 RCC->AHB1RSTR &= ~RCC_AHB1RSTR_DMA1RST;
Zbyszek 9:9ed9dffd602a 97
Zbyszek 9:9ed9dffd602a 98 //Disable channels
Zbyszek 9:9ed9dffd602a 99 DMA1_CH2_DISABLE();
Zbyszek 9:9ed9dffd602a 100 DMA1_CH3_DISABLE();
Zbyszek 9:9ed9dffd602a 101
Zbyszek 9:9ed9dffd602a 102 CLEAR_DMA1_SPI1RX_CSELR_BITS(); //deselect SPI1_Rx on DMA1 Channel 2
Zbyszek 9:9ed9dffd602a 103 CLEAR_DMA1_SPI1TX_CSELR_BITS(); //deselect SPI1_Tx on DMA1 Channel 3
Zbyszek 9:9ed9dffd602a 104
Zbyszek 9:9ed9dffd602a 105
Zbyszek 9:9ed9dffd602a 106 //-----------------------------------------------Receive-----------------------------------------------------
Zbyszek 9:9ed9dffd602a 107 //Clear configuration bits
Zbyszek 9:9ed9dffd602a 108 CLEAR_DMA1_CH2_CCR_DIR_BIT();
Zbyszek 9:9ed9dffd602a 109 CLEAR_DMA1_CH2_CCR_PSIZE_BITS();
Zbyszek 9:9ed9dffd602a 110 CLEAR_DMA1_CH2_CCR_MSIZE_BITS();
Zbyszek 9:9ed9dffd602a 111 CLEAR_DMA1_CH2_CCR_MINC_BIT();
Zbyszek 9:9ed9dffd602a 112 CLEAR_DMA1_CH2_CCR_PINC_BIT();
Zbyszek 9:9ed9dffd602a 113 CLEAR_DMA1_CH2_CCR_TCIE_BIT();
Zbyszek 9:9ed9dffd602a 114 CLEAR_DMA1_CH2_CCR_CIRC_BIT();
Zbyszek 9:9ed9dffd602a 115 CLEAR_DMA1_CH2_CCR_MEM2MEM_BIT();
Zbyszek 9:9ed9dffd602a 116 CLEAR_DMA1_CH2_CCR_PL_BITS();
Zbyszek 9:9ed9dffd602a 117 CLEAR_DMA1_CH2_CCR_TEIE_BIT();
Zbyszek 9:9ed9dffd602a 118
Zbyszek 9:9ed9dffd602a 119 CLEAR_DMA1_CH2_CNDTR_BITS();
Zbyszek 9:9ed9dffd602a 120 CLEAR_DMA1_CH2_CPAR_BITS();
Zbyszek 9:9ed9dffd602a 121 CLEAR_DMA1_CH2_CMAR_BITS();
Zbyszek 9:9ed9dffd602a 122 //-----------------------------------------------Receive-----------------------------------------------------
Zbyszek 9:9ed9dffd602a 123
Zbyszek 9:9ed9dffd602a 124 //-----------------------------------------------Transmission------------------------------------------------
Zbyszek 9:9ed9dffd602a 125 //Clear configuration bits
Zbyszek 9:9ed9dffd602a 126 CLEAR_DMA1_CH3_CCR_DIR_BIT();
Zbyszek 9:9ed9dffd602a 127 CLEAR_DMA1_CH3_CCR_PSIZE_BITS();
Zbyszek 9:9ed9dffd602a 128 CLEAR_DMA1_CH3_CCR_MSIZE_BITS();
Zbyszek 9:9ed9dffd602a 129 CLEAR_DMA1_CH3_CCR_MINC_BIT();
Zbyszek 9:9ed9dffd602a 130 CLEAR_DMA1_CH3_CCR_PINC_BIT();
Zbyszek 9:9ed9dffd602a 131 CLEAR_DMA1_CH3_CCR_TCIE_BIT();
Zbyszek 9:9ed9dffd602a 132 CLEAR_DMA1_CH3_CCR_CIRC_BIT();
Zbyszek 9:9ed9dffd602a 133 CLEAR_DMA1_CH3_CCR_MEM2MEM_BIT();
Zbyszek 9:9ed9dffd602a 134 CLEAR_DMA1_CH3_CCR_PL_BITS();
Zbyszek 9:9ed9dffd602a 135 CLEAR_DMA1_CH3_CCR_TEIE_BIT();
Zbyszek 9:9ed9dffd602a 136
Zbyszek 9:9ed9dffd602a 137 CLEAR_DMA1_CH3_CNDTR_BITS();
Zbyszek 9:9ed9dffd602a 138 CLEAR_DMA1_CH3_CPAR_BITS();
Zbyszek 9:9ed9dffd602a 139 CLEAR_DMA1_CH3_CMAR_BITS();
Zbyszek 9:9ed9dffd602a 140
Zbyszek 9:9ed9dffd602a 141 //-----------------------------------------------Transmission------------------------------------------------
Zbyszek 9:9ed9dffd602a 142
Zbyszek 9:9ed9dffd602a 143 NVIC->ISER[0]&= ~(1u<<12); //Disable DMA1 channel 2 interrupt
Zbyszek 9:9ed9dffd602a 144 NVIC->ISER[0]&= ~(1u<<13); //Disable DMA1 channel 3 interrupt
Zbyszek 9:9ed9dffd602a 145
Zbyszek 9:9ed9dffd602a 146 }
Zbyszek 9:9ed9dffd602a 147 //====================================================DEINITIALISE=========================================================================
Zbyszek 9:9ed9dffd602a 148
Zbyszek 9:9ed9dffd602a 149
Zbyszek 9:9ed9dffd602a 150
Zbyszek 9:9ed9dffd602a 151 void SPI_DMA_SLAVE_init() {
Zbyszek 11:366f1186c121 152 RCC->AHB2ENR|= (RCC_AHB2ENR_GPIOAEN); //GPIO A clock enable
Zbyszek 11:366f1186c121 153 RCC->AHB2ENR |= (RCC_AHB2ENR_GPIOBEN);
Zbyszek 9:9ed9dffd602a 154 RCC->APB2ENR|=RCC_APB2ENR_SPI1EN; //Enable SPI1 Clock
Zbyszek 9:9ed9dffd602a 155
Zbyszek 9:9ed9dffd602a 156 //SET SCK, MISO, MOSI and CS pins
Zbyszek 9:9ed9dffd602a 157 GPIOA->MODER|=(
Zbyszek 9:9ed9dffd602a 158 (2u<<(2*SCK_slave))
Zbyszek 9:9ed9dffd602a 159 |(2u<<(2*MISO_slave))
Zbyszek 9:9ed9dffd602a 160 |(2u<<(2*MOSI_slave))
Zbyszek 11:366f1186c121 161 //|(2u<<(2*4))
Zbyszek 9:9ed9dffd602a 162 );
Zbyszek 11:366f1186c121 163 //Set PB_0 to alternate function
Zbyszek 11:366f1186c121 164 GPIOB->MODER |= (2u<<0);
Zbyszek 9:9ed9dffd602a 165
Zbyszek 9:9ed9dffd602a 166 //SET pins to function as SPI pins
Zbyszek 9:9ed9dffd602a 167 GPIOA->AFR[0]|=(
Zbyszek 9:9ed9dffd602a 168 (5u<<(4*SCK_slave))
Zbyszek 9:9ed9dffd602a 169 |(5u<<(4*MISO_slave))
Zbyszek 9:9ed9dffd602a 170 |(5u<<(4*MOSI_slave))
Zbyszek 11:366f1186c121 171 //|(5u<<(4*4))
Zbyszek 9:9ed9dffd602a 172 );
Zbyszek 11:366f1186c121 173
Zbyszek 11:366f1186c121 174 //Select SPI1_SSEL alternate function
Zbyszek 11:366f1186c121 175 GPIOB->AFR[0] |= (5u<<(4*0));
Zbyszek 9:9ed9dffd602a 176
Zbyszek 9:9ed9dffd602a 177 SET_SPI1_CR1_BR_BITS(); //baud rate bits set 1/16 giving 1MHz SCK frequency
Zbyszek 9:9ed9dffd602a 178 SET_SPI1_CR1_CPOL_BIT(); //CPOL = 1
Zbyszek 9:9ed9dffd602a 179 SET_SPI1_CR1_CPHA_BIT(); //CPHA = 1
Zbyszek 9:9ed9dffd602a 180
Zbyszek 9:9ed9dffd602a 181
Zbyszek 9:9ed9dffd602a 182 SET_SPI1_CR2_DS_BITS(); //Data Size = 16 bits
Zbyszek 11:366f1186c121 183 // SET_SPI1_CR2_RXDMAEN_BIT(); //Rx buffer DMA enable
Zbyszek 11:366f1186c121 184 // SET_SPI1_CR2_TXDMAEN_BIT(); //Tx buffer DMA enable
Zbyszek 9:9ed9dffd602a 185
Zbyszek 9:9ed9dffd602a 186
Zbyszek 9:9ed9dffd602a 187 }
Zbyszek 9:9ed9dffd602a 188
Zbyszek 9:9ed9dffd602a 189
Zbyszek 8:e87027349167 190
Zbyszek 8:e87027349167 191 void initDMA() {
Zbyszek 9:9ed9dffd602a 192 RCC->AHB1ENR|= (RCC_AHB1ENR_DMA1EN); //Enable the DMA1 clock
Zbyszek 9:9ed9dffd602a 193
Zbyszek 9:9ed9dffd602a 194 DMA1_CH2_DISABLE(); //Disable DMA channel 2
Zbyszek 9:9ed9dffd602a 195 DMA1_CH3_DISABLE(); //Disable DMA channel 3
Zbyszek 8:e87027349167 196
Zbyszek 9:9ed9dffd602a 197 SET_DMA1_SPI1RX_CSELR_BITS(); //Select SPI1_Rx on DMA1 Channel 2
Zbyszek 9:9ed9dffd602a 198 SET_DMA1_SPI1TX_CSELR_BITS(); //Select SPI1_Tx on DMA1 Channel 3
Zbyszek 8:e87027349167 199
Zbyszek 9:9ed9dffd602a 200 //-----------------------------------------------Receive-----------------------------------------------------
Zbyszek 9:9ed9dffd602a 201 CLEAR_DMA1_CH2_CCR_DIR_BIT(); //Peripheral->Memory
Zbyszek 9:9ed9dffd602a 202 SET_DMA1_CH2_CCR_PSIZE_BITS(); //16 bits
Zbyszek 9:9ed9dffd602a 203 SET_DMA1_CH2_CCR_MSIZE_BITS(); //16 bits
Zbyszek 11:366f1186c121 204 SET_DMA1_CH2_CCR_MINC_BIT(); //Memory increment mode
Zbyszek 9:9ed9dffd602a 205 //SET_DMA1_CH2_CCR_PINC_BIT(); //Peripheral increment mode
Zbyszek 9:9ed9dffd602a 206 SET_DMA1_CH2_CCR_TCIE_BIT(); //Transfer complete interrupt enable
Zbyszek 11:366f1186c121 207 SET_DMA1_CH2_CCR_CIRC_BIT(); //Circular Buffer mode
Zbyszek 9:9ed9dffd602a 208 SET_DMA1_CH2_CCR_PL_BITS(); //Priority Level = Highest
Zbyszek 8:e87027349167 209
Zbyszek 9:9ed9dffd602a 210 DMA1_Channel2->CNDTR = 12; //number of data to transfer from the peripheral to memory.
Zbyszek 9:9ed9dffd602a 211 DMA1_Channel2->CPAR = (int32_t)&SPI1->DR; //Source Adddress = SPI data register
Zbyszek 11:366f1186c121 212 DMA1_Channel2->CMAR = (int32_t)&received_data[0]; //Destination address = received_data array
Zbyszek 9:9ed9dffd602a 213 //-----------------------------------------------Receive-----------------------------------------------------
Zbyszek 9:9ed9dffd602a 214
Zbyszek 9:9ed9dffd602a 215 //-----------------------------------------------Transmission------------------------------------------------
Zbyszek 9:9ed9dffd602a 216
Zbyszek 9:9ed9dffd602a 217 SET_DMA1_CH3_CCR_DIR_BIT(); //Memory->Peripheral
Zbyszek 9:9ed9dffd602a 218 SET_DMA1_CH3_CCR_PSIZE_BITS(); //16 bits
Zbyszek 9:9ed9dffd602a 219 SET_DMA1_CH3_CCR_MSIZE_BITS(); //16 bits
Zbyszek 9:9ed9dffd602a 220 SET_DMA1_CH3_CCR_MINC_BIT(); //Memory increment mode
Zbyszek 9:9ed9dffd602a 221 // SET_DMA1_CH3_CCR_PINC_BIT(); //Peripheral increment mode
Zbyszek 9:9ed9dffd602a 222 SET_DMA1_CH3_CCR_TCIE_BIT(); //Transfer complete interrupt enable
Zbyszek 9:9ed9dffd602a 223 SET_DMA1_CH3_CCR_CIRC_BIT(); //Circular Buffer mode
Zbyszek 9:9ed9dffd602a 224 SET_DMA1_CH3_CCR_PL_BITS(); //Priority Level = Highest
Zbyszek 9:9ed9dffd602a 225
Zbyszek 9:9ed9dffd602a 226 DMA1_Channel3->CNDTR = 12; //number of data to transfer from memory to the peripheral
Zbyszek 11:366f1186c121 227 DMA1_Channel3->CPAR = (int32_t)&SPI1->DR; //Destination address = SPI data register
Zbyszek 11:366f1186c121 228 DMA1_Channel3->CMAR = (int32_t)&data_to_transmit[0]; //Source address = data_to_transmit
Zbyszek 9:9ed9dffd602a 229 //-----------------------------------------------Transmission------------------------------------------------
Zbyszek 8:e87027349167 230
Zbyszek 8:e87027349167 231
Zbyszek 11:366f1186c121 232 NVIC->ISER[0] |= (1u<<12); //Enable DMA1 channel 2 interrupt
Zbyszek 10:5b96211275d4 233 NVIC->ISER[0] |= (1u<<13); //Enable DMA1 channel 3 interrupt
Zbyszek 11:366f1186c121 234 NVIC_EnableIRQ(DMA1_Channel2_IRQn);
Zbyszek 10:5b96211275d4 235 NVIC_EnableIRQ(DMA1_Channel3_IRQn);
Zbyszek 8:e87027349167 236
Zbyszek 8:e87027349167 237 }
Zbyszek 9:9ed9dffd602a 238
Zbyszek 9:9ed9dffd602a 239
Zbyszek 9:9ed9dffd602a 240 //Interrupt Handler for DMA1 Channel 2
Zbyszek 10:5b96211275d4 241 extern "C" void DMA1_Channel2_IRQHandler(void) {
Zbyszek 11:366f1186c121 242 uint16_t n;
Zbyszek 11:366f1186c121 243
Zbyszek 9:9ed9dffd602a 244 CLEAR_DMA1_CH2_IFCR_GFLAG(); //Clear Global Interrupt flag
Zbyszek 11:366f1186c121 245 for(int x = 0; x <= 11; x++) {
Zbyszek 11:366f1186c121 246
Zbyszek 11:366f1186c121 247 n = received_data[x];
Zbyszek 11:366f1186c121 248 n &= ~(8191); //remove first 13 bits
Zbyszek 11:366f1186c121 249 n = n >> 13; //shift by right by 13
Zbyszek 11:366f1186c121 250 SampleFIFO[pointerFS][x] = received_data[x];
Zbyszek 11:366f1186c121 251 // printf("%d \n\r", n);
Zbyszek 11:366f1186c121 252 }
Zbyszek 11:366f1186c121 253 newDataFlag = 1;
Zbyszek 9:9ed9dffd602a 254 }
Zbyszek 9:9ed9dffd602a 255
Zbyszek 9:9ed9dffd602a 256
Zbyszek 9:9ed9dffd602a 257 //Interrupt Handler for DMA1 Channel 3
Zbyszek 11:366f1186c121 258 extern "C" void DMA1_Channel3_IRQHandler(void) {
Zbyszek 10:5b96211275d4 259 if(DMA1->ISR&(1u<<9)) { //Check whteher data transmit transfer is complete
Zbyszek 10:5b96211275d4 260 //Read data from the array that stores received data
Zbyszek 13:c7e8e277f884 261 if(dataRequestFlag == 1 && dataLoadedFlag == 1) {
Zbyszek 13:c7e8e277f884 262 for(int x = 0; x <= 11; x++) {
Zbyszek 13:c7e8e277f884 263 if(x < 7) { //Data is only loaded in first 7 places
Zbyszek 13:c7e8e277f884 264 if(x == 0) { //IMU ID is loaded in array position 0
Zbyszek 13:c7e8e277f884 265 data_to_transmit[x] = IMU_Data_Array[x]; //Load the IMU data for transmission
Zbyszek 14:7bbaafa22f8d 266 //data_to_transmit[x] = 1; //Test Input
Zbyszek 13:c7e8e277f884 267 }
Zbyszek 13:c7e8e277f884 268 else { //Rest is loaded in the following order: x, y, z
Zbyszek 13:c7e8e277f884 269 data_to_transmit[x] = IMU_Data_Array[x]; //Load the IMU data for transmission
Zbyszek 14:7bbaafa22f8d 270 //data_to_transmit[x] = 770 + ((x - 1) * 514); //Test Input
Zbyszek 13:c7e8e277f884 271 }
Zbyszek 13:c7e8e277f884 272 }
Zbyszek 13:c7e8e277f884 273 else { //After 7 positions have been filled, the rest is filled with zeros
Zbyszek 13:c7e8e277f884 274 data_to_transmit[x] = 0; //Above 6 there is nothing more to send so send zeros.
Zbyszek 13:c7e8e277f884 275 }
Zbyszek 13:c7e8e277f884 276 }
Zbyszek 13:c7e8e277f884 277 dataRequestFlag = 0; //Data request has been fulfilled and therefore clear the flag
Zbyszek 10:5b96211275d4 278 }
Zbyszek 13:c7e8e277f884 279 else { //if the two flags arent 1 then load this transmission with zeros
Zbyszek 13:c7e8e277f884 280 for(int x = 0; x <= 11; x++) {
Zbyszek 13:c7e8e277f884 281 data_to_transmit[x] = 0;
Zbyszek 13:c7e8e277f884 282 }
Zbyszek 13:c7e8e277f884 283 }
Zbyszek 10:5b96211275d4 284 CLEAR_DMA1_CH3_IFCR_GFLAG(); //Clear global channel interrupt flag for channel 3
Zbyszek 13:c7e8e277f884 285 } //Clear Global Interrupt flag
Zbyszek 9:9ed9dffd602a 286 }
Zbyszek 9:9ed9dffd602a 287