Zbigniew Druzbacki / Mbed 2 deprecated SPI_Slave

SPI slave program to enable communication between the FPGA and the STM32L432 board.

Dependencies:   mbed

DMA_SPI.cpp@15:791f35b0f220, 2019-05-15 (annotated)

Committer:
Zbyszek
Date:
Wed May 15 22:56:20 2019 +0000
Revision:
15:791f35b0f220
Parent:
14:7bbaafa22f8d 
Official Code used on the 15/05/2019

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Zbyszek 8:e87027349167 1 #include "mbed.h"
Zbyszek 8:e87027349167 2 #include "DMA_SPI.h"
Zbyszek 8:e87027349167 3
Zbyszek 9:9ed9dffd602a 4 int16_t data_to_transmit[12];
Zbyszek 9:9ed9dffd602a 5 int16_t received_data[12];
Zbyszek 13:c7e8e277f884 6 int16_t IMU_Data_Array[12];
Zbyszek 11:366f1186c121 7
Zbyszek 11:366f1186c121 8
Zbyszek 11:366f1186c121 9 int16_t SampleFIFO[10][12];
Zbyszek 11:366f1186c121 10 extern int pointerOS = 0;
Zbyszek 11:366f1186c121 11 extern int pointerNS = 0;
Zbyszek 11:366f1186c121 12 extern int pointerFS = 0;
Zbyszek 11:366f1186c121 13 extern char newDataFlag = 0;
Zbyszek 13:c7e8e277f884 14 volatile extern char dataRequestFlag = 0;
Zbyszek 13:c7e8e277f884 15 volatile extern char dataLoadedFlag = 0;
Zbyszek 11:366f1186c121 16
Zbyszek 9:9ed9dffd602a 17
Zbyszek 9:9ed9dffd602a 18 void SPI_DMA_init() {
Zbyszek 11:366f1186c121 19
Zbyszek 9:9ed9dffd602a 20
Zbyszek 9:9ed9dffd602a 21 //Deinitialise
Zbyszek 9:9ed9dffd602a 22 SPI_DMA_SLAVE_deinit();
Zbyszek 9:9ed9dffd602a 23 deinitDMA();
Zbyszek 9:9ed9dffd602a 24
Zbyszek 9:9ed9dffd602a 25 //Initialise
Zbyszek 9:9ed9dffd602a 26 initDMA();
Zbyszek 9:9ed9dffd602a 27 SPI_DMA_SLAVE_init();
Zbyszek 9:9ed9dffd602a 28
Zbyszek 9:9ed9dffd602a 29 //Start DMA communication
Zbyszek 9:9ed9dffd602a 30 startCommunication();
Zbyszek 9:9ed9dffd602a 31 }
Zbyszek 9:9ed9dffd602a 32
Zbyszek 15:791f35b0f220 33 //-----------------------------------------------Step-5-----------------------------------------------------------------------------------------------------------
Zbyszek 9:9ed9dffd602a 34 /* Starting DMA communication according to STM32L432 Reference Manual p1317-p1318*/
Zbyszek 9:9ed9dffd602a 35 void startCommunication() {
Zbyszek 9:9ed9dffd602a 36
Zbyszek 9:9ed9dffd602a 37 SET_SPI1_CR2_RXDMAEN_BIT(); //Enable RX DMA buffer
Zbyszek 9:9ed9dffd602a 38 DMA1_CH3_ENABLE(); //Enable DMA channel 3
Zbyszek 9:9ed9dffd602a 39 DMA1_CH2_ENABLE(); //Enable DMA channel 2
Zbyszek 9:9ed9dffd602a 40 SET_SPI1_CR2_TXDMAEN_BIT(); //Enable TX DMA buffer
Zbyszek 9:9ed9dffd602a 41 SPI1_ENABLE(); //SPI module enabled
Zbyszek 9:9ed9dffd602a 42 }
Zbyszek 9:9ed9dffd602a 43
Zbyszek 9:9ed9dffd602a 44
Zbyszek 9:9ed9dffd602a 45 //====================================================DEINITIALISE=========================================================================
Zbyszek 9:9ed9dffd602a 46 void SPI_DMA_SLAVE_deinit() {
Zbyszek 9:9ed9dffd602a 47 //Disable the clocks
Zbyszek 9:9ed9dffd602a 48 //RCC->AHB2ENR &= ~(RCC_AHB2ENR_GPIOAEN);
Zbyszek 9:9ed9dffd602a 49 //RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN);
Zbyszek 9:9ed9dffd602a 50 //Clear pin settings
Zbyszek 11:366f1186c121 51
Zbyszek 9:9ed9dffd602a 52
Zbyszek 9:9ed9dffd602a 53 GPIOA->MODER&=~( //clear GPIOB
Zbyszek 9:9ed9dffd602a 54 (3u<<(2*SCK_slave))
Zbyszek 9:9ed9dffd602a 55 |(3u<<(2*MISO_slave))
Zbyszek 9:9ed9dffd602a 56 |(3u<<(2*MOSI_slave))
Zbyszek 11:366f1186c121 57 |(3u<<(2*4))
Zbyszek 9:9ed9dffd602a 58 );
Zbyszek 11:366f1186c121 59
Zbyszek 11:366f1186c121 60
Zbyszek 11:366f1186c121 61 GPIOB->MODER &= ~(2u<<0);
Zbyszek 11:366f1186c121 62
Zbyszek 9:9ed9dffd602a 63 GPIOA->AFR[0]&=~( //clear alternate function selector bits
Zbyszek 9:9ed9dffd602a 64 (0x0f<<(4*SCK_slave))
Zbyszek 9:9ed9dffd602a 65 |(0x0f<<(4*MISO_slave))
Zbyszek 9:9ed9dffd602a 66 |(15u<<(4*MOSI_slave))
Zbyszek 11:366f1186c121 67 //|(15u<<(2*4)) //Thhis is why the UART was not working
Zbyszek 9:9ed9dffd602a 68 );
Zbyszek 11:366f1186c121 69
Zbyszek 11:366f1186c121 70 GPIOB->AFR[0] &= ~(15u<<(4*0));
Zbyszek 9:9ed9dffd602a 71
Zbyszek 9:9ed9dffd602a 72 //Clear SPI bits
Zbyszek 9:9ed9dffd602a 73 SPI1_DISABLE();
Zbyszek 9:9ed9dffd602a 74 CLEAR_SPI1_CR1_MSTR_BIT();
Zbyszek 9:9ed9dffd602a 75 CLEAR_SPI1_CR1_BR_BITS();
Zbyszek 9:9ed9dffd602a 76 CLEAR_SPI1_CR1_SSM_BIT();
Zbyszek 9:9ed9dffd602a 77 CLEAR_SPI1_CR1_SSI_BIT();
Zbyszek 9:9ed9dffd602a 78 CLEAR_SPI1_CR1_CPOL_BIT();
Zbyszek 9:9ed9dffd602a 79 CLEAR_SPI1_CR1_CPHA_BIT();
Zbyszek 9:9ed9dffd602a 80
Zbyszek 9:9ed9dffd602a 81
Zbyszek 9:9ed9dffd602a 82 CLEAR_SPI1_CR2_DS_BITS();
Zbyszek 9:9ed9dffd602a 83 CLEAR_SPI1_CR2_RXDMAEN_BIT();
Zbyszek 9:9ed9dffd602a 84 CLEAR_SPI1_CR2_TXDMAEN_BIT();
Zbyszek 9:9ed9dffd602a 85 CLEAR_SPI1_CR2_RXEIE_BIT();
Zbyszek 9:9ed9dffd602a 86 CLEAR_SPI1_CR2_TXEIE_BIT();
Zbyszek 9:9ed9dffd602a 87
Zbyszek 9:9ed9dffd602a 88 CLEAR_SPI1_CR1_CRC_BIT();
Zbyszek 9:9ed9dffd602a 89
Zbyszek 9:9ed9dffd602a 90 RCC->APB2RSTR |= RCC_APB2RSTR_SPI1RST;
Zbyszek 9:9ed9dffd602a 91 RCC->APB2RSTR &= ~RCC_APB2RSTR_SPI1RST;
Zbyszek 9:9ed9dffd602a 92 }
Zbyszek 9:9ed9dffd602a 93
Zbyszek 9:9ed9dffd602a 94 void deinitDMA() {
Zbyszek 9:9ed9dffd602a 95 //RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN); //Disable the DMA1 clock
Zbyszek 9:9ed9dffd602a 96 RCC->AHB1RSTR |= RCC_AHB1RSTR_DMA1RST;
Zbyszek 9:9ed9dffd602a 97 RCC->AHB1RSTR &= ~RCC_AHB1RSTR_DMA1RST;
Zbyszek 9:9ed9dffd602a 98
Zbyszek 9:9ed9dffd602a 99 //Disable channels
Zbyszek 9:9ed9dffd602a 100 DMA1_CH2_DISABLE();
Zbyszek 9:9ed9dffd602a 101 DMA1_CH3_DISABLE();
Zbyszek 9:9ed9dffd602a 102
Zbyszek 9:9ed9dffd602a 103 CLEAR_DMA1_SPI1RX_CSELR_BITS(); //deselect SPI1_Rx on DMA1 Channel 2
Zbyszek 9:9ed9dffd602a 104 CLEAR_DMA1_SPI1TX_CSELR_BITS(); //deselect SPI1_Tx on DMA1 Channel 3
Zbyszek 9:9ed9dffd602a 105
Zbyszek 9:9ed9dffd602a 106
Zbyszek 9:9ed9dffd602a 107 //-----------------------------------------------Receive-----------------------------------------------------
Zbyszek 9:9ed9dffd602a 108 //Clear configuration bits
Zbyszek 9:9ed9dffd602a 109 CLEAR_DMA1_CH2_CCR_DIR_BIT();
Zbyszek 9:9ed9dffd602a 110 CLEAR_DMA1_CH2_CCR_PSIZE_BITS();
Zbyszek 9:9ed9dffd602a 111 CLEAR_DMA1_CH2_CCR_MSIZE_BITS();
Zbyszek 9:9ed9dffd602a 112 CLEAR_DMA1_CH2_CCR_MINC_BIT();
Zbyszek 9:9ed9dffd602a 113 CLEAR_DMA1_CH2_CCR_PINC_BIT();
Zbyszek 9:9ed9dffd602a 114 CLEAR_DMA1_CH2_CCR_TCIE_BIT();
Zbyszek 9:9ed9dffd602a 115 CLEAR_DMA1_CH2_CCR_CIRC_BIT();
Zbyszek 9:9ed9dffd602a 116 CLEAR_DMA1_CH2_CCR_MEM2MEM_BIT();
Zbyszek 9:9ed9dffd602a 117 CLEAR_DMA1_CH2_CCR_PL_BITS();
Zbyszek 9:9ed9dffd602a 118 CLEAR_DMA1_CH2_CCR_TEIE_BIT();
Zbyszek 9:9ed9dffd602a 119
Zbyszek 9:9ed9dffd602a 120 CLEAR_DMA1_CH2_CNDTR_BITS();
Zbyszek 9:9ed9dffd602a 121 CLEAR_DMA1_CH2_CPAR_BITS();
Zbyszek 9:9ed9dffd602a 122 CLEAR_DMA1_CH2_CMAR_BITS();
Zbyszek 9:9ed9dffd602a 123 //-----------------------------------------------Receive-----------------------------------------------------
Zbyszek 9:9ed9dffd602a 124
Zbyszek 9:9ed9dffd602a 125 //-----------------------------------------------Transmission------------------------------------------------
Zbyszek 9:9ed9dffd602a 126 //Clear configuration bits
Zbyszek 9:9ed9dffd602a 127 CLEAR_DMA1_CH3_CCR_DIR_BIT();
Zbyszek 9:9ed9dffd602a 128 CLEAR_DMA1_CH3_CCR_PSIZE_BITS();
Zbyszek 9:9ed9dffd602a 129 CLEAR_DMA1_CH3_CCR_MSIZE_BITS();
Zbyszek 9:9ed9dffd602a 130 CLEAR_DMA1_CH3_CCR_MINC_BIT();
Zbyszek 9:9ed9dffd602a 131 CLEAR_DMA1_CH3_CCR_PINC_BIT();
Zbyszek 9:9ed9dffd602a 132 CLEAR_DMA1_CH3_CCR_TCIE_BIT();
Zbyszek 9:9ed9dffd602a 133 CLEAR_DMA1_CH3_CCR_CIRC_BIT();
Zbyszek 9:9ed9dffd602a 134 CLEAR_DMA1_CH3_CCR_MEM2MEM_BIT();
Zbyszek 9:9ed9dffd602a 135 CLEAR_DMA1_CH3_CCR_PL_BITS();
Zbyszek 9:9ed9dffd602a 136 CLEAR_DMA1_CH3_CCR_TEIE_BIT();
Zbyszek 9:9ed9dffd602a 137
Zbyszek 9:9ed9dffd602a 138 CLEAR_DMA1_CH3_CNDTR_BITS();
Zbyszek 9:9ed9dffd602a 139 CLEAR_DMA1_CH3_CPAR_BITS();
Zbyszek 9:9ed9dffd602a 140 CLEAR_DMA1_CH3_CMAR_BITS();
Zbyszek 9:9ed9dffd602a 141
Zbyszek 9:9ed9dffd602a 142 //-----------------------------------------------Transmission------------------------------------------------
Zbyszek 9:9ed9dffd602a 143
Zbyszek 9:9ed9dffd602a 144 NVIC->ISER[0]&= ~(1u<<12); //Disable DMA1 channel 2 interrupt
Zbyszek 9:9ed9dffd602a 145 NVIC->ISER[0]&= ~(1u<<13); //Disable DMA1 channel 3 interrupt
Zbyszek 9:9ed9dffd602a 146
Zbyszek 9:9ed9dffd602a 147 }
Zbyszek 9:9ed9dffd602a 148 //====================================================DEINITIALISE=========================================================================
Zbyszek 9:9ed9dffd602a 149
Zbyszek 9:9ed9dffd602a 150
Zbyszek 9:9ed9dffd602a 151
Zbyszek 9:9ed9dffd602a 152 void SPI_DMA_SLAVE_init() {
Zbyszek 15:791f35b0f220 153 //-----------------------------------------------Step-1-----------------------------------------------------------------------------------------------------------
Zbyszek 15:791f35b0f220 154 RCC->AHB2ENR|= (RCC_AHB2ENR_GPIOAEN); //GPIO A clock enable by setting the GPIOAEN bit in the RCC_AHB2ENR register
Zbyszek 15:791f35b0f220 155 RCC->AHB2ENR |= (RCC_AHB2ENR_GPIOBEN); //GPIO B clock enable by setting the GPIOBEN bit in the RCC_AHB2ENR register
Zbyszek 15:791f35b0f220 156 RCC->APB2ENR|=RCC_APB2ENR_SPI1EN; //Enable SPI1 Clock by setting the SPI1EN bit in the RCC_APB2ENR register
Zbyszek 9:9ed9dffd602a 157
Zbyszek 15:791f35b0f220 158 //-----------------------------------------------Step-2-----------------------------------------------------------------------------------------------------------
Zbyszek 15:791f35b0f220 159 //SET SCK, MISO, MOSI and CS pins
Zbyszek 9:9ed9dffd602a 160 GPIOA->MODER|=(
Zbyszek 15:791f35b0f220 161 (2u<<(2*SCK_slave)) //Set pin 1 in the MODER register of port A as alternate function
Zbyszek 15:791f35b0f220 162 |(2u<<(2*MISO_slave)) //Set pin 6 in the MODER register of port A as alternate function
Zbyszek 15:791f35b0f220 163 |(2u<<(2*MOSI_slave)) //Set pin 7 in the MODER register of port A as alternate function
Zbyszek 11:366f1186c121 164 //|(2u<<(2*4))
Zbyszek 9:9ed9dffd602a 165 );
Zbyszek 11:366f1186c121 166 //Set PB_0 to alternate function
Zbyszek 15:791f35b0f220 167 GPIOB->MODER |= (2u<<0); //Set pin 0 in the MODER register of port B as alternate function
Zbyszek 15:791f35b0f220 168
Zbyszek 15:791f35b0f220 169 //-----------------------------------------------Step-3-----------------------------------------------------------------------------------------------------------
Zbyszek 9:9ed9dffd602a 170 //SET pins to function as SPI pins
Zbyszek 15:791f35b0f220 171 GPIOA->AFR[0]|=(
Zbyszek 15:791f35b0f220 172 (5u<<(4*SCK_slave)) //Set the alternate function of pin 1 as SPI clock pin by writing 1001 to the lower part of the AFR register of port A.
Zbyszek 15:791f35b0f220 173 |(5u<<(4*MISO_slave)) //Set the alternate function of pin 6 as SPI MISO pin by writing 1001 to the lower part of the AFR register of port A.
Zbyszek 15:791f35b0f220 174 |(5u<<(4*MOSI_slave)) //Set the alternate function of pin 7 as SPI clock pin by writing 1001 to the lower part of the AFR register of port A.
Zbyszek 11:366f1186c121 175 //|(5u<<(4*4))
Zbyszek 9:9ed9dffd602a 176 );
Zbyszek 11:366f1186c121 177
Zbyszek 11:366f1186c121 178 //Select SPI1_SSEL alternate function
Zbyszek 15:791f35b0f220 179 GPIOB->AFR[0] |= (5u<<(4*0)); //Set the alternate function of pin 0 as SPI slave select pin by writing 1001 to the lower part of the AFR register of port B.
Zbyszek 15:791f35b0f220 180
Zbyszek 15:791f35b0f220 181 //-----------------------------------------------Step-4-----------------------------------------------------------------------------------------------------------
Zbyszek 9:9ed9dffd602a 182 SET_SPI1_CR1_BR_BITS(); //baud rate bits set 1/16 giving 1MHz SCK frequency
Zbyszek 15:791f35b0f220 183 //-----------------------------------------------Step-5-----------------------------------------------------------------------------------------------------------
Zbyszek 9:9ed9dffd602a 184 SET_SPI1_CR1_CPOL_BIT(); //CPOL = 1
Zbyszek 9:9ed9dffd602a 185 SET_SPI1_CR1_CPHA_BIT(); //CPHA = 1
Zbyszek 9:9ed9dffd602a 186
Zbyszek 15:791f35b0f220 187 //-----------------------------------------------Step-6-----------------------------------------------------------------------------------------------------------
Zbyszek 9:9ed9dffd602a 188 SET_SPI1_CR2_DS_BITS(); //Data Size = 16 bits
Zbyszek 11:366f1186c121 189 // SET_SPI1_CR2_RXDMAEN_BIT(); //Rx buffer DMA enable
Zbyszek 15:791f35b0f220 190 // SET_SPI1_CR2_TXDMAEN_BIT(); //Tx buffer DMA enable
Zbyszek 9:9ed9dffd602a 191 }
Zbyszek 9:9ed9dffd602a 192
Zbyszek 15:791f35b0f220 193 //SET_DMA1_CH2_CCR_PINC_BIT(); //Peripheral increment mode
Zbyszek 15:791f35b0f220 194 // SET_DMA1_CH3_CCR_PINC_BIT(); //Peripheral increment mode
Zbyszek 15:791f35b0f220 195
Zbyszek 8:e87027349167 196 void initDMA() {
Zbyszek 15:791f35b0f220 197 //-----------------------------------------------Step-1-----------------------------------------------------------------------------------------------------------
Zbyszek 9:9ed9dffd602a 198 RCC->AHB1ENR|= (RCC_AHB1ENR_DMA1EN); //Enable the DMA1 clock
Zbyszek 9:9ed9dffd602a 199
Zbyszek 15:791f35b0f220 200 //-----------------------------------------------Step-2-----------------------------------------------------------------------------------------------------------
Zbyszek 9:9ed9dffd602a 201 DMA1_CH2_DISABLE(); //Disable DMA channel 2
Zbyszek 9:9ed9dffd602a 202 DMA1_CH3_DISABLE(); //Disable DMA channel 3
Zbyszek 8:e87027349167 203
Zbyszek 9:9ed9dffd602a 204 SET_DMA1_SPI1RX_CSELR_BITS(); //Select SPI1_Rx on DMA1 Channel 2
Zbyszek 9:9ed9dffd602a 205 SET_DMA1_SPI1TX_CSELR_BITS(); //Select SPI1_Tx on DMA1 Channel 3
Zbyszek 15:791f35b0f220 206
Zbyszek 15:791f35b0f220 207 //-----------------------------------------------Step-3-----------------------------------------------------------------------------------------------------------
Zbyszek 9:9ed9dffd602a 208 //-----------------------------------------------Receive-----------------------------------------------------
Zbyszek 15:791f35b0f220 209 CLEAR_DMA1_CH2_CCR_DIR_BIT(); //Direction bit: 0 = Peripheral->Memory. Data will be loaded from SPI data register to the specified variable
Zbyszek 15:791f35b0f220 210 SET_DMA1_CH2_CCR_PSIZE_BITS(); //peripheral size bit: 1 = 16 bits. The size is set to 16 bits as thats the data size SPI will work in.
Zbyszek 15:791f35b0f220 211 SET_DMA1_CH2_CCR_MSIZE_BITS(); //Memory size bit: 1 = 16 bits. The size is set to 16 bits as data coming from SPI is 16 bits wide
Zbyszek 15:791f35b0f220 212 SET_DMA1_CH2_CCR_MINC_BIT(); //Memory increment mode but: 1 = Increment memory after each transaction. Used when multiple transaction are done before interrupt occurs
Zbyszek 15:791f35b0f220 213 SET_DMA1_CH2_CCR_TCIE_BIT(); //Transfer complete interrupt enable: 1 = enabled. Allows DMA to interrupt software when number of transaction has occured.
Zbyszek 15:791f35b0f220 214 SET_DMA1_CH2_CCR_CIRC_BIT(); //Circular Buffer mode: 1 = enabled. After n transaction, the address is reset to starting memory address automatically.
Zbyszek 9:9ed9dffd602a 215 SET_DMA1_CH2_CCR_PL_BITS(); //Priority Level = Highest
Zbyszek 8:e87027349167 216
Zbyszek 15:791f35b0f220 217 DMA1_Channel2->CNDTR = 12; //number of data to transfer from the peripheral to memory before interrupt occurs.
Zbyszek 9:9ed9dffd602a 218 DMA1_Channel2->CPAR = (int32_t)&SPI1->DR; //Source Adddress = SPI data register
Zbyszek 15:791f35b0f220 219 DMA1_Channel2->CMAR = (int32_t)&received_data[0]; //Destination address = received_data array.
Zbyszek 9:9ed9dffd602a 220 //-----------------------------------------------Receive-----------------------------------------------------
Zbyszek 9:9ed9dffd602a 221
Zbyszek 15:791f35b0f220 222
Zbyszek 15:791f35b0f220 223
Zbyszek 9:9ed9dffd602a 224 //-----------------------------------------------Transmission------------------------------------------------
Zbyszek 9:9ed9dffd602a 225
Zbyszek 15:791f35b0f220 226 SET_DMA1_CH3_CCR_DIR_BIT(); //Direction bit: 1 = Memory->Peripheral. Data will be sent from variable to SPI data register for transmission
Zbyszek 15:791f35b0f220 227 SET_DMA1_CH3_CCR_PSIZE_BITS(); //peripheral size bit: 1 = 16 bits. The size is set to 16 bits as thats the data size SPI will work in.
Zbyszek 15:791f35b0f220 228 SET_DMA1_CH3_CCR_MSIZE_BITS(); //Memory size bit: 1 = 16 bits. The size is set to 16 bits as data coming from SPI is 16 bits wide
Zbyszek 9:9ed9dffd602a 229 SET_DMA1_CH3_CCR_MINC_BIT(); //Memory increment mode
Zbyszek 9:9ed9dffd602a 230 SET_DMA1_CH3_CCR_TCIE_BIT(); //Transfer complete interrupt enable
Zbyszek 9:9ed9dffd602a 231 SET_DMA1_CH3_CCR_CIRC_BIT(); //Circular Buffer mode
Zbyszek 9:9ed9dffd602a 232 SET_DMA1_CH3_CCR_PL_BITS(); //Priority Level = Highest
Zbyszek 9:9ed9dffd602a 233
Zbyszek 15:791f35b0f220 234 DMA1_Channel3->CNDTR = 12; //number of data to transfer from memory to the peripheral to be transmitted.
Zbyszek 11:366f1186c121 235 DMA1_Channel3->CPAR = (int32_t)&SPI1->DR; //Destination address = SPI data register
Zbyszek 15:791f35b0f220 236 DMA1_Channel3->CMAR = (int32_t)&data_to_transmit[0]; //Source address = data_to_transmit: Address from which data will be loaded to the SPI data register for transmission
Zbyszek 9:9ed9dffd602a 237 //-----------------------------------------------Transmission------------------------------------------------
Zbyszek 15:791f35b0f220 238 //-----------------------------------------------Step-4-----------------------------------------------------------------------------------------------------------
Zbyszek 15:791f35b0f220 239 //Enable DMA1 channel 2 and 3 interrupts
Zbyszek 15:791f35b0f220 240 NVIC->ISER[0] |= (1u<<12);
Zbyszek 15:791f35b0f220 241 NVIC->ISER[0] |= (1u<<13);
Zbyszek 11:366f1186c121 242 NVIC_EnableIRQ(DMA1_Channel2_IRQn);
Zbyszek 15:791f35b0f220 243 NVIC_EnableIRQ(DMA1_Channel3_IRQn);
Zbyszek 8:e87027349167 244 }
Zbyszek 9:9ed9dffd602a 245
Zbyszek 9:9ed9dffd602a 246
Zbyszek 9:9ed9dffd602a 247 //Interrupt Handler for DMA1 Channel 2
Zbyszek 10:5b96211275d4 248 extern "C" void DMA1_Channel2_IRQHandler(void) {
Zbyszek 11:366f1186c121 249 uint16_t n;
Zbyszek 11:366f1186c121 250
Zbyszek 15:791f35b0f220 251 CLEAR_DMA1_CH2_IFCR_GFLAG(); //Clear Global Interrupt flag so that the nterrupt can occur again once a new batch of data is received.
Zbyszek 15:791f35b0f220 252 for(int x = 0; x <= 11; x++) { //run the for loop to read new data from the array that the SPI uses to save the received data to a new array to avoid overwritting
Zbyszek 15:791f35b0f220 253 SampleFIFO[pointerFS][x] = received_data[x]; //Just move the data from one array to the other.
Zbyszek 11:366f1186c121 254 }
Zbyszek 15:791f35b0f220 255 newDataFlag = 1; //Once new data has been read set this flag to notify software that new data is received so that it proceeds with processing it.
Zbyszek 9:9ed9dffd602a 256 }
Zbyszek 9:9ed9dffd602a 257
Zbyszek 9:9ed9dffd602a 258
Zbyszek 9:9ed9dffd602a 259 //Interrupt Handler for DMA1 Channel 3
Zbyszek 11:366f1186c121 260 extern "C" void DMA1_Channel3_IRQHandler(void) {
Zbyszek 10:5b96211275d4 261 if(DMA1->ISR&(1u<<9)) { //Check whteher data transmit transfer is complete
Zbyszek 10:5b96211275d4 262 //Read data from the array that stores received data
Zbyszek 13:c7e8e277f884 263 if(dataRequestFlag == 1 && dataLoadedFlag == 1) {
Zbyszek 13:c7e8e277f884 264 for(int x = 0; x <= 11; x++) {
Zbyszek 13:c7e8e277f884 265 if(x < 7) { //Data is only loaded in first 7 places
Zbyszek 13:c7e8e277f884 266 if(x == 0) { //IMU ID is loaded in array position 0
Zbyszek 13:c7e8e277f884 267 data_to_transmit[x] = IMU_Data_Array[x]; //Load the IMU data for transmission
Zbyszek 14:7bbaafa22f8d 268 //data_to_transmit[x] = 1; //Test Input
Zbyszek 13:c7e8e277f884 269 }
Zbyszek 13:c7e8e277f884 270 else { //Rest is loaded in the following order: x, y, z
Zbyszek 13:c7e8e277f884 271 data_to_transmit[x] = IMU_Data_Array[x]; //Load the IMU data for transmission
Zbyszek 14:7bbaafa22f8d 272 //data_to_transmit[x] = 770 + ((x - 1) * 514); //Test Input
Zbyszek 13:c7e8e277f884 273 }
Zbyszek 13:c7e8e277f884 274 }
Zbyszek 13:c7e8e277f884 275 else { //After 7 positions have been filled, the rest is filled with zeros
Zbyszek 13:c7e8e277f884 276 data_to_transmit[x] = 0; //Above 6 there is nothing more to send so send zeros.
Zbyszek 13:c7e8e277f884 277 }
Zbyszek 13:c7e8e277f884 278 }
Zbyszek 13:c7e8e277f884 279 dataRequestFlag = 0; //Data request has been fulfilled and therefore clear the flag
Zbyszek 10:5b96211275d4 280 }
Zbyszek 13:c7e8e277f884 281 else { //if the two flags arent 1 then load this transmission with zeros
Zbyszek 13:c7e8e277f884 282 for(int x = 0; x <= 11; x++) {
Zbyszek 13:c7e8e277f884 283 data_to_transmit[x] = 0;
Zbyszek 13:c7e8e277f884 284 }
Zbyszek 13:c7e8e277f884 285 }
Zbyszek 10:5b96211275d4 286 CLEAR_DMA1_CH3_IFCR_GFLAG(); //Clear global channel interrupt flag for channel 3
Zbyszek 13:c7e8e277f884 287 } //Clear Global Interrupt flag
Zbyszek 9:9ed9dffd602a 288 }
Zbyszek 9:9ed9dffd602a 289