Zbigniew Druzbacki / Mbed 2 deprecated SPI_Slave

SPI slave program to enable communication between the FPGA and the STM32L432 board.

Dependencies:   mbed

DMA_SPI.cpp@8:e87027349167, 2019-02-27 (annotated)

Committer:
Zbyszek
Date:
Wed Feb 27 23:35:51 2019 +0000
Revision:
8:e87027349167
Child:
9:9ed9dffd602a
Exporting To Mbed studio

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Zbyszek 8:e87027349167 1 #include "mbed.h"
Zbyszek 8:e87027349167 2 #include "DMA_SPI.h"
Zbyszek 8:e87027349167 3
Zbyszek 8:e87027349167 4 extern int16_t data_to_transmit[6];
Zbyszek 8:e87027349167 5 extern int16_t received_data[12];
Zbyszek 8:e87027349167 6
Zbyszek 8:e87027349167 7 void initDMA() {
Zbyszek 8:e87027349167 8 RCC->AHB1ENR|= (RCC_AHB1ENR_DMA1EN); //Enable the DMA clock
Zbyszek 8:e87027349167 9
Zbyszek 8:e87027349167 10 DMA1->DMA1_CSELR |= (
Zbyszek 8:e87027349167 11 (0x01<<(4*(C2S - 1))) //Select SPI1_Rx on DMA1 Channel 2
Zbyszek 8:e87027349167 12 |(0x01<<(4*(C3S - 1))) //Select SPI1_Tx on DMA1 Channel 3
Zbyszek 8:e87027349167 13 );
Zbyszek 8:e87027349167 14
Zbyszek 8:e87027349167 15
Zbyszek 8:e87027349167 16
Zbyszek 8:e87027349167 17 DMA1->DMA1_CCR2 &= ~((0x01 << 4)); //Clear bit 4 in channel 2 configuration register to set the channel to read from peripheral. Peripheral -> Memory
Zbyszek 8:e87027349167 18 DMA1->DMA1_CCR2 |= ((0x01 << 8) //Set peripheral size to 16-bits
Zbyszek 8:e87027349167 19 |(0x01 << 10) //Set memory size to 16-bits
Zbyszek 8:e87027349167 20 |(0x01 << 7) //Set to memory increment mode
Zbyszek 8:e87027349167 21 |(0x01 << 1) //Transfer complete interrupt enable
Zbyszek 8:e87027349167 22 );
Zbyszek 8:e87027349167 23
Zbyszek 8:e87027349167 24 DMA1->DMA1_CNDTR2 = 12; //number of data to transfer from the peripherla to memory
Zbyszek 8:e87027349167 25 DMA1->DMA1_CPAR2 = SPI1->DR;
Zbyszek 8:e87027349167 26 DMA1->DMA1_CMAR2 = received_data;
Zbyszek 8:e87027349167 27
Zbyszek 8:e87027349167 28
Zbyszek 8:e87027349167 29 DMA1->DMA1_CCR3 |= ((0x01 << 4)); //Clear bit 4 in channel 3 configuration register to set the channel to read from memory. Memroy -> Peripheral
Zbyszek 8:e87027349167 30 DMA1->DMA1_CCR3 |= ((0x01 << 8) //Set peripheral size to 16-bits
Zbyszek 8:e87027349167 31 |(0x01 << 10) //Set memory size to 16-bits
Zbyszek 8:e87027349167 32 |(0x01 << 7) //Set to memory increment mode
Zbyszek 8:e87027349167 33 |(0x01 << 1) //Transfer complete interrupt enable
Zbyszek 8:e87027349167 34 );
Zbyszek 8:e87027349167 35
Zbyszek 8:e87027349167 36 DMA1->DMA1_CNDTR3 = 6; //number of data to transfer from memory to the peripheral
Zbyszek 8:e87027349167 37 DMA1->DMA1_CPAR3 = SPI1->DR;
Zbyszek 8:e87027349167 38 DMA1->DMA1_CMAR3 = data_to_transmit;
Zbyszek 8:e87027349167 39
Zbyszek 8:e87027349167 40
Zbyszek 8:e87027349167 41 DMA1->DMA1_CCR2 |= (0x01<<0); //Enable channel 2. Must be disabled in order to be able to alter DMA
Zbyszek 8:e87027349167 42 DMA1->DMA_CCR3 |= (0x01<<0); //Enable channel 3. Must be disabled in order to be able to alter DMA
Zbyszek 8:e87027349167 43
Zbyszek 8:e87027349167 44
Zbyszek 8:e87027349167 45 NVIC->ISER[0]|= (1u<<12); //Enable DMA1 channel 2 interrupt
Zbyszek 8:e87027349167 46 NVIC->ISER[0]|= (1u<<13); //Enable DMA1 channel 3 interrupt
Zbyszek 8:e87027349167 47 //NVIC_EnableIRQ(EXTI15_10_IRQn); //enable the interrupt request
Zbyszek 8:e87027349167 48
Zbyszek 8:e87027349167 49 }