Rob Kluin / nRF51822

Fork of nRF51822 by Nordic Semiconductor

Committer:
rgrover1
Date:
Thu Jul 02 09:08:44 2015 +0100
Revision:
362:6fa0d4d555f6
Parent:
361:d2405f5a4853
Child:
370:295f76db798e
Synchronized with git rev 2716309c
Author: Rohit Grover
Release 0.4.0
=============

This is a major release which introduces the GATT Client functionality. It
aligns with release 0.4.0 of BLE_API.

Enhancements
~~~~~~~~~~~~

* Introduce GattClient. This includes functionality for service-discovery,
connections, and attribute-reads and writes. You'll find a demo program for
LEDBlinker on the mbed.org Bluetooth team page to use the new APIs. Some of
the GATT client functionality hasn't been implemented yet, but the APIs have
been added.

* We've added an implementation for the abstract base class for
SecurityManager. All security related APIs have been moved into that.

* There has been a major cleanup of APIs under BLE. APIs have now been
categorized as belonging to Gap, GattServer, GattClient, or SecurityManager.
There are accessors to get references for Gap, GattServer, GattClient, and
SecurityManager. A former call to ble.setAddress(...) is now expected to be
achieved with ble.gap().setAddress(...).

* We've cleaned up our APIs, and this has resulted in dropping some APIs like
BLE::reset().

* We've also dropped GattServer::initializeGattDatabase(). THis was added at
some point to support controllers where a commit point was needed to
indicate when the application had finished constructing the GATT database.
This API would get called internally before Gap::startAdvertising(). We now
expect the underlying port to do the equivalent of initializeGattDatabase()
implicitly upon Gap::startAdvertising().

* We've added a version of Gap::disconnect() which takes a connection handle.
The previous API (which did not take a connection handle) has been
deprecated; it will still work for situations where there's only a single
active connection. We hold on to that API to allow existing code to migrate
to the new API.

Bugfixes
~~~~~~~~

* None.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
rgrover1 362:6fa0d4d555f6 1 /*
rgrover1 362:6fa0d4d555f6 2 * Copyright (c) Nordic Semiconductor ASA
rgrover1 362:6fa0d4d555f6 3 * All rights reserved.
rgrover1 362:6fa0d4d555f6 4 *
rgrover1 362:6fa0d4d555f6 5 * Redistribution and use in source and binary forms, with or without modification,
rgrover1 362:6fa0d4d555f6 6 * are permitted provided that the following conditions are met:
rgrover1 362:6fa0d4d555f6 7 *
rgrover1 362:6fa0d4d555f6 8 * 1. Redistributions of source code must retain the above copyright notice, this
rgrover1 362:6fa0d4d555f6 9 * list of conditions and the following disclaimer.
rgrover1 362:6fa0d4d555f6 10 *
rgrover1 362:6fa0d4d555f6 11 * 2. Redistributions in binary form must reproduce the above copyright notice, this
rgrover1 362:6fa0d4d555f6 12 * list of conditions and the following disclaimer in the documentation and/or
rgrover1 362:6fa0d4d555f6 13 * other materials provided with the distribution.
rgrover1 362:6fa0d4d555f6 14 *
rgrover1 362:6fa0d4d555f6 15 * 3. Neither the name of Nordic Semiconductor ASA nor the names of other
rgrover1 362:6fa0d4d555f6 16 * contributors to this software may be used to endorse or promote products
rgrover1 362:6fa0d4d555f6 17 * derived from this software without specific prior written permission.
rgrover1 362:6fa0d4d555f6 18 *
rgrover1 362:6fa0d4d555f6 19 *
rgrover1 362:6fa0d4d555f6 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
rgrover1 362:6fa0d4d555f6 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
rgrover1 362:6fa0d4d555f6 22 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
rgrover1 362:6fa0d4d555f6 23 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
rgrover1 362:6fa0d4d555f6 24 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
rgrover1 362:6fa0d4d555f6 25 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
rgrover1 362:6fa0d4d555f6 26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
rgrover1 362:6fa0d4d555f6 27 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
rgrover1 362:6fa0d4d555f6 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
rgrover1 362:6fa0d4d555f6 29 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
rgrover1 362:6fa0d4d555f6 30 *
rgrover1 362:6fa0d4d555f6 31 */
rgrover1 362:6fa0d4d555f6 32
rgrover1 362:6fa0d4d555f6 33 /** @addtogroup nRF51
rgrover1 362:6fa0d4d555f6 34 * @{
rgrover1 362:6fa0d4d555f6 35 */
rgrover1 362:6fa0d4d555f6 36
rgrover1 362:6fa0d4d555f6 37 #ifndef NRF51_H
rgrover1 362:6fa0d4d555f6 38 #define NRF51_H
rgrover1 362:6fa0d4d555f6 39
rgrover1 362:6fa0d4d555f6 40 #ifdef __cplusplus
rgrover1 362:6fa0d4d555f6 41 extern "C" {
rgrover1 362:6fa0d4d555f6 42 #endif
rgrover1 362:6fa0d4d555f6 43
rgrover1 362:6fa0d4d555f6 44
rgrover1 362:6fa0d4d555f6 45 /* ------------------------- Interrupt Number Definition ------------------------ */
rgrover1 362:6fa0d4d555f6 46
rgrover1 362:6fa0d4d555f6 47 typedef enum {
rgrover1 362:6fa0d4d555f6 48 /* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
rgrover1 362:6fa0d4d555f6 49 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
rgrover1 362:6fa0d4d555f6 50 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
rgrover1 362:6fa0d4d555f6 51 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
rgrover1 362:6fa0d4d555f6 52 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
rgrover1 362:6fa0d4d555f6 53 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
rgrover1 362:6fa0d4d555f6 54 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
rgrover1 362:6fa0d4d555f6 55 SysTick_IRQn = -1, /*!< 15 System Tick Timer */
rgrover1 362:6fa0d4d555f6 56 /* ---------------------- nRF51 Specific Interrupt Numbers ---------------------- */
rgrover1 362:6fa0d4d555f6 57 POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */
rgrover1 362:6fa0d4d555f6 58 RADIO_IRQn = 1, /*!< 1 RADIO */
rgrover1 362:6fa0d4d555f6 59 UART0_IRQn = 2, /*!< 2 UART0 */
rgrover1 362:6fa0d4d555f6 60 SPI0_TWI0_IRQn = 3, /*!< 3 SPI0_TWI0 */
rgrover1 362:6fa0d4d555f6 61 SPI1_TWI1_IRQn = 4, /*!< 4 SPI1_TWI1 */
rgrover1 362:6fa0d4d555f6 62 GPIOTE_IRQn = 6, /*!< 6 GPIOTE */
rgrover1 362:6fa0d4d555f6 63 ADC_IRQn = 7, /*!< 7 ADC */
rgrover1 362:6fa0d4d555f6 64 TIMER0_IRQn = 8, /*!< 8 TIMER0 */
rgrover1 362:6fa0d4d555f6 65 TIMER1_IRQn = 9, /*!< 9 TIMER1 */
rgrover1 362:6fa0d4d555f6 66 TIMER2_IRQn = 10, /*!< 10 TIMER2 */
rgrover1 362:6fa0d4d555f6 67 RTC0_IRQn = 11, /*!< 11 RTC0 */
rgrover1 362:6fa0d4d555f6 68 TEMP_IRQn = 12, /*!< 12 TEMP */
rgrover1 362:6fa0d4d555f6 69 RNG_IRQn = 13, /*!< 13 RNG */
rgrover1 362:6fa0d4d555f6 70 ECB_IRQn = 14, /*!< 14 ECB */
rgrover1 362:6fa0d4d555f6 71 CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */
rgrover1 362:6fa0d4d555f6 72 WDT_IRQn = 16, /*!< 16 WDT */
rgrover1 362:6fa0d4d555f6 73 RTC1_IRQn = 17, /*!< 17 RTC1 */
rgrover1 362:6fa0d4d555f6 74 QDEC_IRQn = 18, /*!< 18 QDEC */
rgrover1 362:6fa0d4d555f6 75 LPCOMP_IRQn = 19, /*!< 19 LPCOMP */
rgrover1 362:6fa0d4d555f6 76 SWI0_IRQn = 20, /*!< 20 SWI0 */
rgrover1 362:6fa0d4d555f6 77 SWI1_IRQn = 21, /*!< 21 SWI1 */
rgrover1 362:6fa0d4d555f6 78 SWI2_IRQn = 22, /*!< 22 SWI2 */
rgrover1 362:6fa0d4d555f6 79 SWI3_IRQn = 23, /*!< 23 SWI3 */
rgrover1 362:6fa0d4d555f6 80 SWI4_IRQn = 24, /*!< 24 SWI4 */
rgrover1 362:6fa0d4d555f6 81 SWI5_IRQn = 25 /*!< 25 SWI5 */
rgrover1 362:6fa0d4d555f6 82 } IRQn_Type;
rgrover1 362:6fa0d4d555f6 83
rgrover1 362:6fa0d4d555f6 84
rgrover1 362:6fa0d4d555f6 85 /** @addtogroup Configuration_of_CMSIS
rgrover1 362:6fa0d4d555f6 86 * @{
rgrover1 362:6fa0d4d555f6 87 */
rgrover1 362:6fa0d4d555f6 88
rgrover1 362:6fa0d4d555f6 89
rgrover1 362:6fa0d4d555f6 90 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 91 /* ================ Processor and Core Peripheral Section ================ */
rgrover1 362:6fa0d4d555f6 92 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 93
rgrover1 362:6fa0d4d555f6 94 /* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */
rgrover1 362:6fa0d4d555f6 95 #define __CM0_REV 0x0301 /*!< Cortex-M0 Core Revision */
rgrover1 362:6fa0d4d555f6 96 #define __MPU_PRESENT 0 /*!< MPU present or not */
rgrover1 362:6fa0d4d555f6 97 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
rgrover1 362:6fa0d4d555f6 98 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
rgrover1 362:6fa0d4d555f6 99 /** @} */ /* End of group Configuration_of_CMSIS */
rgrover1 362:6fa0d4d555f6 100
rgrover1 362:6fa0d4d555f6 101 #include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */
rgrover1 362:6fa0d4d555f6 102 #include "system_nrf51.h" /*!< nRF51 System */
rgrover1 362:6fa0d4d555f6 103
rgrover1 362:6fa0d4d555f6 104
rgrover1 362:6fa0d4d555f6 105 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 106 /* ================ Device Specific Peripheral Section ================ */
rgrover1 362:6fa0d4d555f6 107 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 108
rgrover1 362:6fa0d4d555f6 109
rgrover1 362:6fa0d4d555f6 110 /** @addtogroup Device_Peripheral_Registers
rgrover1 362:6fa0d4d555f6 111 * @{
rgrover1 362:6fa0d4d555f6 112 */
rgrover1 362:6fa0d4d555f6 113
rgrover1 362:6fa0d4d555f6 114
rgrover1 362:6fa0d4d555f6 115 /* ------------------- Start of section using anonymous unions ------------------ */
rgrover1 362:6fa0d4d555f6 116 #if defined(__CC_ARM)
rgrover1 362:6fa0d4d555f6 117 #pragma push
rgrover1 362:6fa0d4d555f6 118 #pragma anon_unions
rgrover1 362:6fa0d4d555f6 119 #elif defined(__ICCARM__)
rgrover1 362:6fa0d4d555f6 120 #pragma language=extended
rgrover1 362:6fa0d4d555f6 121 #elif defined(__GNUC__)
rgrover1 362:6fa0d4d555f6 122 /* anonymous unions are enabled by default */
rgrover1 362:6fa0d4d555f6 123 #elif defined(__TMS470__)
rgrover1 362:6fa0d4d555f6 124 /* anonymous unions are enabled by default */
rgrover1 362:6fa0d4d555f6 125 #elif defined(__TASKING__)
rgrover1 362:6fa0d4d555f6 126 #pragma warning 586
rgrover1 362:6fa0d4d555f6 127 #else
rgrover1 362:6fa0d4d555f6 128 #warning Not supported compiler type
rgrover1 362:6fa0d4d555f6 129 #endif
rgrover1 362:6fa0d4d555f6 130
rgrover1 362:6fa0d4d555f6 131
rgrover1 362:6fa0d4d555f6 132 typedef struct {
rgrover1 362:6fa0d4d555f6 133 __IO uint32_t CPU0; /*!< Configurable priority configuration register for CPU0. */
rgrover1 362:6fa0d4d555f6 134 __IO uint32_t SPIS1; /*!< Configurable priority configuration register for SPIS1. */
rgrover1 362:6fa0d4d555f6 135 __IO uint32_t RADIO; /*!< Configurable priority configuration register for RADIO. */
rgrover1 362:6fa0d4d555f6 136 __IO uint32_t ECB; /*!< Configurable priority configuration register for ECB. */
rgrover1 362:6fa0d4d555f6 137 __IO uint32_t CCM; /*!< Configurable priority configuration register for CCM. */
rgrover1 362:6fa0d4d555f6 138 __IO uint32_t AAR; /*!< Configurable priority configuration register for AAR. */
rgrover1 362:6fa0d4d555f6 139 } AMLI_RAMPRI_Type;
rgrover1 362:6fa0d4d555f6 140
rgrover1 362:6fa0d4d555f6 141 typedef struct {
rgrover1 362:6fa0d4d555f6 142 __IO uint32_t SCK; /*!< Pin select for SCK. */
rgrover1 362:6fa0d4d555f6 143 __IO uint32_t MOSI; /*!< Pin select for MOSI. */
rgrover1 362:6fa0d4d555f6 144 __IO uint32_t MISO; /*!< Pin select for MISO. */
rgrover1 362:6fa0d4d555f6 145 } SPIM_PSEL_Type;
rgrover1 362:6fa0d4d555f6 146
rgrover1 362:6fa0d4d555f6 147 typedef struct {
rgrover1 362:6fa0d4d555f6 148 __IO uint32_t PTR; /*!< Data pointer. */
rgrover1 362:6fa0d4d555f6 149 __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to receive. */
rgrover1 362:6fa0d4d555f6 150 __I uint32_t AMOUNT; /*!< Number of bytes received in the last transaction. */
rgrover1 362:6fa0d4d555f6 151 } SPIM_RXD_Type;
rgrover1 362:6fa0d4d555f6 152
rgrover1 362:6fa0d4d555f6 153 typedef struct {
rgrover1 362:6fa0d4d555f6 154 __IO uint32_t PTR; /*!< Data pointer. */
rgrover1 362:6fa0d4d555f6 155 __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to send. */
rgrover1 362:6fa0d4d555f6 156 __I uint32_t AMOUNT; /*!< Number of bytes sent in the last transaction. */
rgrover1 362:6fa0d4d555f6 157 } SPIM_TXD_Type;
rgrover1 362:6fa0d4d555f6 158
rgrover1 362:6fa0d4d555f6 159 typedef struct {
rgrover1 362:6fa0d4d555f6 160 __O uint32_t EN; /*!< Enable channel group. */
rgrover1 362:6fa0d4d555f6 161 __O uint32_t DIS; /*!< Disable channel group. */
rgrover1 362:6fa0d4d555f6 162 } PPI_TASKS_CHG_Type;
rgrover1 362:6fa0d4d555f6 163
rgrover1 362:6fa0d4d555f6 164 typedef struct {
rgrover1 362:6fa0d4d555f6 165 __IO uint32_t EEP; /*!< Channel event end-point. */
rgrover1 362:6fa0d4d555f6 166 __IO uint32_t TEP; /*!< Channel task end-point. */
rgrover1 362:6fa0d4d555f6 167 } PPI_CH_Type;
rgrover1 362:6fa0d4d555f6 168
rgrover1 362:6fa0d4d555f6 169 typedef struct {
rgrover1 362:6fa0d4d555f6 170 __I uint32_t PART; /*!< Part code */
rgrover1 362:6fa0d4d555f6 171 __I uint32_t VARIANT; /*!< Part variant */
rgrover1 362:6fa0d4d555f6 172 __I uint32_t PACKAGE; /*!< Package option */
rgrover1 362:6fa0d4d555f6 173 __I uint32_t RAM; /*!< RAM variant */
rgrover1 362:6fa0d4d555f6 174 __I uint32_t FLASH; /*!< Flash variant */
rgrover1 362:6fa0d4d555f6 175 __I uint32_t RESERVED[3]; /*!< Reserved */
rgrover1 362:6fa0d4d555f6 176 } FICR_INFO_Type;
rgrover1 362:6fa0d4d555f6 177
rgrover1 362:6fa0d4d555f6 178
rgrover1 362:6fa0d4d555f6 179 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 180 /* ================ POWER ================ */
rgrover1 362:6fa0d4d555f6 181 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 182
rgrover1 362:6fa0d4d555f6 183
rgrover1 362:6fa0d4d555f6 184 /**
rgrover1 362:6fa0d4d555f6 185 * @brief Power Control. (POWER)
rgrover1 362:6fa0d4d555f6 186 */
rgrover1 362:6fa0d4d555f6 187
rgrover1 362:6fa0d4d555f6 188 typedef struct { /*!< POWER Structure */
rgrover1 362:6fa0d4d555f6 189 __I uint32_t RESERVED0[30];
rgrover1 362:6fa0d4d555f6 190 __O uint32_t TASKS_CONSTLAT; /*!< Enable constant latency mode. */
rgrover1 362:6fa0d4d555f6 191 __O uint32_t TASKS_LOWPWR; /*!< Enable low power mode (variable latency). */
rgrover1 362:6fa0d4d555f6 192 __I uint32_t RESERVED1[34];
rgrover1 362:6fa0d4d555f6 193 __IO uint32_t EVENTS_POFWARN; /*!< Power failure warning. */
rgrover1 362:6fa0d4d555f6 194 __I uint32_t RESERVED2[126];
rgrover1 362:6fa0d4d555f6 195 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 362:6fa0d4d555f6 196 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 362:6fa0d4d555f6 197 __I uint32_t RESERVED3[61];
rgrover1 362:6fa0d4d555f6 198 __IO uint32_t RESETREAS; /*!< Reset reason. */
rgrover1 362:6fa0d4d555f6 199 __I uint32_t RESERVED4[9];
rgrover1 362:6fa0d4d555f6 200 __I uint32_t RAMSTATUS; /*!< Ram status register. */
rgrover1 362:6fa0d4d555f6 201 __I uint32_t RESERVED5[53];
rgrover1 362:6fa0d4d555f6 202 __O uint32_t SYSTEMOFF; /*!< System off register. */
rgrover1 362:6fa0d4d555f6 203 __I uint32_t RESERVED6[3];
rgrover1 362:6fa0d4d555f6 204 __IO uint32_t POFCON; /*!< Power failure configuration. */
rgrover1 362:6fa0d4d555f6 205 __I uint32_t RESERVED7[2];
rgrover1 362:6fa0d4d555f6 206 __IO uint32_t GPREGRET; /*!< General purpose retention register. This register is a retained
rgrover1 362:6fa0d4d555f6 207 register. */
rgrover1 362:6fa0d4d555f6 208 __I uint32_t RESERVED8;
rgrover1 362:6fa0d4d555f6 209 __IO uint32_t RAMON; /*!< Ram on/off. */
rgrover1 362:6fa0d4d555f6 210 __I uint32_t RESERVED9[7];
rgrover1 362:6fa0d4d555f6 211 __IO uint32_t RESET; /*!< Pin reset functionality configuration register. This register
rgrover1 362:6fa0d4d555f6 212 is a retained register. */
rgrover1 362:6fa0d4d555f6 213 __I uint32_t RESERVED10[3];
rgrover1 362:6fa0d4d555f6 214 __IO uint32_t RAMONB; /*!< Ram on/off. */
rgrover1 362:6fa0d4d555f6 215 __I uint32_t RESERVED11[8];
rgrover1 362:6fa0d4d555f6 216 __IO uint32_t DCDCEN; /*!< DCDC converter enable configuration register. */
rgrover1 362:6fa0d4d555f6 217 __I uint32_t RESERVED12[291];
rgrover1 362:6fa0d4d555f6 218 __IO uint32_t DCDCFORCE; /*!< DCDC power-up force register. */
rgrover1 362:6fa0d4d555f6 219 } NRF_POWER_Type;
rgrover1 362:6fa0d4d555f6 220
rgrover1 362:6fa0d4d555f6 221
rgrover1 362:6fa0d4d555f6 222 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 223 /* ================ CLOCK ================ */
rgrover1 362:6fa0d4d555f6 224 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 225
rgrover1 362:6fa0d4d555f6 226
rgrover1 362:6fa0d4d555f6 227 /**
rgrover1 362:6fa0d4d555f6 228 * @brief Clock control. (CLOCK)
rgrover1 362:6fa0d4d555f6 229 */
rgrover1 362:6fa0d4d555f6 230
rgrover1 362:6fa0d4d555f6 231 typedef struct { /*!< CLOCK Structure */
rgrover1 362:6fa0d4d555f6 232 __O uint32_t TASKS_HFCLKSTART; /*!< Start HFCLK clock source. */
rgrover1 362:6fa0d4d555f6 233 __O uint32_t TASKS_HFCLKSTOP; /*!< Stop HFCLK clock source. */
rgrover1 362:6fa0d4d555f6 234 __O uint32_t TASKS_LFCLKSTART; /*!< Start LFCLK clock source. */
rgrover1 362:6fa0d4d555f6 235 __O uint32_t TASKS_LFCLKSTOP; /*!< Stop LFCLK clock source. */
rgrover1 362:6fa0d4d555f6 236 __O uint32_t TASKS_CAL; /*!< Start calibration of LFCLK RC oscillator. */
rgrover1 362:6fa0d4d555f6 237 __O uint32_t TASKS_CTSTART; /*!< Start calibration timer. */
rgrover1 362:6fa0d4d555f6 238 __O uint32_t TASKS_CTSTOP; /*!< Stop calibration timer. */
rgrover1 362:6fa0d4d555f6 239 __I uint32_t RESERVED0[57];
rgrover1 362:6fa0d4d555f6 240 __IO uint32_t EVENTS_HFCLKSTARTED; /*!< HFCLK oscillator started. */
rgrover1 362:6fa0d4d555f6 241 __IO uint32_t EVENTS_LFCLKSTARTED; /*!< LFCLK oscillator started. */
rgrover1 362:6fa0d4d555f6 242 __I uint32_t RESERVED1;
rgrover1 362:6fa0d4d555f6 243 __IO uint32_t EVENTS_DONE; /*!< Calibration of LFCLK RC oscillator completed. */
rgrover1 362:6fa0d4d555f6 244 __IO uint32_t EVENTS_CTTO; /*!< Calibration timer timeout. */
rgrover1 362:6fa0d4d555f6 245 __I uint32_t RESERVED2[124];
rgrover1 362:6fa0d4d555f6 246 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 362:6fa0d4d555f6 247 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 362:6fa0d4d555f6 248 __I uint32_t RESERVED3[63];
rgrover1 362:6fa0d4d555f6 249 __I uint32_t HFCLKRUN; /*!< Task HFCLKSTART trigger status. */
rgrover1 362:6fa0d4d555f6 250 __I uint32_t HFCLKSTAT; /*!< High frequency clock status. */
rgrover1 362:6fa0d4d555f6 251 __I uint32_t RESERVED4;
rgrover1 362:6fa0d4d555f6 252 __I uint32_t LFCLKRUN; /*!< Task LFCLKSTART triggered status. */
rgrover1 362:6fa0d4d555f6 253 __I uint32_t LFCLKSTAT; /*!< Low frequency clock status. */
rgrover1 362:6fa0d4d555f6 254 __I uint32_t LFCLKSRCCOPY; /*!< Clock source for the LFCLK clock, set when task LKCLKSTART is
rgrover1 362:6fa0d4d555f6 255 triggered. */
rgrover1 362:6fa0d4d555f6 256 __I uint32_t RESERVED5[62];
rgrover1 362:6fa0d4d555f6 257 __IO uint32_t LFCLKSRC; /*!< Clock source for the LFCLK clock. */
rgrover1 362:6fa0d4d555f6 258 __I uint32_t RESERVED6[7];
rgrover1 362:6fa0d4d555f6 259 __IO uint32_t CTIV; /*!< Calibration timer interval. */
rgrover1 362:6fa0d4d555f6 260 __I uint32_t RESERVED7[5];
rgrover1 362:6fa0d4d555f6 261 __IO uint32_t XTALFREQ; /*!< Crystal frequency. */
rgrover1 362:6fa0d4d555f6 262 } NRF_CLOCK_Type;
rgrover1 362:6fa0d4d555f6 263
rgrover1 362:6fa0d4d555f6 264
rgrover1 362:6fa0d4d555f6 265 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 266 /* ================ MPU ================ */
rgrover1 362:6fa0d4d555f6 267 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 268
rgrover1 362:6fa0d4d555f6 269
rgrover1 362:6fa0d4d555f6 270 /**
rgrover1 362:6fa0d4d555f6 271 * @brief Memory Protection Unit. (MPU)
rgrover1 362:6fa0d4d555f6 272 */
rgrover1 362:6fa0d4d555f6 273
rgrover1 362:6fa0d4d555f6 274 typedef struct { /*!< MPU Structure */
rgrover1 362:6fa0d4d555f6 275 __I uint32_t RESERVED0[330];
rgrover1 362:6fa0d4d555f6 276 __IO uint32_t PERR0; /*!< Configuration of peripherals in mpu regions. */
rgrover1 362:6fa0d4d555f6 277 __IO uint32_t RLENR0; /*!< Length of RAM region 0. */
rgrover1 362:6fa0d4d555f6 278 __I uint32_t RESERVED1[52];
rgrover1 362:6fa0d4d555f6 279 __IO uint32_t PROTENSET0; /*!< Erase and write protection bit enable set register. */
rgrover1 362:6fa0d4d555f6 280 __IO uint32_t PROTENSET1; /*!< Erase and write protection bit enable set register. */
rgrover1 362:6fa0d4d555f6 281 __IO uint32_t DISABLEINDEBUG; /*!< Disable erase and write protection mechanism in debug mode. */
rgrover1 362:6fa0d4d555f6 282 __IO uint32_t PROTBLOCKSIZE; /*!< Erase and write protection block size. */
rgrover1 362:6fa0d4d555f6 283 } NRF_MPU_Type;
rgrover1 362:6fa0d4d555f6 284
rgrover1 362:6fa0d4d555f6 285
rgrover1 362:6fa0d4d555f6 286 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 287 /* ================ PU ================ */
rgrover1 362:6fa0d4d555f6 288 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 289
rgrover1 362:6fa0d4d555f6 290
rgrover1 362:6fa0d4d555f6 291 /**
rgrover1 362:6fa0d4d555f6 292 * @brief Patch unit. (PU)
rgrover1 362:6fa0d4d555f6 293 */
rgrover1 362:6fa0d4d555f6 294
rgrover1 362:6fa0d4d555f6 295 typedef struct { /*!< PU Structure */
rgrover1 362:6fa0d4d555f6 296 __I uint32_t RESERVED0[448];
rgrover1 362:6fa0d4d555f6 297 __IO uint32_t REPLACEADDR[8]; /*!< Address of first instruction to replace. */
rgrover1 362:6fa0d4d555f6 298 __I uint32_t RESERVED1[24];
rgrover1 362:6fa0d4d555f6 299 __IO uint32_t PATCHADDR[8]; /*!< Relative address of patch instructions. */
rgrover1 362:6fa0d4d555f6 300 __I uint32_t RESERVED2[24];
rgrover1 362:6fa0d4d555f6 301 __IO uint32_t PATCHEN; /*!< Patch enable register. */
rgrover1 362:6fa0d4d555f6 302 __IO uint32_t PATCHENSET; /*!< Patch enable register. */
rgrover1 362:6fa0d4d555f6 303 __IO uint32_t PATCHENCLR; /*!< Patch disable register. */
rgrover1 362:6fa0d4d555f6 304 } NRF_PU_Type;
rgrover1 362:6fa0d4d555f6 305
rgrover1 362:6fa0d4d555f6 306
rgrover1 362:6fa0d4d555f6 307 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 308 /* ================ AMLI ================ */
rgrover1 362:6fa0d4d555f6 309 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 310
rgrover1 362:6fa0d4d555f6 311
rgrover1 362:6fa0d4d555f6 312 /**
rgrover1 362:6fa0d4d555f6 313 * @brief AHB Multi-Layer Interface. (AMLI)
rgrover1 362:6fa0d4d555f6 314 */
rgrover1 362:6fa0d4d555f6 315
rgrover1 362:6fa0d4d555f6 316 typedef struct { /*!< AMLI Structure */
rgrover1 362:6fa0d4d555f6 317 __I uint32_t RESERVED0[896];
rgrover1 362:6fa0d4d555f6 318 AMLI_RAMPRI_Type RAMPRI; /*!< RAM configurable priority configuration structure. */
rgrover1 362:6fa0d4d555f6 319 } NRF_AMLI_Type;
rgrover1 362:6fa0d4d555f6 320
rgrover1 362:6fa0d4d555f6 321
rgrover1 362:6fa0d4d555f6 322 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 323 /* ================ RADIO ================ */
rgrover1 362:6fa0d4d555f6 324 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 325
rgrover1 362:6fa0d4d555f6 326
rgrover1 362:6fa0d4d555f6 327 /**
rgrover1 362:6fa0d4d555f6 328 * @brief The radio. (RADIO)
rgrover1 362:6fa0d4d555f6 329 */
rgrover1 362:6fa0d4d555f6 330
rgrover1 362:6fa0d4d555f6 331 typedef struct { /*!< RADIO Structure */
rgrover1 362:6fa0d4d555f6 332 __O uint32_t TASKS_TXEN; /*!< Enable radio in TX mode. */
rgrover1 362:6fa0d4d555f6 333 __O uint32_t TASKS_RXEN; /*!< Enable radio in RX mode. */
rgrover1 362:6fa0d4d555f6 334 __O uint32_t TASKS_START; /*!< Start radio. */
rgrover1 362:6fa0d4d555f6 335 __O uint32_t TASKS_STOP; /*!< Stop radio. */
rgrover1 362:6fa0d4d555f6 336 __O uint32_t TASKS_DISABLE; /*!< Disable radio. */
rgrover1 362:6fa0d4d555f6 337 __O uint32_t TASKS_RSSISTART; /*!< Start the RSSI and take one sample of the receive signal strength. */
rgrover1 362:6fa0d4d555f6 338 __O uint32_t TASKS_RSSISTOP; /*!< Stop the RSSI measurement. */
rgrover1 362:6fa0d4d555f6 339 __O uint32_t TASKS_BCSTART; /*!< Start the bit counter. */
rgrover1 362:6fa0d4d555f6 340 __O uint32_t TASKS_BCSTOP; /*!< Stop the bit counter. */
rgrover1 362:6fa0d4d555f6 341 __I uint32_t RESERVED0[55];
rgrover1 362:6fa0d4d555f6 342 __IO uint32_t EVENTS_READY; /*!< Ready event. */
rgrover1 362:6fa0d4d555f6 343 __IO uint32_t EVENTS_ADDRESS; /*!< Address event. */
rgrover1 362:6fa0d4d555f6 344 __IO uint32_t EVENTS_PAYLOAD; /*!< Payload event. */
rgrover1 362:6fa0d4d555f6 345 __IO uint32_t EVENTS_END; /*!< End event. */
rgrover1 362:6fa0d4d555f6 346 __IO uint32_t EVENTS_DISABLED; /*!< Disable event. */
rgrover1 362:6fa0d4d555f6 347 __IO uint32_t EVENTS_DEVMATCH; /*!< A device address match occurred on the last received packet. */
rgrover1 362:6fa0d4d555f6 348 __IO uint32_t EVENTS_DEVMISS; /*!< No device address match occurred on the last received packet. */
rgrover1 362:6fa0d4d555f6 349 __IO uint32_t EVENTS_RSSIEND; /*!< Sampling of the receive signal strength complete. A new RSSI
rgrover1 362:6fa0d4d555f6 350 sample is ready for readout at the RSSISAMPLE register. */
rgrover1 362:6fa0d4d555f6 351 __I uint32_t RESERVED1[2];
rgrover1 362:6fa0d4d555f6 352 __IO uint32_t EVENTS_BCMATCH; /*!< Bit counter reached bit count value specified in BC register. */
rgrover1 362:6fa0d4d555f6 353 __I uint32_t RESERVED2[53];
rgrover1 362:6fa0d4d555f6 354 __IO uint32_t SHORTS; /*!< Shortcuts for the radio. */
rgrover1 362:6fa0d4d555f6 355 __I uint32_t RESERVED3[64];
rgrover1 362:6fa0d4d555f6 356 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 362:6fa0d4d555f6 357 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 362:6fa0d4d555f6 358 __I uint32_t RESERVED4[61];
rgrover1 362:6fa0d4d555f6 359 __I uint32_t CRCSTATUS; /*!< CRC status of received packet. */
rgrover1 362:6fa0d4d555f6 360 __I uint32_t CD; /*!< Carrier detect. */
rgrover1 362:6fa0d4d555f6 361 __I uint32_t RXMATCH; /*!< Received address. */
rgrover1 362:6fa0d4d555f6 362 __I uint32_t RXCRC; /*!< Received CRC. */
rgrover1 362:6fa0d4d555f6 363 __I uint32_t DAI; /*!< Device address match index. */
rgrover1 362:6fa0d4d555f6 364 __I uint32_t RESERVED5[60];
rgrover1 362:6fa0d4d555f6 365 __IO uint32_t PACKETPTR; /*!< Packet pointer. Decision point: START task. */
rgrover1 362:6fa0d4d555f6 366 __IO uint32_t FREQUENCY; /*!< Frequency. */
rgrover1 362:6fa0d4d555f6 367 __IO uint32_t TXPOWER; /*!< Output power. */
rgrover1 362:6fa0d4d555f6 368 __IO uint32_t MODE; /*!< Data rate and modulation. */
rgrover1 362:6fa0d4d555f6 369 __IO uint32_t PCNF0; /*!< Packet configuration 0. */
rgrover1 362:6fa0d4d555f6 370 __IO uint32_t PCNF1; /*!< Packet configuration 1. */
rgrover1 362:6fa0d4d555f6 371 __IO uint32_t BASE0; /*!< Radio base address 0. Decision point: START task. */
rgrover1 362:6fa0d4d555f6 372 __IO uint32_t BASE1; /*!< Radio base address 1. Decision point: START task. */
rgrover1 362:6fa0d4d555f6 373 __IO uint32_t PREFIX0; /*!< Prefixes bytes for logical addresses 0 to 3. */
rgrover1 362:6fa0d4d555f6 374 __IO uint32_t PREFIX1; /*!< Prefixes bytes for logical addresses 4 to 7. */
rgrover1 362:6fa0d4d555f6 375 __IO uint32_t TXADDRESS; /*!< Transmit address select. */
rgrover1 362:6fa0d4d555f6 376 __IO uint32_t RXADDRESSES; /*!< Receive address select. */
rgrover1 362:6fa0d4d555f6 377 __IO uint32_t CRCCNF; /*!< CRC configuration. */
rgrover1 362:6fa0d4d555f6 378 __IO uint32_t CRCPOLY; /*!< CRC polynomial. */
rgrover1 362:6fa0d4d555f6 379 __IO uint32_t CRCINIT; /*!< CRC initial value. */
rgrover1 362:6fa0d4d555f6 380 __IO uint32_t TEST; /*!< Test features enable register. */
rgrover1 362:6fa0d4d555f6 381 __IO uint32_t TIFS; /*!< Inter Frame Spacing in microseconds. */
rgrover1 362:6fa0d4d555f6 382 __I uint32_t RSSISAMPLE; /*!< RSSI sample. */
rgrover1 362:6fa0d4d555f6 383 __I uint32_t RESERVED6;
rgrover1 362:6fa0d4d555f6 384 __I uint32_t STATE; /*!< Current radio state. */
rgrover1 362:6fa0d4d555f6 385 __IO uint32_t DATAWHITEIV; /*!< Data whitening initial value. */
rgrover1 362:6fa0d4d555f6 386 __I uint32_t RESERVED7[2];
rgrover1 362:6fa0d4d555f6 387 __IO uint32_t BCC; /*!< Bit counter compare. */
rgrover1 362:6fa0d4d555f6 388 __I uint32_t RESERVED8[39];
rgrover1 362:6fa0d4d555f6 389 __IO uint32_t DAB[8]; /*!< Device address base segment. */
rgrover1 362:6fa0d4d555f6 390 __IO uint32_t DAP[8]; /*!< Device address prefix. */
rgrover1 362:6fa0d4d555f6 391 __IO uint32_t DACNF; /*!< Device address match configuration. */
rgrover1 362:6fa0d4d555f6 392 __I uint32_t RESERVED9[56];
rgrover1 362:6fa0d4d555f6 393 __IO uint32_t OVERRIDE0; /*!< Trim value override register 0. */
rgrover1 362:6fa0d4d555f6 394 __IO uint32_t OVERRIDE1; /*!< Trim value override register 1. */
rgrover1 362:6fa0d4d555f6 395 __IO uint32_t OVERRIDE2; /*!< Trim value override register 2. */
rgrover1 362:6fa0d4d555f6 396 __IO uint32_t OVERRIDE3; /*!< Trim value override register 3. */
rgrover1 362:6fa0d4d555f6 397 __IO uint32_t OVERRIDE4; /*!< Trim value override register 4. */
rgrover1 362:6fa0d4d555f6 398 __I uint32_t RESERVED10[561];
rgrover1 362:6fa0d4d555f6 399 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 362:6fa0d4d555f6 400 } NRF_RADIO_Type;
rgrover1 362:6fa0d4d555f6 401
rgrover1 362:6fa0d4d555f6 402
rgrover1 362:6fa0d4d555f6 403 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 404 /* ================ UART ================ */
rgrover1 362:6fa0d4d555f6 405 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 406
rgrover1 362:6fa0d4d555f6 407
rgrover1 362:6fa0d4d555f6 408 /**
rgrover1 362:6fa0d4d555f6 409 * @brief Universal Asynchronous Receiver/Transmitter. (UART)
rgrover1 362:6fa0d4d555f6 410 */
rgrover1 362:6fa0d4d555f6 411
rgrover1 362:6fa0d4d555f6 412 typedef struct { /*!< UART Structure */
rgrover1 362:6fa0d4d555f6 413 __O uint32_t TASKS_STARTRX; /*!< Start UART receiver. */
rgrover1 362:6fa0d4d555f6 414 __O uint32_t TASKS_STOPRX; /*!< Stop UART receiver. */
rgrover1 362:6fa0d4d555f6 415 __O uint32_t TASKS_STARTTX; /*!< Start UART transmitter. */
rgrover1 362:6fa0d4d555f6 416 __O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter. */
rgrover1 362:6fa0d4d555f6 417 __I uint32_t RESERVED0[3];
rgrover1 362:6fa0d4d555f6 418 __O uint32_t TASKS_SUSPEND; /*!< Suspend UART. */
rgrover1 362:6fa0d4d555f6 419 __I uint32_t RESERVED1[56];
rgrover1 362:6fa0d4d555f6 420 __IO uint32_t EVENTS_CTS; /*!< CTS activated. */
rgrover1 362:6fa0d4d555f6 421 __IO uint32_t EVENTS_NCTS; /*!< CTS deactivated. */
rgrover1 362:6fa0d4d555f6 422 __IO uint32_t EVENTS_RXDRDY; /*!< Data received in RXD. */
rgrover1 362:6fa0d4d555f6 423 __I uint32_t RESERVED2[4];
rgrover1 362:6fa0d4d555f6 424 __IO uint32_t EVENTS_TXDRDY; /*!< Data sent from TXD. */
rgrover1 362:6fa0d4d555f6 425 __I uint32_t RESERVED3;
rgrover1 362:6fa0d4d555f6 426 __IO uint32_t EVENTS_ERROR; /*!< Error detected. */
rgrover1 362:6fa0d4d555f6 427 __I uint32_t RESERVED4[7];
rgrover1 362:6fa0d4d555f6 428 __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout. */
rgrover1 362:6fa0d4d555f6 429 __I uint32_t RESERVED5[46];
rgrover1 362:6fa0d4d555f6 430 __IO uint32_t SHORTS; /*!< Shortcuts for UART. */
rgrover1 362:6fa0d4d555f6 431 __I uint32_t RESERVED6[64];
rgrover1 362:6fa0d4d555f6 432 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 362:6fa0d4d555f6 433 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 362:6fa0d4d555f6 434 __I uint32_t RESERVED7[93];
rgrover1 362:6fa0d4d555f6 435 __IO uint32_t ERRORSRC; /*!< Error source. Write error field to 1 to clear error. */
rgrover1 362:6fa0d4d555f6 436 __I uint32_t RESERVED8[31];
rgrover1 362:6fa0d4d555f6 437 __IO uint32_t ENABLE; /*!< Enable UART and acquire IOs. */
rgrover1 362:6fa0d4d555f6 438 __I uint32_t RESERVED9;
rgrover1 362:6fa0d4d555f6 439 __IO uint32_t PSELRTS; /*!< Pin select for RTS. */
rgrover1 362:6fa0d4d555f6 440 __IO uint32_t PSELTXD; /*!< Pin select for TXD. */
rgrover1 362:6fa0d4d555f6 441 __IO uint32_t PSELCTS; /*!< Pin select for CTS. */
rgrover1 362:6fa0d4d555f6 442 __IO uint32_t PSELRXD; /*!< Pin select for RXD. */
rgrover1 362:6fa0d4d555f6 443 __I uint32_t RXD; /*!< RXD register. On read action the buffer pointer is displaced.
rgrover1 362:6fa0d4d555f6 444 Once read the character is consumed. If read when no character
rgrover1 362:6fa0d4d555f6 445 available, the UART will stop working. */
rgrover1 362:6fa0d4d555f6 446 __O uint32_t TXD; /*!< TXD register. */
rgrover1 362:6fa0d4d555f6 447 __I uint32_t RESERVED10;
rgrover1 362:6fa0d4d555f6 448 __IO uint32_t BAUDRATE; /*!< UART Baudrate. */
rgrover1 362:6fa0d4d555f6 449 __I uint32_t RESERVED11[17];
rgrover1 362:6fa0d4d555f6 450 __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control register. */
rgrover1 362:6fa0d4d555f6 451 __I uint32_t RESERVED12[675];
rgrover1 362:6fa0d4d555f6 452 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 362:6fa0d4d555f6 453 } NRF_UART_Type;
rgrover1 362:6fa0d4d555f6 454
rgrover1 362:6fa0d4d555f6 455
rgrover1 362:6fa0d4d555f6 456 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 457 /* ================ SPI ================ */
rgrover1 362:6fa0d4d555f6 458 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 459
rgrover1 362:6fa0d4d555f6 460
rgrover1 362:6fa0d4d555f6 461 /**
rgrover1 362:6fa0d4d555f6 462 * @brief SPI master 0. (SPI)
rgrover1 362:6fa0d4d555f6 463 */
rgrover1 362:6fa0d4d555f6 464
rgrover1 362:6fa0d4d555f6 465 typedef struct { /*!< SPI Structure */
rgrover1 362:6fa0d4d555f6 466 __I uint32_t RESERVED0[66];
rgrover1 362:6fa0d4d555f6 467 __IO uint32_t EVENTS_READY; /*!< TXD byte sent and RXD byte received. */
rgrover1 362:6fa0d4d555f6 468 __I uint32_t RESERVED1[126];
rgrover1 362:6fa0d4d555f6 469 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 362:6fa0d4d555f6 470 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 362:6fa0d4d555f6 471 __I uint32_t RESERVED2[125];
rgrover1 362:6fa0d4d555f6 472 __IO uint32_t ENABLE; /*!< Enable SPI. */
rgrover1 362:6fa0d4d555f6 473 __I uint32_t RESERVED3;
rgrover1 362:6fa0d4d555f6 474 __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
rgrover1 362:6fa0d4d555f6 475 __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
rgrover1 362:6fa0d4d555f6 476 __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
rgrover1 362:6fa0d4d555f6 477 __I uint32_t RESERVED4;
rgrover1 362:6fa0d4d555f6 478 __I uint32_t RXD; /*!< RX data. */
rgrover1 362:6fa0d4d555f6 479 __IO uint32_t TXD; /*!< TX data. */
rgrover1 362:6fa0d4d555f6 480 __I uint32_t RESERVED5;
rgrover1 362:6fa0d4d555f6 481 __IO uint32_t FREQUENCY; /*!< SPI frequency */
rgrover1 362:6fa0d4d555f6 482 __I uint32_t RESERVED6[11];
rgrover1 362:6fa0d4d555f6 483 __IO uint32_t CONFIG; /*!< Configuration register. */
rgrover1 362:6fa0d4d555f6 484 __I uint32_t RESERVED7[681];
rgrover1 362:6fa0d4d555f6 485 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 362:6fa0d4d555f6 486 } NRF_SPI_Type;
rgrover1 362:6fa0d4d555f6 487
rgrover1 362:6fa0d4d555f6 488
rgrover1 362:6fa0d4d555f6 489 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 490 /* ================ TWI ================ */
rgrover1 362:6fa0d4d555f6 491 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 492
rgrover1 362:6fa0d4d555f6 493
rgrover1 362:6fa0d4d555f6 494 /**
rgrover1 362:6fa0d4d555f6 495 * @brief Two-wire interface master 0. (TWI)
rgrover1 362:6fa0d4d555f6 496 */
rgrover1 362:6fa0d4d555f6 497
rgrover1 362:6fa0d4d555f6 498 typedef struct { /*!< TWI Structure */
rgrover1 362:6fa0d4d555f6 499 __O uint32_t TASKS_STARTRX; /*!< Start 2-Wire master receive sequence. */
rgrover1 362:6fa0d4d555f6 500 __I uint32_t RESERVED0;
rgrover1 362:6fa0d4d555f6 501 __O uint32_t TASKS_STARTTX; /*!< Start 2-Wire master transmit sequence. */
rgrover1 362:6fa0d4d555f6 502 __I uint32_t RESERVED1[2];
rgrover1 362:6fa0d4d555f6 503 __O uint32_t TASKS_STOP; /*!< Stop 2-Wire transaction. */
rgrover1 362:6fa0d4d555f6 504 __I uint32_t RESERVED2;
rgrover1 362:6fa0d4d555f6 505 __O uint32_t TASKS_SUSPEND; /*!< Suspend 2-Wire transaction. */
rgrover1 362:6fa0d4d555f6 506 __O uint32_t TASKS_RESUME; /*!< Resume 2-Wire transaction. */
rgrover1 362:6fa0d4d555f6 507 __I uint32_t RESERVED3[56];
rgrover1 362:6fa0d4d555f6 508 __IO uint32_t EVENTS_STOPPED; /*!< Two-wire stopped. */
rgrover1 362:6fa0d4d555f6 509 __IO uint32_t EVENTS_RXDREADY; /*!< Two-wire ready to deliver new RXD byte received. */
rgrover1 362:6fa0d4d555f6 510 __I uint32_t RESERVED4[4];
rgrover1 362:6fa0d4d555f6 511 __IO uint32_t EVENTS_TXDSENT; /*!< Two-wire finished sending last TXD byte. */
rgrover1 362:6fa0d4d555f6 512 __I uint32_t RESERVED5;
rgrover1 362:6fa0d4d555f6 513 __IO uint32_t EVENTS_ERROR; /*!< Two-wire error detected. */
rgrover1 362:6fa0d4d555f6 514 __I uint32_t RESERVED6[4];
rgrover1 362:6fa0d4d555f6 515 __IO uint32_t EVENTS_BB; /*!< Two-wire byte boundary. */
rgrover1 362:6fa0d4d555f6 516 __I uint32_t RESERVED7[3];
rgrover1 362:6fa0d4d555f6 517 __IO uint32_t EVENTS_SUSPENDED; /*!< Two-wire suspended. */
rgrover1 362:6fa0d4d555f6 518 __I uint32_t RESERVED8[45];
rgrover1 362:6fa0d4d555f6 519 __IO uint32_t SHORTS; /*!< Shortcuts for TWI. */
rgrover1 362:6fa0d4d555f6 520 __I uint32_t RESERVED9[64];
rgrover1 362:6fa0d4d555f6 521 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 362:6fa0d4d555f6 522 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 362:6fa0d4d555f6 523 __I uint32_t RESERVED10[110];
rgrover1 362:6fa0d4d555f6 524 __IO uint32_t ERRORSRC; /*!< Two-wire error source. Write error field to 1 to clear error. */
rgrover1 362:6fa0d4d555f6 525 __I uint32_t RESERVED11[14];
rgrover1 362:6fa0d4d555f6 526 __IO uint32_t ENABLE; /*!< Enable two-wire master. */
rgrover1 362:6fa0d4d555f6 527 __I uint32_t RESERVED12;
rgrover1 362:6fa0d4d555f6 528 __IO uint32_t PSELSCL; /*!< Pin select for SCL. */
rgrover1 362:6fa0d4d555f6 529 __IO uint32_t PSELSDA; /*!< Pin select for SDA. */
rgrover1 362:6fa0d4d555f6 530 __I uint32_t RESERVED13[2];
rgrover1 362:6fa0d4d555f6 531 __I uint32_t RXD; /*!< RX data register. */
rgrover1 362:6fa0d4d555f6 532 __IO uint32_t TXD; /*!< TX data register. */
rgrover1 362:6fa0d4d555f6 533 __I uint32_t RESERVED14;
rgrover1 362:6fa0d4d555f6 534 __IO uint32_t FREQUENCY; /*!< Two-wire frequency. */
rgrover1 362:6fa0d4d555f6 535 __I uint32_t RESERVED15[24];
rgrover1 362:6fa0d4d555f6 536 __IO uint32_t ADDRESS; /*!< Address used in the two-wire transfer. */
rgrover1 362:6fa0d4d555f6 537 __I uint32_t RESERVED16[668];
rgrover1 362:6fa0d4d555f6 538 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 362:6fa0d4d555f6 539 } NRF_TWI_Type;
rgrover1 362:6fa0d4d555f6 540
rgrover1 362:6fa0d4d555f6 541
rgrover1 362:6fa0d4d555f6 542 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 543 /* ================ SPIS ================ */
rgrover1 362:6fa0d4d555f6 544 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 545
rgrover1 362:6fa0d4d555f6 546
rgrover1 362:6fa0d4d555f6 547 /**
rgrover1 362:6fa0d4d555f6 548 * @brief SPI slave 1. (SPIS)
rgrover1 362:6fa0d4d555f6 549 */
rgrover1 362:6fa0d4d555f6 550
rgrover1 362:6fa0d4d555f6 551 typedef struct { /*!< SPIS Structure */
rgrover1 362:6fa0d4d555f6 552 __I uint32_t RESERVED0[9];
rgrover1 362:6fa0d4d555f6 553 __O uint32_t TASKS_ACQUIRE; /*!< Acquire SPI semaphore. */
rgrover1 362:6fa0d4d555f6 554 __O uint32_t TASKS_RELEASE; /*!< Release SPI semaphore. */
rgrover1 362:6fa0d4d555f6 555 __I uint32_t RESERVED1[54];
rgrover1 362:6fa0d4d555f6 556 __IO uint32_t EVENTS_END; /*!< Granted transaction completed. */
rgrover1 362:6fa0d4d555f6 557 __I uint32_t RESERVED2[8];
rgrover1 362:6fa0d4d555f6 558 __IO uint32_t EVENTS_ACQUIRED; /*!< Semaphore acquired. */
rgrover1 362:6fa0d4d555f6 559 __I uint32_t RESERVED3[53];
rgrover1 362:6fa0d4d555f6 560 __IO uint32_t SHORTS; /*!< Shortcuts for SPIS. */
rgrover1 362:6fa0d4d555f6 561 __I uint32_t RESERVED4[64];
rgrover1 362:6fa0d4d555f6 562 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 362:6fa0d4d555f6 563 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 362:6fa0d4d555f6 564 __I uint32_t RESERVED5[61];
rgrover1 362:6fa0d4d555f6 565 __I uint32_t SEMSTAT; /*!< Semaphore status. */
rgrover1 362:6fa0d4d555f6 566 __I uint32_t RESERVED6[15];
rgrover1 362:6fa0d4d555f6 567 __IO uint32_t STATUS; /*!< Status from last transaction. */
rgrover1 362:6fa0d4d555f6 568 __I uint32_t RESERVED7[47];
rgrover1 362:6fa0d4d555f6 569 __IO uint32_t ENABLE; /*!< Enable SPIS. */
rgrover1 362:6fa0d4d555f6 570 __I uint32_t RESERVED8;
rgrover1 362:6fa0d4d555f6 571 __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
rgrover1 362:6fa0d4d555f6 572 __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
rgrover1 362:6fa0d4d555f6 573 __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
rgrover1 362:6fa0d4d555f6 574 __IO uint32_t PSELCSN; /*!< Pin select for CSN. */
rgrover1 362:6fa0d4d555f6 575 __I uint32_t RESERVED9[7];
rgrover1 362:6fa0d4d555f6 576 __IO uint32_t RXDPTR; /*!< RX data pointer. */
rgrover1 362:6fa0d4d555f6 577 __IO uint32_t MAXRX; /*!< Maximum number of bytes in the receive buffer. */
rgrover1 362:6fa0d4d555f6 578 __I uint32_t AMOUNTRX; /*!< Number of bytes received in last granted transaction. */
rgrover1 362:6fa0d4d555f6 579 __I uint32_t RESERVED10;
rgrover1 362:6fa0d4d555f6 580 __IO uint32_t TXDPTR; /*!< TX data pointer. */
rgrover1 362:6fa0d4d555f6 581 __IO uint32_t MAXTX; /*!< Maximum number of bytes in the transmit buffer. */
rgrover1 362:6fa0d4d555f6 582 __I uint32_t AMOUNTTX; /*!< Number of bytes transmitted in last granted transaction. */
rgrover1 362:6fa0d4d555f6 583 __I uint32_t RESERVED11;
rgrover1 362:6fa0d4d555f6 584 __IO uint32_t CONFIG; /*!< Configuration register. */
rgrover1 362:6fa0d4d555f6 585 __I uint32_t RESERVED12;
rgrover1 362:6fa0d4d555f6 586 __IO uint32_t DEF; /*!< Default character. */
rgrover1 362:6fa0d4d555f6 587 __I uint32_t RESERVED13[24];
rgrover1 362:6fa0d4d555f6 588 __IO uint32_t ORC; /*!< Over-read character. */
rgrover1 362:6fa0d4d555f6 589 __I uint32_t RESERVED14[654];
rgrover1 362:6fa0d4d555f6 590 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 362:6fa0d4d555f6 591 } NRF_SPIS_Type;
rgrover1 362:6fa0d4d555f6 592
rgrover1 362:6fa0d4d555f6 593
rgrover1 362:6fa0d4d555f6 594 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 595 /* ================ SPIM ================ */
rgrover1 362:6fa0d4d555f6 596 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 597
rgrover1 362:6fa0d4d555f6 598
rgrover1 362:6fa0d4d555f6 599 /**
rgrover1 362:6fa0d4d555f6 600 * @brief SPI master with easyDMA 1. (SPIM)
rgrover1 362:6fa0d4d555f6 601 */
rgrover1 362:6fa0d4d555f6 602
rgrover1 362:6fa0d4d555f6 603 typedef struct { /*!< SPIM Structure */
rgrover1 362:6fa0d4d555f6 604 __I uint32_t RESERVED0[4];
rgrover1 362:6fa0d4d555f6 605 __O uint32_t TASKS_START; /*!< Start SPI transaction. */
rgrover1 362:6fa0d4d555f6 606 __O uint32_t TASKS_STOP; /*!< Stop SPI transaction. */
rgrover1 362:6fa0d4d555f6 607 __I uint32_t RESERVED1;
rgrover1 362:6fa0d4d555f6 608 __O uint32_t TASKS_SUSPEND; /*!< Suspend SPI transaction. */
rgrover1 362:6fa0d4d555f6 609 __O uint32_t TASKS_RESUME; /*!< Resume SPI transaction. */
rgrover1 362:6fa0d4d555f6 610 __I uint32_t RESERVED2[56];
rgrover1 362:6fa0d4d555f6 611 __IO uint32_t EVENTS_STOPPED; /*!< SPI transaction has stopped. */
rgrover1 362:6fa0d4d555f6 612 __I uint32_t RESERVED3[2];
rgrover1 362:6fa0d4d555f6 613 __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached. */
rgrover1 362:6fa0d4d555f6 614 __I uint32_t RESERVED4;
rgrover1 362:6fa0d4d555f6 615 __IO uint32_t EVENTS_END; /*!< End of RXD buffer and TXD buffer reached. */
rgrover1 362:6fa0d4d555f6 616 __I uint32_t RESERVED5;
rgrover1 362:6fa0d4d555f6 617 __IO uint32_t EVENTS_ENDTX; /*!< End of TXD buffer reached. */
rgrover1 362:6fa0d4d555f6 618 __I uint32_t RESERVED6[10];
rgrover1 362:6fa0d4d555f6 619 __IO uint32_t EVENTS_STARTED; /*!< Transaction started. */
rgrover1 362:6fa0d4d555f6 620 __I uint32_t RESERVED7[44];
rgrover1 362:6fa0d4d555f6 621 __IO uint32_t SHORTS; /*!< Shortcuts for SPIM. */
rgrover1 362:6fa0d4d555f6 622 __I uint32_t RESERVED8[64];
rgrover1 362:6fa0d4d555f6 623 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 362:6fa0d4d555f6 624 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 362:6fa0d4d555f6 625 __I uint32_t RESERVED9[125];
rgrover1 362:6fa0d4d555f6 626 __IO uint32_t ENABLE; /*!< Enable SPIM. */
rgrover1 362:6fa0d4d555f6 627 __I uint32_t RESERVED10;
rgrover1 362:6fa0d4d555f6 628 SPIM_PSEL_Type PSEL; /*!< Pin select configuration. */
rgrover1 362:6fa0d4d555f6 629 __I uint32_t RESERVED11;
rgrover1 362:6fa0d4d555f6 630 __I uint32_t RXDDATA; /*!< RXD register. */
rgrover1 362:6fa0d4d555f6 631 __IO uint32_t TXDDATA; /*!< TXD register. */
rgrover1 362:6fa0d4d555f6 632 __I uint32_t RESERVED12;
rgrover1 362:6fa0d4d555f6 633 __IO uint32_t FREQUENCY; /*!< SPI frequency. */
rgrover1 362:6fa0d4d555f6 634 __I uint32_t RESERVED13[3];
rgrover1 362:6fa0d4d555f6 635 SPIM_RXD_Type RXD; /*!< RXD EasyDMA configuration and status. */
rgrover1 362:6fa0d4d555f6 636 __I uint32_t RESERVED14;
rgrover1 362:6fa0d4d555f6 637 SPIM_TXD_Type TXD; /*!< TXD EasyDMA configuration and status. */
rgrover1 362:6fa0d4d555f6 638 __I uint32_t RESERVED15;
rgrover1 362:6fa0d4d555f6 639 __IO uint32_t CONFIG; /*!< Configuration register. */
rgrover1 362:6fa0d4d555f6 640 __I uint32_t RESERVED16[26];
rgrover1 362:6fa0d4d555f6 641 __IO uint32_t ORC; /*!< Over-read character. */
rgrover1 362:6fa0d4d555f6 642 __I uint32_t RESERVED17[654];
rgrover1 362:6fa0d4d555f6 643 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 362:6fa0d4d555f6 644 } NRF_SPIM_Type;
rgrover1 362:6fa0d4d555f6 645
rgrover1 362:6fa0d4d555f6 646
rgrover1 362:6fa0d4d555f6 647 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 648 /* ================ GPIOTE ================ */
rgrover1 362:6fa0d4d555f6 649 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 650
rgrover1 362:6fa0d4d555f6 651
rgrover1 362:6fa0d4d555f6 652 /**
rgrover1 362:6fa0d4d555f6 653 * @brief GPIO tasks and events. (GPIOTE)
rgrover1 362:6fa0d4d555f6 654 */
rgrover1 362:6fa0d4d555f6 655
rgrover1 362:6fa0d4d555f6 656 typedef struct { /*!< GPIOTE Structure */
rgrover1 362:6fa0d4d555f6 657 __O uint32_t TASKS_OUT[4]; /*!< Tasks asssociated with GPIOTE channels. */
rgrover1 362:6fa0d4d555f6 658 __I uint32_t RESERVED0[60];
rgrover1 362:6fa0d4d555f6 659 __IO uint32_t EVENTS_IN[4]; /*!< Tasks asssociated with GPIOTE channels. */
rgrover1 362:6fa0d4d555f6 660 __I uint32_t RESERVED1[27];
rgrover1 362:6fa0d4d555f6 661 __IO uint32_t EVENTS_PORT; /*!< Event generated from multiple pins. */
rgrover1 362:6fa0d4d555f6 662 __I uint32_t RESERVED2[97];
rgrover1 362:6fa0d4d555f6 663 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 362:6fa0d4d555f6 664 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 362:6fa0d4d555f6 665 __I uint32_t RESERVED3[129];
rgrover1 362:6fa0d4d555f6 666 __IO uint32_t CONFIG[4]; /*!< Channel configuration registers. */
rgrover1 362:6fa0d4d555f6 667 __I uint32_t RESERVED4[695];
rgrover1 362:6fa0d4d555f6 668 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 362:6fa0d4d555f6 669 } NRF_GPIOTE_Type;
rgrover1 362:6fa0d4d555f6 670
rgrover1 362:6fa0d4d555f6 671
rgrover1 362:6fa0d4d555f6 672 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 673 /* ================ ADC ================ */
rgrover1 362:6fa0d4d555f6 674 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 675
rgrover1 362:6fa0d4d555f6 676
rgrover1 362:6fa0d4d555f6 677 /**
rgrover1 362:6fa0d4d555f6 678 * @brief Analog to digital converter. (ADC)
rgrover1 362:6fa0d4d555f6 679 */
rgrover1 362:6fa0d4d555f6 680
rgrover1 362:6fa0d4d555f6 681 typedef struct { /*!< ADC Structure */
rgrover1 362:6fa0d4d555f6 682 __O uint32_t TASKS_START; /*!< Start an ADC conversion. */
rgrover1 362:6fa0d4d555f6 683 __O uint32_t TASKS_STOP; /*!< Stop ADC. */
rgrover1 362:6fa0d4d555f6 684 __I uint32_t RESERVED0[62];
rgrover1 362:6fa0d4d555f6 685 __IO uint32_t EVENTS_END; /*!< ADC conversion complete. */
rgrover1 362:6fa0d4d555f6 686 __I uint32_t RESERVED1[128];
rgrover1 362:6fa0d4d555f6 687 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 362:6fa0d4d555f6 688 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 362:6fa0d4d555f6 689 __I uint32_t RESERVED2[61];
rgrover1 362:6fa0d4d555f6 690 __I uint32_t BUSY; /*!< ADC busy register. */
rgrover1 362:6fa0d4d555f6 691 __I uint32_t RESERVED3[63];
rgrover1 362:6fa0d4d555f6 692 __IO uint32_t ENABLE; /*!< ADC enable. */
rgrover1 362:6fa0d4d555f6 693 __IO uint32_t CONFIG; /*!< ADC configuration register. */
rgrover1 362:6fa0d4d555f6 694 __I uint32_t RESULT; /*!< Result of ADC conversion. */
rgrover1 362:6fa0d4d555f6 695 __I uint32_t RESERVED4[700];
rgrover1 362:6fa0d4d555f6 696 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 362:6fa0d4d555f6 697 } NRF_ADC_Type;
rgrover1 362:6fa0d4d555f6 698
rgrover1 362:6fa0d4d555f6 699
rgrover1 362:6fa0d4d555f6 700 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 701 /* ================ TIMER ================ */
rgrover1 362:6fa0d4d555f6 702 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 703
rgrover1 362:6fa0d4d555f6 704
rgrover1 362:6fa0d4d555f6 705 /**
rgrover1 362:6fa0d4d555f6 706 * @brief Timer 0. (TIMER)
rgrover1 362:6fa0d4d555f6 707 */
rgrover1 362:6fa0d4d555f6 708
rgrover1 362:6fa0d4d555f6 709 typedef struct { /*!< TIMER Structure */
rgrover1 362:6fa0d4d555f6 710 __O uint32_t TASKS_START; /*!< Start Timer. */
rgrover1 362:6fa0d4d555f6 711 __O uint32_t TASKS_STOP; /*!< Stop Timer. */
rgrover1 362:6fa0d4d555f6 712 __O uint32_t TASKS_COUNT; /*!< Increment Timer (In counter mode). */
rgrover1 362:6fa0d4d555f6 713 __O uint32_t TASKS_CLEAR; /*!< Clear timer. */
rgrover1 362:6fa0d4d555f6 714 __O uint32_t TASKS_SHUTDOWN; /*!< Shutdown timer. */
rgrover1 362:6fa0d4d555f6 715 __I uint32_t RESERVED0[11];
rgrover1 362:6fa0d4d555f6 716 __O uint32_t TASKS_CAPTURE[4]; /*!< Capture Timer value to CC[n] registers. */
rgrover1 362:6fa0d4d555f6 717 __I uint32_t RESERVED1[60];
rgrover1 362:6fa0d4d555f6 718 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
rgrover1 362:6fa0d4d555f6 719 __I uint32_t RESERVED2[44];
rgrover1 362:6fa0d4d555f6 720 __IO uint32_t SHORTS; /*!< Shortcuts for Timer. */
rgrover1 362:6fa0d4d555f6 721 __I uint32_t RESERVED3[64];
rgrover1 362:6fa0d4d555f6 722 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 362:6fa0d4d555f6 723 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 362:6fa0d4d555f6 724 __I uint32_t RESERVED4[126];
rgrover1 362:6fa0d4d555f6 725 __IO uint32_t MODE; /*!< Timer Mode selection. */
rgrover1 362:6fa0d4d555f6 726 __IO uint32_t BITMODE; /*!< Sets timer behaviour. */
rgrover1 362:6fa0d4d555f6 727 __I uint32_t RESERVED5;
rgrover1 362:6fa0d4d555f6 728 __IO uint32_t PRESCALER; /*!< 4-bit prescaler to source clock frequency (max value 9). Source
rgrover1 362:6fa0d4d555f6 729 clock frequency is divided by 2^SCALE. */
rgrover1 362:6fa0d4d555f6 730 __I uint32_t RESERVED6[11];
rgrover1 362:6fa0d4d555f6 731 __IO uint32_t CC[4]; /*!< Capture/compare registers. */
rgrover1 362:6fa0d4d555f6 732 __I uint32_t RESERVED7[683];
rgrover1 362:6fa0d4d555f6 733 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 362:6fa0d4d555f6 734 } NRF_TIMER_Type;
rgrover1 362:6fa0d4d555f6 735
rgrover1 362:6fa0d4d555f6 736
rgrover1 362:6fa0d4d555f6 737 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 738 /* ================ RTC ================ */
rgrover1 362:6fa0d4d555f6 739 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 740
rgrover1 362:6fa0d4d555f6 741
rgrover1 362:6fa0d4d555f6 742 /**
rgrover1 362:6fa0d4d555f6 743 * @brief Real time counter 0. (RTC)
rgrover1 362:6fa0d4d555f6 744 */
rgrover1 362:6fa0d4d555f6 745
rgrover1 362:6fa0d4d555f6 746 typedef struct { /*!< RTC Structure */
rgrover1 362:6fa0d4d555f6 747 __O uint32_t TASKS_START; /*!< Start RTC Counter. */
rgrover1 362:6fa0d4d555f6 748 __O uint32_t TASKS_STOP; /*!< Stop RTC Counter. */
rgrover1 362:6fa0d4d555f6 749 __O uint32_t TASKS_CLEAR; /*!< Clear RTC Counter. */
rgrover1 362:6fa0d4d555f6 750 __O uint32_t TASKS_TRIGOVRFLW; /*!< Set COUNTER to 0xFFFFFFF0. */
rgrover1 362:6fa0d4d555f6 751 __I uint32_t RESERVED0[60];
rgrover1 362:6fa0d4d555f6 752 __IO uint32_t EVENTS_TICK; /*!< Event on COUNTER increment. */
rgrover1 362:6fa0d4d555f6 753 __IO uint32_t EVENTS_OVRFLW; /*!< Event on COUNTER overflow. */
rgrover1 362:6fa0d4d555f6 754 __I uint32_t RESERVED1[14];
rgrover1 362:6fa0d4d555f6 755 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
rgrover1 362:6fa0d4d555f6 756 __I uint32_t RESERVED2[109];
rgrover1 362:6fa0d4d555f6 757 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 362:6fa0d4d555f6 758 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 362:6fa0d4d555f6 759 __I uint32_t RESERVED3[13];
rgrover1 362:6fa0d4d555f6 760 __IO uint32_t EVTEN; /*!< Configures event enable routing to PPI for each RTC event. */
rgrover1 362:6fa0d4d555f6 761 __IO uint32_t EVTENSET; /*!< Enable events routing to PPI. The reading of this register gives
rgrover1 362:6fa0d4d555f6 762 the value of EVTEN. */
rgrover1 362:6fa0d4d555f6 763 __IO uint32_t EVTENCLR; /*!< Disable events routing to PPI. The reading of this register
rgrover1 362:6fa0d4d555f6 764 gives the value of EVTEN. */
rgrover1 362:6fa0d4d555f6 765 __I uint32_t RESERVED4[110];
rgrover1 362:6fa0d4d555f6 766 __I uint32_t COUNTER; /*!< Current COUNTER value. */
rgrover1 362:6fa0d4d555f6 767 __IO uint32_t PRESCALER; /*!< 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).
rgrover1 362:6fa0d4d555f6 768 Must be written when RTC is STOPed. */
rgrover1 362:6fa0d4d555f6 769 __I uint32_t RESERVED5[13];
rgrover1 362:6fa0d4d555f6 770 __IO uint32_t CC[4]; /*!< Capture/compare registers. */
rgrover1 362:6fa0d4d555f6 771 __I uint32_t RESERVED6[683];
rgrover1 362:6fa0d4d555f6 772 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 362:6fa0d4d555f6 773 } NRF_RTC_Type;
rgrover1 362:6fa0d4d555f6 774
rgrover1 362:6fa0d4d555f6 775
rgrover1 362:6fa0d4d555f6 776 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 777 /* ================ TEMP ================ */
rgrover1 362:6fa0d4d555f6 778 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 779
rgrover1 362:6fa0d4d555f6 780
rgrover1 362:6fa0d4d555f6 781 /**
rgrover1 362:6fa0d4d555f6 782 * @brief Temperature Sensor. (TEMP)
rgrover1 362:6fa0d4d555f6 783 */
rgrover1 362:6fa0d4d555f6 784
rgrover1 362:6fa0d4d555f6 785 typedef struct { /*!< TEMP Structure */
rgrover1 362:6fa0d4d555f6 786 __O uint32_t TASKS_START; /*!< Start temperature measurement. */
rgrover1 362:6fa0d4d555f6 787 __O uint32_t TASKS_STOP; /*!< Stop temperature measurement. */
rgrover1 362:6fa0d4d555f6 788 __I uint32_t RESERVED0[62];
rgrover1 362:6fa0d4d555f6 789 __IO uint32_t EVENTS_DATARDY; /*!< Temperature measurement complete, data ready event. */
rgrover1 362:6fa0d4d555f6 790 __I uint32_t RESERVED1[128];
rgrover1 362:6fa0d4d555f6 791 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 362:6fa0d4d555f6 792 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 362:6fa0d4d555f6 793 __I uint32_t RESERVED2[127];
rgrover1 362:6fa0d4d555f6 794 __I int32_t TEMP; /*!< Die temperature in degC, 2's complement format, 0.25 degC pecision. */
rgrover1 362:6fa0d4d555f6 795 __I uint32_t RESERVED3[700];
rgrover1 362:6fa0d4d555f6 796 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 362:6fa0d4d555f6 797 } NRF_TEMP_Type;
rgrover1 362:6fa0d4d555f6 798
rgrover1 362:6fa0d4d555f6 799
rgrover1 362:6fa0d4d555f6 800 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 801 /* ================ RNG ================ */
rgrover1 362:6fa0d4d555f6 802 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 803
rgrover1 362:6fa0d4d555f6 804
rgrover1 362:6fa0d4d555f6 805 /**
rgrover1 362:6fa0d4d555f6 806 * @brief Random Number Generator. (RNG)
rgrover1 362:6fa0d4d555f6 807 */
rgrover1 362:6fa0d4d555f6 808
rgrover1 362:6fa0d4d555f6 809 typedef struct { /*!< RNG Structure */
rgrover1 362:6fa0d4d555f6 810 __O uint32_t TASKS_START; /*!< Start the random number generator. */
rgrover1 362:6fa0d4d555f6 811 __O uint32_t TASKS_STOP; /*!< Stop the random number generator. */
rgrover1 362:6fa0d4d555f6 812 __I uint32_t RESERVED0[62];
rgrover1 362:6fa0d4d555f6 813 __IO uint32_t EVENTS_VALRDY; /*!< New random number generated and written to VALUE register. */
rgrover1 362:6fa0d4d555f6 814 __I uint32_t RESERVED1[63];
rgrover1 362:6fa0d4d555f6 815 __IO uint32_t SHORTS; /*!< Shortcuts for the RNG. */
rgrover1 362:6fa0d4d555f6 816 __I uint32_t RESERVED2[64];
rgrover1 362:6fa0d4d555f6 817 __IO uint32_t INTENSET; /*!< Interrupt enable set register */
rgrover1 362:6fa0d4d555f6 818 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register */
rgrover1 362:6fa0d4d555f6 819 __I uint32_t RESERVED3[126];
rgrover1 362:6fa0d4d555f6 820 __IO uint32_t CONFIG; /*!< Configuration register. */
rgrover1 362:6fa0d4d555f6 821 __I uint32_t VALUE; /*!< RNG random number. */
rgrover1 362:6fa0d4d555f6 822 __I uint32_t RESERVED4[700];
rgrover1 362:6fa0d4d555f6 823 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 362:6fa0d4d555f6 824 } NRF_RNG_Type;
rgrover1 362:6fa0d4d555f6 825
rgrover1 362:6fa0d4d555f6 826
rgrover1 362:6fa0d4d555f6 827 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 828 /* ================ ECB ================ */
rgrover1 362:6fa0d4d555f6 829 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 830
rgrover1 362:6fa0d4d555f6 831
rgrover1 362:6fa0d4d555f6 832 /**
rgrover1 362:6fa0d4d555f6 833 * @brief AES ECB Mode Encryption. (ECB)
rgrover1 362:6fa0d4d555f6 834 */
rgrover1 362:6fa0d4d555f6 835
rgrover1 362:6fa0d4d555f6 836 typedef struct { /*!< ECB Structure */
rgrover1 362:6fa0d4d555f6 837 __O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt. If a crypto operation is running, this
rgrover1 362:6fa0d4d555f6 838 will not initiate a new encryption and the ERRORECB event will
rgrover1 362:6fa0d4d555f6 839 be triggered. */
rgrover1 362:6fa0d4d555f6 840 __O uint32_t TASKS_STOPECB; /*!< Stop current ECB encryption. If a crypto operation is running,
rgrover1 362:6fa0d4d555f6 841 this will will trigger the ERRORECB event. */
rgrover1 362:6fa0d4d555f6 842 __I uint32_t RESERVED0[62];
rgrover1 362:6fa0d4d555f6 843 __IO uint32_t EVENTS_ENDECB; /*!< ECB block encrypt complete. */
rgrover1 362:6fa0d4d555f6 844 __IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted due to a STOPECB task or due to an
rgrover1 362:6fa0d4d555f6 845 error. */
rgrover1 362:6fa0d4d555f6 846 __I uint32_t RESERVED1[127];
rgrover1 362:6fa0d4d555f6 847 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 362:6fa0d4d555f6 848 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 362:6fa0d4d555f6 849 __I uint32_t RESERVED2[126];
rgrover1 362:6fa0d4d555f6 850 __IO uint32_t ECBDATAPTR; /*!< ECB block encrypt memory pointer. */
rgrover1 362:6fa0d4d555f6 851 __I uint32_t RESERVED3[701];
rgrover1 362:6fa0d4d555f6 852 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 362:6fa0d4d555f6 853 } NRF_ECB_Type;
rgrover1 362:6fa0d4d555f6 854
rgrover1 362:6fa0d4d555f6 855
rgrover1 362:6fa0d4d555f6 856 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 857 /* ================ AAR ================ */
rgrover1 362:6fa0d4d555f6 858 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 859
rgrover1 362:6fa0d4d555f6 860
rgrover1 362:6fa0d4d555f6 861 /**
rgrover1 362:6fa0d4d555f6 862 * @brief Accelerated Address Resolver. (AAR)
rgrover1 362:6fa0d4d555f6 863 */
rgrover1 362:6fa0d4d555f6 864
rgrover1 362:6fa0d4d555f6 865 typedef struct { /*!< AAR Structure */
rgrover1 362:6fa0d4d555f6 866 __O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK
rgrover1 362:6fa0d4d555f6 867 data structure. */
rgrover1 362:6fa0d4d555f6 868 __I uint32_t RESERVED0;
rgrover1 362:6fa0d4d555f6 869 __O uint32_t TASKS_STOP; /*!< Stop resolving addresses. */
rgrover1 362:6fa0d4d555f6 870 __I uint32_t RESERVED1[61];
rgrover1 362:6fa0d4d555f6 871 __IO uint32_t EVENTS_END; /*!< Address resolution procedure completed. */
rgrover1 362:6fa0d4d555f6 872 __IO uint32_t EVENTS_RESOLVED; /*!< Address resolved. */
rgrover1 362:6fa0d4d555f6 873 __IO uint32_t EVENTS_NOTRESOLVED; /*!< Address not resolved. */
rgrover1 362:6fa0d4d555f6 874 __I uint32_t RESERVED2[126];
rgrover1 362:6fa0d4d555f6 875 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 362:6fa0d4d555f6 876 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 362:6fa0d4d555f6 877 __I uint32_t RESERVED3[61];
rgrover1 362:6fa0d4d555f6 878 __I uint32_t STATUS; /*!< Resolution status. */
rgrover1 362:6fa0d4d555f6 879 __I uint32_t RESERVED4[63];
rgrover1 362:6fa0d4d555f6 880 __IO uint32_t ENABLE; /*!< Enable AAR. */
rgrover1 362:6fa0d4d555f6 881 __IO uint32_t NIRK; /*!< Number of Identity root Keys in the IRK data structure. */
rgrover1 362:6fa0d4d555f6 882 __IO uint32_t IRKPTR; /*!< Pointer to the IRK data structure. */
rgrover1 362:6fa0d4d555f6 883 __I uint32_t RESERVED5;
rgrover1 362:6fa0d4d555f6 884 __IO uint32_t ADDRPTR; /*!< Pointer to the resolvable address (6 bytes). */
rgrover1 362:6fa0d4d555f6 885 __IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
rgrover1 362:6fa0d4d555f6 886 during resolution. A minimum of 3 bytes must be reserved. */
rgrover1 362:6fa0d4d555f6 887 __I uint32_t RESERVED6[697];
rgrover1 362:6fa0d4d555f6 888 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 362:6fa0d4d555f6 889 } NRF_AAR_Type;
rgrover1 362:6fa0d4d555f6 890
rgrover1 362:6fa0d4d555f6 891
rgrover1 362:6fa0d4d555f6 892 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 893 /* ================ CCM ================ */
rgrover1 362:6fa0d4d555f6 894 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 895
rgrover1 362:6fa0d4d555f6 896
rgrover1 362:6fa0d4d555f6 897 /**
rgrover1 362:6fa0d4d555f6 898 * @brief AES CCM Mode Encryption. (CCM)
rgrover1 362:6fa0d4d555f6 899 */
rgrover1 362:6fa0d4d555f6 900
rgrover1 362:6fa0d4d555f6 901 typedef struct { /*!< CCM Structure */
rgrover1 362:6fa0d4d555f6 902 __O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by
rgrover1 362:6fa0d4d555f6 903 itself when completed. */
rgrover1 362:6fa0d4d555f6 904 __O uint32_t TASKS_CRYPT; /*!< Start encrypt/decrypt. This operation will stop by itself when
rgrover1 362:6fa0d4d555f6 905 completed. */
rgrover1 362:6fa0d4d555f6 906 __O uint32_t TASKS_STOP; /*!< Stop encrypt/decrypt. */
rgrover1 362:6fa0d4d555f6 907 __I uint32_t RESERVED0[61];
rgrover1 362:6fa0d4d555f6 908 __IO uint32_t EVENTS_ENDKSGEN; /*!< Keystream generation completed. */
rgrover1 362:6fa0d4d555f6 909 __IO uint32_t EVENTS_ENDCRYPT; /*!< Encrypt/decrypt completed. */
rgrover1 362:6fa0d4d555f6 910 __IO uint32_t EVENTS_ERROR; /*!< Error happened. */
rgrover1 362:6fa0d4d555f6 911 __I uint32_t RESERVED1[61];
rgrover1 362:6fa0d4d555f6 912 __IO uint32_t SHORTS; /*!< Shortcuts for the CCM. */
rgrover1 362:6fa0d4d555f6 913 __I uint32_t RESERVED2[64];
rgrover1 362:6fa0d4d555f6 914 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 362:6fa0d4d555f6 915 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 362:6fa0d4d555f6 916 __I uint32_t RESERVED3[61];
rgrover1 362:6fa0d4d555f6 917 __I uint32_t MICSTATUS; /*!< CCM RX MIC check result. */
rgrover1 362:6fa0d4d555f6 918 __I uint32_t RESERVED4[63];
rgrover1 362:6fa0d4d555f6 919 __IO uint32_t ENABLE; /*!< CCM enable. */
rgrover1 362:6fa0d4d555f6 920 __IO uint32_t MODE; /*!< Operation mode. */
rgrover1 362:6fa0d4d555f6 921 __IO uint32_t CNFPTR; /*!< Pointer to a data structure holding AES key and NONCE vector. */
rgrover1 362:6fa0d4d555f6 922 __IO uint32_t INPTR; /*!< Pointer to the input packet. */
rgrover1 362:6fa0d4d555f6 923 __IO uint32_t OUTPTR; /*!< Pointer to the output packet. */
rgrover1 362:6fa0d4d555f6 924 __IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
rgrover1 362:6fa0d4d555f6 925 during resolution. A minimum of 43 bytes must be reserved. */
rgrover1 362:6fa0d4d555f6 926 __I uint32_t RESERVED5[697];
rgrover1 362:6fa0d4d555f6 927 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 362:6fa0d4d555f6 928 } NRF_CCM_Type;
rgrover1 362:6fa0d4d555f6 929
rgrover1 362:6fa0d4d555f6 930
rgrover1 362:6fa0d4d555f6 931 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 932 /* ================ WDT ================ */
rgrover1 362:6fa0d4d555f6 933 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 934
rgrover1 362:6fa0d4d555f6 935
rgrover1 362:6fa0d4d555f6 936 /**
rgrover1 362:6fa0d4d555f6 937 * @brief Watchdog Timer. (WDT)
rgrover1 362:6fa0d4d555f6 938 */
rgrover1 362:6fa0d4d555f6 939
rgrover1 362:6fa0d4d555f6 940 typedef struct { /*!< WDT Structure */
rgrover1 362:6fa0d4d555f6 941 __O uint32_t TASKS_START; /*!< Start the watchdog. */
rgrover1 362:6fa0d4d555f6 942 __I uint32_t RESERVED0[63];
rgrover1 362:6fa0d4d555f6 943 __IO uint32_t EVENTS_TIMEOUT; /*!< Watchdog timeout. */
rgrover1 362:6fa0d4d555f6 944 __I uint32_t RESERVED1[128];
rgrover1 362:6fa0d4d555f6 945 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 362:6fa0d4d555f6 946 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 362:6fa0d4d555f6 947 __I uint32_t RESERVED2[61];
rgrover1 362:6fa0d4d555f6 948 __I uint32_t RUNSTATUS; /*!< Watchdog running status. */
rgrover1 362:6fa0d4d555f6 949 __I uint32_t REQSTATUS; /*!< Request status. */
rgrover1 362:6fa0d4d555f6 950 __I uint32_t RESERVED3[63];
rgrover1 362:6fa0d4d555f6 951 __IO uint32_t CRV; /*!< Counter reload value in number of 32kiHz clock cycles. */
rgrover1 362:6fa0d4d555f6 952 __IO uint32_t RREN; /*!< Reload request enable. */
rgrover1 362:6fa0d4d555f6 953 __IO uint32_t CONFIG; /*!< Configuration register. */
rgrover1 362:6fa0d4d555f6 954 __I uint32_t RESERVED4[60];
rgrover1 362:6fa0d4d555f6 955 __O uint32_t RR[8]; /*!< Reload requests registers. */
rgrover1 362:6fa0d4d555f6 956 __I uint32_t RESERVED5[631];
rgrover1 362:6fa0d4d555f6 957 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 362:6fa0d4d555f6 958 } NRF_WDT_Type;
rgrover1 362:6fa0d4d555f6 959
rgrover1 362:6fa0d4d555f6 960
rgrover1 362:6fa0d4d555f6 961 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 962 /* ================ QDEC ================ */
rgrover1 362:6fa0d4d555f6 963 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 964
rgrover1 362:6fa0d4d555f6 965
rgrover1 362:6fa0d4d555f6 966 /**
rgrover1 362:6fa0d4d555f6 967 * @brief Rotary decoder. (QDEC)
rgrover1 362:6fa0d4d555f6 968 */
rgrover1 362:6fa0d4d555f6 969
rgrover1 362:6fa0d4d555f6 970 typedef struct { /*!< QDEC Structure */
rgrover1 362:6fa0d4d555f6 971 __O uint32_t TASKS_START; /*!< Start the quadrature decoder. */
rgrover1 362:6fa0d4d555f6 972 __O uint32_t TASKS_STOP; /*!< Stop the quadrature decoder. */
rgrover1 362:6fa0d4d555f6 973 __O uint32_t TASKS_READCLRACC; /*!< Transfers the content from ACC registers to ACCREAD registers,
rgrover1 362:6fa0d4d555f6 974 and clears the ACC registers. */
rgrover1 362:6fa0d4d555f6 975 __I uint32_t RESERVED0[61];
rgrover1 362:6fa0d4d555f6 976 __IO uint32_t EVENTS_SAMPLERDY; /*!< A new sample is written to the sample register. */
rgrover1 362:6fa0d4d555f6 977 __IO uint32_t EVENTS_REPORTRDY; /*!< REPORTPER number of samples accumulated in ACC register, and
rgrover1 362:6fa0d4d555f6 978 ACC register different than zero. */
rgrover1 362:6fa0d4d555f6 979 __IO uint32_t EVENTS_ACCOF; /*!< ACC or ACCDBL register overflow. */
rgrover1 362:6fa0d4d555f6 980 __I uint32_t RESERVED1[61];
rgrover1 362:6fa0d4d555f6 981 __IO uint32_t SHORTS; /*!< Shortcuts for the QDEC. */
rgrover1 362:6fa0d4d555f6 982 __I uint32_t RESERVED2[64];
rgrover1 362:6fa0d4d555f6 983 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 362:6fa0d4d555f6 984 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 362:6fa0d4d555f6 985 __I uint32_t RESERVED3[125];
rgrover1 362:6fa0d4d555f6 986 __IO uint32_t ENABLE; /*!< Enable the QDEC. */
rgrover1 362:6fa0d4d555f6 987 __IO uint32_t LEDPOL; /*!< LED output pin polarity. */
rgrover1 362:6fa0d4d555f6 988 __IO uint32_t SAMPLEPER; /*!< Sample period. */
rgrover1 362:6fa0d4d555f6 989 __I int32_t SAMPLE; /*!< Motion sample value. */
rgrover1 362:6fa0d4d555f6 990 __IO uint32_t REPORTPER; /*!< Number of samples to generate an EVENT_REPORTRDY. */
rgrover1 362:6fa0d4d555f6 991 __I int32_t ACC; /*!< Accumulated valid transitions register. */
rgrover1 362:6fa0d4d555f6 992 __I int32_t ACCREAD; /*!< Snapshot of ACC register. Value generated by the TASKS_READCLEACC
rgrover1 362:6fa0d4d555f6 993 task. */
rgrover1 362:6fa0d4d555f6 994 __IO uint32_t PSELLED; /*!< Pin select for LED output. */
rgrover1 362:6fa0d4d555f6 995 __IO uint32_t PSELA; /*!< Pin select for phase A input. */
rgrover1 362:6fa0d4d555f6 996 __IO uint32_t PSELB; /*!< Pin select for phase B input. */
rgrover1 362:6fa0d4d555f6 997 __IO uint32_t DBFEN; /*!< Enable debouncer input filters. */
rgrover1 362:6fa0d4d555f6 998 __I uint32_t RESERVED4[5];
rgrover1 362:6fa0d4d555f6 999 __IO uint32_t LEDPRE; /*!< Time LED is switched ON before the sample. */
rgrover1 362:6fa0d4d555f6 1000 __I uint32_t ACCDBL; /*!< Accumulated double (error) transitions register. */
rgrover1 362:6fa0d4d555f6 1001 __I uint32_t ACCDBLREAD; /*!< Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC
rgrover1 362:6fa0d4d555f6 1002 task. */
rgrover1 362:6fa0d4d555f6 1003 __I uint32_t RESERVED5[684];
rgrover1 362:6fa0d4d555f6 1004 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 362:6fa0d4d555f6 1005 } NRF_QDEC_Type;
rgrover1 362:6fa0d4d555f6 1006
rgrover1 362:6fa0d4d555f6 1007
rgrover1 362:6fa0d4d555f6 1008 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 1009 /* ================ LPCOMP ================ */
rgrover1 362:6fa0d4d555f6 1010 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 1011
rgrover1 362:6fa0d4d555f6 1012
rgrover1 362:6fa0d4d555f6 1013 /**
rgrover1 362:6fa0d4d555f6 1014 * @brief Low power comparator. (LPCOMP)
rgrover1 362:6fa0d4d555f6 1015 */
rgrover1 362:6fa0d4d555f6 1016
rgrover1 362:6fa0d4d555f6 1017 typedef struct { /*!< LPCOMP Structure */
rgrover1 362:6fa0d4d555f6 1018 __O uint32_t TASKS_START; /*!< Start the comparator. */
rgrover1 362:6fa0d4d555f6 1019 __O uint32_t TASKS_STOP; /*!< Stop the comparator. */
rgrover1 362:6fa0d4d555f6 1020 __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value. */
rgrover1 362:6fa0d4d555f6 1021 __I uint32_t RESERVED0[61];
rgrover1 362:6fa0d4d555f6 1022 __IO uint32_t EVENTS_READY; /*!< LPCOMP is ready and output is valid. */
rgrover1 362:6fa0d4d555f6 1023 __IO uint32_t EVENTS_DOWN; /*!< Input voltage crossed the threshold going down. */
rgrover1 362:6fa0d4d555f6 1024 __IO uint32_t EVENTS_UP; /*!< Input voltage crossed the threshold going up. */
rgrover1 362:6fa0d4d555f6 1025 __IO uint32_t EVENTS_CROSS; /*!< Input voltage crossed the threshold in any direction. */
rgrover1 362:6fa0d4d555f6 1026 __I uint32_t RESERVED1[60];
rgrover1 362:6fa0d4d555f6 1027 __IO uint32_t SHORTS; /*!< Shortcuts for the LPCOMP. */
rgrover1 362:6fa0d4d555f6 1028 __I uint32_t RESERVED2[64];
rgrover1 362:6fa0d4d555f6 1029 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 362:6fa0d4d555f6 1030 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 362:6fa0d4d555f6 1031 __I uint32_t RESERVED3[61];
rgrover1 362:6fa0d4d555f6 1032 __I uint32_t RESULT; /*!< Result of last compare. */
rgrover1 362:6fa0d4d555f6 1033 __I uint32_t RESERVED4[63];
rgrover1 362:6fa0d4d555f6 1034 __IO uint32_t ENABLE; /*!< Enable the LPCOMP. */
rgrover1 362:6fa0d4d555f6 1035 __IO uint32_t PSEL; /*!< Input pin select. */
rgrover1 362:6fa0d4d555f6 1036 __IO uint32_t REFSEL; /*!< Reference select. */
rgrover1 362:6fa0d4d555f6 1037 __IO uint32_t EXTREFSEL; /*!< External reference select. */
rgrover1 362:6fa0d4d555f6 1038 __I uint32_t RESERVED5[4];
rgrover1 362:6fa0d4d555f6 1039 __IO uint32_t ANADETECT; /*!< Analog detect configuration. */
rgrover1 362:6fa0d4d555f6 1040 __I uint32_t RESERVED6[694];
rgrover1 362:6fa0d4d555f6 1041 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 362:6fa0d4d555f6 1042 } NRF_LPCOMP_Type;
rgrover1 362:6fa0d4d555f6 1043
rgrover1 362:6fa0d4d555f6 1044
rgrover1 362:6fa0d4d555f6 1045 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 1046 /* ================ SWI ================ */
rgrover1 362:6fa0d4d555f6 1047 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 1048
rgrover1 362:6fa0d4d555f6 1049
rgrover1 362:6fa0d4d555f6 1050 /**
rgrover1 362:6fa0d4d555f6 1051 * @brief SW Interrupts. (SWI)
rgrover1 362:6fa0d4d555f6 1052 */
rgrover1 362:6fa0d4d555f6 1053
rgrover1 362:6fa0d4d555f6 1054 typedef struct { /*!< SWI Structure */
rgrover1 362:6fa0d4d555f6 1055 __I uint32_t UNUSED; /*!< Unused. */
rgrover1 362:6fa0d4d555f6 1056 } NRF_SWI_Type;
rgrover1 362:6fa0d4d555f6 1057
rgrover1 362:6fa0d4d555f6 1058
rgrover1 362:6fa0d4d555f6 1059 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 1060 /* ================ NVMC ================ */
rgrover1 362:6fa0d4d555f6 1061 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 1062
rgrover1 362:6fa0d4d555f6 1063
rgrover1 362:6fa0d4d555f6 1064 /**
rgrover1 362:6fa0d4d555f6 1065 * @brief Non Volatile Memory Controller. (NVMC)
rgrover1 362:6fa0d4d555f6 1066 */
rgrover1 362:6fa0d4d555f6 1067
rgrover1 362:6fa0d4d555f6 1068 typedef struct { /*!< NVMC Structure */
rgrover1 362:6fa0d4d555f6 1069 __I uint32_t RESERVED0[256];
rgrover1 362:6fa0d4d555f6 1070 __I uint32_t READY; /*!< Ready flag. */
rgrover1 362:6fa0d4d555f6 1071 __I uint32_t RESERVED1[64];
rgrover1 362:6fa0d4d555f6 1072 __IO uint32_t CONFIG; /*!< Configuration register. */
rgrover1 362:6fa0d4d555f6 1073 __IO uint32_t ERASEPAGE; /*!< Register for erasing a non-protected non-volatile memory page. */
rgrover1 362:6fa0d4d555f6 1074 __IO uint32_t ERASEALL; /*!< Register for erasing all non-volatile user memory. */
rgrover1 362:6fa0d4d555f6 1075 __IO uint32_t ERASEPROTECTEDPAGE; /*!< Register for erasing a protected non-volatile memory page. */
rgrover1 362:6fa0d4d555f6 1076 __IO uint32_t ERASEUICR; /*!< Register for start erasing User Information Congfiguration Registers. */
rgrover1 362:6fa0d4d555f6 1077 } NRF_NVMC_Type;
rgrover1 362:6fa0d4d555f6 1078
rgrover1 362:6fa0d4d555f6 1079
rgrover1 362:6fa0d4d555f6 1080 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 1081 /* ================ PPI ================ */
rgrover1 362:6fa0d4d555f6 1082 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 1083
rgrover1 362:6fa0d4d555f6 1084
rgrover1 362:6fa0d4d555f6 1085 /**
rgrover1 362:6fa0d4d555f6 1086 * @brief PPI controller. (PPI)
rgrover1 362:6fa0d4d555f6 1087 */
rgrover1 362:6fa0d4d555f6 1088
rgrover1 362:6fa0d4d555f6 1089 typedef struct { /*!< PPI Structure */
rgrover1 362:6fa0d4d555f6 1090 PPI_TASKS_CHG_Type TASKS_CHG[4]; /*!< Channel group tasks. */
rgrover1 362:6fa0d4d555f6 1091 __I uint32_t RESERVED0[312];
rgrover1 362:6fa0d4d555f6 1092 __IO uint32_t CHEN; /*!< Channel enable. */
rgrover1 362:6fa0d4d555f6 1093 __IO uint32_t CHENSET; /*!< Channel enable set. */
rgrover1 362:6fa0d4d555f6 1094 __IO uint32_t CHENCLR; /*!< Channel enable clear. */
rgrover1 362:6fa0d4d555f6 1095 __I uint32_t RESERVED1;
rgrover1 362:6fa0d4d555f6 1096 PPI_CH_Type CH[16]; /*!< PPI Channel. */
rgrover1 362:6fa0d4d555f6 1097 __I uint32_t RESERVED2[156];
rgrover1 362:6fa0d4d555f6 1098 __IO uint32_t CHG[4]; /*!< Channel group configuration. */
rgrover1 362:6fa0d4d555f6 1099 } NRF_PPI_Type;
rgrover1 362:6fa0d4d555f6 1100
rgrover1 362:6fa0d4d555f6 1101
rgrover1 362:6fa0d4d555f6 1102 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 1103 /* ================ FICR ================ */
rgrover1 362:6fa0d4d555f6 1104 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 1105
rgrover1 362:6fa0d4d555f6 1106
rgrover1 362:6fa0d4d555f6 1107 /**
rgrover1 362:6fa0d4d555f6 1108 * @brief Factory Information Configuration. (FICR)
rgrover1 362:6fa0d4d555f6 1109 */
rgrover1 362:6fa0d4d555f6 1110
rgrover1 362:6fa0d4d555f6 1111 typedef struct { /*!< FICR Structure */
rgrover1 362:6fa0d4d555f6 1112 __I uint32_t RESERVED0[4];
rgrover1 362:6fa0d4d555f6 1113 __I uint32_t CODEPAGESIZE; /*!< Code memory page size in bytes. */
rgrover1 362:6fa0d4d555f6 1114 __I uint32_t CODESIZE; /*!< Code memory size in pages. */
rgrover1 362:6fa0d4d555f6 1115 __I uint32_t RESERVED1[4];
rgrover1 362:6fa0d4d555f6 1116 __I uint32_t CLENR0; /*!< Length of code region 0 in bytes. */
rgrover1 362:6fa0d4d555f6 1117 __I uint32_t PPFC; /*!< Pre-programmed factory code present. */
rgrover1 362:6fa0d4d555f6 1118 __I uint32_t RESERVED2;
rgrover1 362:6fa0d4d555f6 1119 __I uint32_t NUMRAMBLOCK; /*!< Number of individualy controllable RAM blocks. */
rgrover1 362:6fa0d4d555f6 1120
rgrover1 362:6fa0d4d555f6 1121 union {
rgrover1 362:6fa0d4d555f6 1122 __I uint32_t SIZERAMBLOCK[4]; /*!< Deprecated array of size of RAM block in bytes. This name is
rgrover1 362:6fa0d4d555f6 1123 kept for backward compatinility purposes. Use SIZERAMBLOCKS
rgrover1 362:6fa0d4d555f6 1124 instead. */
rgrover1 362:6fa0d4d555f6 1125 __I uint32_t SIZERAMBLOCKS; /*!< Size of RAM blocks in bytes. */
rgrover1 362:6fa0d4d555f6 1126 };
rgrover1 362:6fa0d4d555f6 1127 __I uint32_t RESERVED3[5];
rgrover1 362:6fa0d4d555f6 1128 __I uint32_t CONFIGID; /*!< Configuration identifier. */
rgrover1 362:6fa0d4d555f6 1129 __I uint32_t DEVICEID[2]; /*!< Device identifier. */
rgrover1 362:6fa0d4d555f6 1130 __I uint32_t RESERVED4[6];
rgrover1 362:6fa0d4d555f6 1131 __I uint32_t ER[4]; /*!< Encryption root. */
rgrover1 362:6fa0d4d555f6 1132 __I uint32_t IR[4]; /*!< Identity root. */
rgrover1 362:6fa0d4d555f6 1133 __I uint32_t DEVICEADDRTYPE; /*!< Device address type. */
rgrover1 362:6fa0d4d555f6 1134 __I uint32_t DEVICEADDR[2]; /*!< Device address. */
rgrover1 362:6fa0d4d555f6 1135 __I uint32_t OVERRIDEEN; /*!< Radio calibration override enable. */
rgrover1 362:6fa0d4d555f6 1136 __I uint32_t NRF_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for NRF_1Mbit
rgrover1 362:6fa0d4d555f6 1137 mode. */
rgrover1 362:6fa0d4d555f6 1138 __I uint32_t RESERVED5[10];
rgrover1 362:6fa0d4d555f6 1139 __I uint32_t BLE_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit
rgrover1 362:6fa0d4d555f6 1140 mode. */
rgrover1 362:6fa0d4d555f6 1141 FICR_INFO_Type INFO; /*!< Device info */
rgrover1 362:6fa0d4d555f6 1142 } NRF_FICR_Type;
rgrover1 362:6fa0d4d555f6 1143
rgrover1 362:6fa0d4d555f6 1144
rgrover1 362:6fa0d4d555f6 1145 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 1146 /* ================ UICR ================ */
rgrover1 362:6fa0d4d555f6 1147 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 1148
rgrover1 362:6fa0d4d555f6 1149
rgrover1 362:6fa0d4d555f6 1150 /**
rgrover1 362:6fa0d4d555f6 1151 * @brief User Information Configuration. (UICR)
rgrover1 362:6fa0d4d555f6 1152 */
rgrover1 362:6fa0d4d555f6 1153
rgrover1 362:6fa0d4d555f6 1154 typedef struct { /*!< UICR Structure */
rgrover1 362:6fa0d4d555f6 1155 __IO uint32_t CLENR0; /*!< Length of code region 0. */
rgrover1 362:6fa0d4d555f6 1156 __IO uint32_t RBPCONF; /*!< Readback protection configuration. */
rgrover1 362:6fa0d4d555f6 1157 __IO uint32_t XTALFREQ; /*!< Reset value for CLOCK XTALFREQ register. */
rgrover1 362:6fa0d4d555f6 1158 __I uint32_t RESERVED0;
rgrover1 362:6fa0d4d555f6 1159 __I uint32_t FWID; /*!< Firmware ID. */
rgrover1 362:6fa0d4d555f6 1160 __IO uint32_t BOOTLOADERADDR; /*!< Bootloader start address. */
rgrover1 362:6fa0d4d555f6 1161 } NRF_UICR_Type;
rgrover1 362:6fa0d4d555f6 1162
rgrover1 362:6fa0d4d555f6 1163
rgrover1 362:6fa0d4d555f6 1164 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 1165 /* ================ GPIO ================ */
rgrover1 362:6fa0d4d555f6 1166 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 1167
rgrover1 362:6fa0d4d555f6 1168
rgrover1 362:6fa0d4d555f6 1169 /**
rgrover1 362:6fa0d4d555f6 1170 * @brief General purpose input and output. (GPIO)
rgrover1 362:6fa0d4d555f6 1171 */
rgrover1 362:6fa0d4d555f6 1172
rgrover1 362:6fa0d4d555f6 1173 typedef struct { /*!< GPIO Structure */
rgrover1 362:6fa0d4d555f6 1174 __I uint32_t RESERVED0[321];
rgrover1 362:6fa0d4d555f6 1175 __IO uint32_t OUT; /*!< Write GPIO port. */
rgrover1 362:6fa0d4d555f6 1176 __IO uint32_t OUTSET; /*!< Set individual bits in GPIO port. */
rgrover1 362:6fa0d4d555f6 1177 __IO uint32_t OUTCLR; /*!< Clear individual bits in GPIO port. */
rgrover1 362:6fa0d4d555f6 1178 __I uint32_t IN; /*!< Read GPIO port. */
rgrover1 362:6fa0d4d555f6 1179 __IO uint32_t DIR; /*!< Direction of GPIO pins. */
rgrover1 362:6fa0d4d555f6 1180 __IO uint32_t DIRSET; /*!< DIR set register. */
rgrover1 362:6fa0d4d555f6 1181 __IO uint32_t DIRCLR; /*!< DIR clear register. */
rgrover1 362:6fa0d4d555f6 1182 __I uint32_t RESERVED1[120];
rgrover1 362:6fa0d4d555f6 1183 __IO uint32_t PIN_CNF[32]; /*!< Configuration of GPIO pins. */
rgrover1 362:6fa0d4d555f6 1184 } NRF_GPIO_Type;
rgrover1 362:6fa0d4d555f6 1185
rgrover1 362:6fa0d4d555f6 1186
rgrover1 362:6fa0d4d555f6 1187 /* -------------------- End of section using anonymous unions ------------------- */
rgrover1 362:6fa0d4d555f6 1188 #if defined(__CC_ARM)
rgrover1 362:6fa0d4d555f6 1189 #pragma pop
rgrover1 362:6fa0d4d555f6 1190 #elif defined(__ICCARM__)
rgrover1 362:6fa0d4d555f6 1191 /* leave anonymous unions enabled */
rgrover1 362:6fa0d4d555f6 1192 #elif defined(__GNUC__)
rgrover1 362:6fa0d4d555f6 1193 /* anonymous unions are enabled by default */
rgrover1 362:6fa0d4d555f6 1194 #elif defined(__TMS470__)
rgrover1 362:6fa0d4d555f6 1195 /* anonymous unions are enabled by default */
rgrover1 362:6fa0d4d555f6 1196 #elif defined(__TASKING__)
rgrover1 362:6fa0d4d555f6 1197 #pragma warning restore
rgrover1 362:6fa0d4d555f6 1198 #else
rgrover1 362:6fa0d4d555f6 1199 #warning Not supported compiler type
rgrover1 362:6fa0d4d555f6 1200 #endif
rgrover1 362:6fa0d4d555f6 1201
rgrover1 362:6fa0d4d555f6 1202
rgrover1 362:6fa0d4d555f6 1203
rgrover1 362:6fa0d4d555f6 1204
rgrover1 362:6fa0d4d555f6 1205 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 1206 /* ================ Peripheral memory map ================ */
rgrover1 362:6fa0d4d555f6 1207 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 1208
rgrover1 362:6fa0d4d555f6 1209 #define NRF_POWER_BASE 0x40000000UL
rgrover1 362:6fa0d4d555f6 1210 #define NRF_CLOCK_BASE 0x40000000UL
rgrover1 362:6fa0d4d555f6 1211 #define NRF_MPU_BASE 0x40000000UL
rgrover1 362:6fa0d4d555f6 1212 #define NRF_PU_BASE 0x40000000UL
rgrover1 362:6fa0d4d555f6 1213 #define NRF_AMLI_BASE 0x40000000UL
rgrover1 362:6fa0d4d555f6 1214 #define NRF_RADIO_BASE 0x40001000UL
rgrover1 362:6fa0d4d555f6 1215 #define NRF_UART0_BASE 0x40002000UL
rgrover1 362:6fa0d4d555f6 1216 #define NRF_SPI0_BASE 0x40003000UL
rgrover1 362:6fa0d4d555f6 1217 #define NRF_TWI0_BASE 0x40003000UL
rgrover1 362:6fa0d4d555f6 1218 #define NRF_SPI1_BASE 0x40004000UL
rgrover1 362:6fa0d4d555f6 1219 #define NRF_TWI1_BASE 0x40004000UL
rgrover1 362:6fa0d4d555f6 1220 #define NRF_SPIS1_BASE 0x40004000UL
rgrover1 362:6fa0d4d555f6 1221 #define NRF_SPIM1_BASE 0x40004000UL
rgrover1 362:6fa0d4d555f6 1222 #define NRF_GPIOTE_BASE 0x40006000UL
rgrover1 362:6fa0d4d555f6 1223 #define NRF_ADC_BASE 0x40007000UL
rgrover1 362:6fa0d4d555f6 1224 #define NRF_TIMER0_BASE 0x40008000UL
rgrover1 362:6fa0d4d555f6 1225 #define NRF_TIMER1_BASE 0x40009000UL
rgrover1 362:6fa0d4d555f6 1226 #define NRF_TIMER2_BASE 0x4000A000UL
rgrover1 362:6fa0d4d555f6 1227 #define NRF_RTC0_BASE 0x4000B000UL
rgrover1 362:6fa0d4d555f6 1228 #define NRF_TEMP_BASE 0x4000C000UL
rgrover1 362:6fa0d4d555f6 1229 #define NRF_RNG_BASE 0x4000D000UL
rgrover1 362:6fa0d4d555f6 1230 #define NRF_ECB_BASE 0x4000E000UL
rgrover1 362:6fa0d4d555f6 1231 #define NRF_AAR_BASE 0x4000F000UL
rgrover1 362:6fa0d4d555f6 1232 #define NRF_CCM_BASE 0x4000F000UL
rgrover1 362:6fa0d4d555f6 1233 #define NRF_WDT_BASE 0x40010000UL
rgrover1 362:6fa0d4d555f6 1234 #define NRF_RTC1_BASE 0x40011000UL
rgrover1 362:6fa0d4d555f6 1235 #define NRF_QDEC_BASE 0x40012000UL
rgrover1 362:6fa0d4d555f6 1236 #define NRF_LPCOMP_BASE 0x40013000UL
rgrover1 362:6fa0d4d555f6 1237 #define NRF_SWI_BASE 0x40014000UL
rgrover1 362:6fa0d4d555f6 1238 #define NRF_NVMC_BASE 0x4001E000UL
rgrover1 362:6fa0d4d555f6 1239 #define NRF_PPI_BASE 0x4001F000UL
rgrover1 362:6fa0d4d555f6 1240 #define NRF_FICR_BASE 0x10000000UL
rgrover1 362:6fa0d4d555f6 1241 #define NRF_UICR_BASE 0x10001000UL
rgrover1 362:6fa0d4d555f6 1242 #define NRF_GPIO_BASE 0x50000000UL
rgrover1 362:6fa0d4d555f6 1243
rgrover1 362:6fa0d4d555f6 1244
rgrover1 362:6fa0d4d555f6 1245 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 1246 /* ================ Peripheral declaration ================ */
rgrover1 362:6fa0d4d555f6 1247 /* ================================================================================ */
rgrover1 362:6fa0d4d555f6 1248
rgrover1 362:6fa0d4d555f6 1249 #define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE)
rgrover1 362:6fa0d4d555f6 1250 #define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE)
rgrover1 362:6fa0d4d555f6 1251 #define NRF_MPU ((NRF_MPU_Type *) NRF_MPU_BASE)
rgrover1 362:6fa0d4d555f6 1252 #define NRF_PU ((NRF_PU_Type *) NRF_PU_BASE)
rgrover1 362:6fa0d4d555f6 1253 #define NRF_AMLI ((NRF_AMLI_Type *) NRF_AMLI_BASE)
rgrover1 362:6fa0d4d555f6 1254 #define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE)
rgrover1 362:6fa0d4d555f6 1255 #define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE)
rgrover1 362:6fa0d4d555f6 1256 #define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE)
rgrover1 362:6fa0d4d555f6 1257 #define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE)
rgrover1 362:6fa0d4d555f6 1258 #define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE)
rgrover1 362:6fa0d4d555f6 1259 #define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE)
rgrover1 362:6fa0d4d555f6 1260 #define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE)
rgrover1 362:6fa0d4d555f6 1261 #define NRF_SPIM1 ((NRF_SPIM_Type *) NRF_SPIM1_BASE)
rgrover1 362:6fa0d4d555f6 1262 #define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE)
rgrover1 362:6fa0d4d555f6 1263 #define NRF_ADC ((NRF_ADC_Type *) NRF_ADC_BASE)
rgrover1 362:6fa0d4d555f6 1264 #define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE)
rgrover1 362:6fa0d4d555f6 1265 #define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE)
rgrover1 362:6fa0d4d555f6 1266 #define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE)
rgrover1 362:6fa0d4d555f6 1267 #define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE)
rgrover1 362:6fa0d4d555f6 1268 #define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE)
rgrover1 362:6fa0d4d555f6 1269 #define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE)
rgrover1 362:6fa0d4d555f6 1270 #define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE)
rgrover1 362:6fa0d4d555f6 1271 #define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE)
rgrover1 362:6fa0d4d555f6 1272 #define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE)
rgrover1 362:6fa0d4d555f6 1273 #define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE)
rgrover1 362:6fa0d4d555f6 1274 #define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE)
rgrover1 362:6fa0d4d555f6 1275 #define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE)
rgrover1 362:6fa0d4d555f6 1276 #define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE)
rgrover1 362:6fa0d4d555f6 1277 #define NRF_SWI ((NRF_SWI_Type *) NRF_SWI_BASE)
rgrover1 362:6fa0d4d555f6 1278 #define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE)
rgrover1 362:6fa0d4d555f6 1279 #define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE)
rgrover1 362:6fa0d4d555f6 1280 #define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE)
rgrover1 362:6fa0d4d555f6 1281 #define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE)
rgrover1 362:6fa0d4d555f6 1282 #define NRF_GPIO ((NRF_GPIO_Type *) NRF_GPIO_BASE)
rgrover1 362:6fa0d4d555f6 1283
rgrover1 362:6fa0d4d555f6 1284
rgrover1 362:6fa0d4d555f6 1285 /** @} */ /* End of group Device_Peripheral_Registers */
rgrover1 362:6fa0d4d555f6 1286 /** @} */ /* End of group nRF51 */
rgrover1 362:6fa0d4d555f6 1287 /** @} */ /* End of group Nordic Semiconductor */
rgrover1 362:6fa0d4d555f6 1288
rgrover1 362:6fa0d4d555f6 1289 #ifdef __cplusplus
rgrover1 362:6fa0d4d555f6 1290 }
rgrover1 362:6fa0d4d555f6 1291 #endif
rgrover1 362:6fa0d4d555f6 1292
rgrover1 362:6fa0d4d555f6 1293
rgrover1 362:6fa0d4d555f6 1294 #endif /* nRF51_H */