Rob Kluin / nRF51822

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Fork of nRF51822 by Nordic Semiconductor

nordic-sdk/components/drivers_nrf/hal/nrf51.h@361:d2405f5a4853, 2015-07-02 (annotated)

Committer:
rgrover1
Date:
Thu Jul 02 09:08:44 2015 +0100
Revision:
361:d2405f5a4853
Parent:
346:14b090482fd2
Child:
362:6fa0d4d555f6
Synchronized with git rev 9f72c4ba

Author: Rohit Grover

Release 0.3.7

=============



This is a minor set of enhancements mostly around reduce our global static

memory footprint.



Enhancements

~~~~~~~~~~~~



* Reduce the maximum number of CHARACTERISTICS and DESCRIPTORS that can be

  handled. This has memory implications for static global memory. It should

  be possible to re-architect our solution for add_characteristic() to not

  require these limits; hopefully we'll get there soon.



* Move nRF51GattServer::getInstance() into a .cpp file; same for nRF51Gap::getInstance().



* Reduce max bonds to managed by device-manager to 4; this has memory implications for static global memory.



* Reduce pStorage command queue size to 2; this has memory implications for static global memory.



* Replace uses of deprecated Gap::addr_type_t with Gap::AddressType_t.



* Some UUID-related types have moved into UUID class. Minor changes were needed to work around build errors.



Bugfixes

~~~~~~~~



* None.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
rgrover1 361:d2405f5a4853 1
rgrover1 361:d2405f5a4853 2 /****************************************************************************************************//**
rgrover1 361:d2405f5a4853 3 * @file nRF51.h
rgrover1 361:d2405f5a4853 4 *
rgrover1 361:d2405f5a4853 5 * @brief CMSIS Cortex-M0 Peripheral Access Layer Header File for
rgrover1 361:d2405f5a4853 6 * nRF51 from Nordic Semiconductor.
rgrover1 361:d2405f5a4853 7 *
rgrover1 361:d2405f5a4853 8 * @version V522
rgrover1 361:d2405f5a4853 9 * @date 31. October 2014
rgrover1 361:d2405f5a4853 10 *
rgrover1 361:d2405f5a4853 11 * @note Generated with SVDConv V2.81d
rgrover1 361:d2405f5a4853 12 * from CMSIS SVD File 'nRF51.xml' Version 522,
rgrover1 361:d2405f5a4853 13 *
rgrover1 361:d2405f5a4853 14 * @par Copyright (c) 2013, Nordic Semiconductor ASA
rgrover1 361:d2405f5a4853 15 * All rights reserved.
rgrover1 361:d2405f5a4853 16 *
rgrover1 361:d2405f5a4853 17 * Redistribution and use in source and binary forms, with or without
rgrover1 361:d2405f5a4853 18 * modification, are permitted provided that the following conditions are met:
rgrover1 361:d2405f5a4853 19 *
rgrover1 361:d2405f5a4853 20 * * Redistributions of source code must retain the above copyright notice, this
rgrover1 361:d2405f5a4853 21 * list of conditions and the following disclaimer.
rgrover1 361:d2405f5a4853 22 *
rgrover1 361:d2405f5a4853 23 * * Redistributions in binary form must reproduce the above copyright notice,
rgrover1 361:d2405f5a4853 24 * this list of conditions and the following disclaimer in the documentation
rgrover1 361:d2405f5a4853 25 * and/or other materials provided with the distribution.
rgrover1 361:d2405f5a4853 26 *
rgrover1 361:d2405f5a4853 27 * * Neither the name of Nordic Semiconductor ASA nor the names of its
rgrover1 361:d2405f5a4853 28 * contributors may be used to endorse or promote products derived from
rgrover1 361:d2405f5a4853 29 * this software without specific prior written permission.
rgrover1 361:d2405f5a4853 30 *
rgrover1 361:d2405f5a4853 31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
rgrover1 361:d2405f5a4853 32 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
rgrover1 361:d2405f5a4853 33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
rgrover1 361:d2405f5a4853 34 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
rgrover1 361:d2405f5a4853 35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
rgrover1 361:d2405f5a4853 36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
rgrover1 361:d2405f5a4853 37 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
rgrover1 361:d2405f5a4853 38 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
rgrover1 361:d2405f5a4853 39 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
rgrover1 361:d2405f5a4853 40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
rgrover1 361:d2405f5a4853 41 *
rgrover1 361:d2405f5a4853 42 *
rgrover1 361:d2405f5a4853 43 *******************************************************************************************************/
rgrover1 361:d2405f5a4853 44
rgrover1 361:d2405f5a4853 45
rgrover1 361:d2405f5a4853 46
rgrover1 361:d2405f5a4853 47 /** @addtogroup Nordic Semiconductor
rgrover1 361:d2405f5a4853 48 * @{
rgrover1 361:d2405f5a4853 49 */
rgrover1 361:d2405f5a4853 50
rgrover1 361:d2405f5a4853 51 /** @addtogroup nRF51
rgrover1 361:d2405f5a4853 52 * @{
rgrover1 361:d2405f5a4853 53 */
rgrover1 361:d2405f5a4853 54
rgrover1 361:d2405f5a4853 55 #ifndef NRF51_H
rgrover1 361:d2405f5a4853 56 #define NRF51_H
rgrover1 361:d2405f5a4853 57
rgrover1 361:d2405f5a4853 58 #ifdef __cplusplus
rgrover1 361:d2405f5a4853 59 extern "C" {
rgrover1 361:d2405f5a4853 60 #endif
rgrover1 361:d2405f5a4853 61
rgrover1 361:d2405f5a4853 62
rgrover1 361:d2405f5a4853 63 /* ------------------------- Interrupt Number Definition ------------------------ */
rgrover1 361:d2405f5a4853 64
rgrover1 361:d2405f5a4853 65 typedef enum {
rgrover1 361:d2405f5a4853 66 /* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
rgrover1 361:d2405f5a4853 67 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
rgrover1 361:d2405f5a4853 68 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
rgrover1 361:d2405f5a4853 69 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
rgrover1 361:d2405f5a4853 70 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
rgrover1 361:d2405f5a4853 71 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
rgrover1 361:d2405f5a4853 72 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
rgrover1 361:d2405f5a4853 73 SysTick_IRQn = -1, /*!< 15 System Tick Timer */
rgrover1 361:d2405f5a4853 74 /* ---------------------- nRF51 Specific Interrupt Numbers ---------------------- */
rgrover1 361:d2405f5a4853 75 POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */
rgrover1 361:d2405f5a4853 76 RADIO_IRQn = 1, /*!< 1 RADIO */
rgrover1 361:d2405f5a4853 77 UART0_IRQn = 2, /*!< 2 UART0 */
rgrover1 361:d2405f5a4853 78 SPI0_TWI0_IRQn = 3, /*!< 3 SPI0_TWI0 */
rgrover1 361:d2405f5a4853 79 SPI1_TWI1_IRQn = 4, /*!< 4 SPI1_TWI1 */
rgrover1 361:d2405f5a4853 80 GPIOTE_IRQn = 6, /*!< 6 GPIOTE */
rgrover1 361:d2405f5a4853 81 ADC_IRQn = 7, /*!< 7 ADC */
rgrover1 361:d2405f5a4853 82 TIMER0_IRQn = 8, /*!< 8 TIMER0 */
rgrover1 361:d2405f5a4853 83 TIMER1_IRQn = 9, /*!< 9 TIMER1 */
rgrover1 361:d2405f5a4853 84 TIMER2_IRQn = 10, /*!< 10 TIMER2 */
rgrover1 361:d2405f5a4853 85 RTC0_IRQn = 11, /*!< 11 RTC0 */
rgrover1 361:d2405f5a4853 86 TEMP_IRQn = 12, /*!< 12 TEMP */
rgrover1 361:d2405f5a4853 87 RNG_IRQn = 13, /*!< 13 RNG */
rgrover1 361:d2405f5a4853 88 ECB_IRQn = 14, /*!< 14 ECB */
rgrover1 361:d2405f5a4853 89 CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */
rgrover1 361:d2405f5a4853 90 WDT_IRQn = 16, /*!< 16 WDT */
rgrover1 361:d2405f5a4853 91 RTC1_IRQn = 17, /*!< 17 RTC1 */
rgrover1 361:d2405f5a4853 92 QDEC_IRQn = 18, /*!< 18 QDEC */
rgrover1 361:d2405f5a4853 93 LPCOMP_IRQn = 19, /*!< 19 LPCOMP */
rgrover1 361:d2405f5a4853 94 SWI0_IRQn = 20, /*!< 20 SWI0 */
rgrover1 361:d2405f5a4853 95 SWI1_IRQn = 21, /*!< 21 SWI1 */
rgrover1 361:d2405f5a4853 96 SWI2_IRQn = 22, /*!< 22 SWI2 */
rgrover1 361:d2405f5a4853 97 SWI3_IRQn = 23, /*!< 23 SWI3 */
rgrover1 361:d2405f5a4853 98 SWI4_IRQn = 24, /*!< 24 SWI4 */
rgrover1 361:d2405f5a4853 99 SWI5_IRQn = 25 /*!< 25 SWI5 */
rgrover1 361:d2405f5a4853 100 } IRQn_Type;
rgrover1 361:d2405f5a4853 101
rgrover1 361:d2405f5a4853 102
rgrover1 361:d2405f5a4853 103 /** @addtogroup Configuration_of_CMSIS
rgrover1 361:d2405f5a4853 104 * @{
rgrover1 361:d2405f5a4853 105 */
rgrover1 361:d2405f5a4853 106
rgrover1 361:d2405f5a4853 107
rgrover1 361:d2405f5a4853 108 /* ================================================================================ */
rgrover1 361:d2405f5a4853 109 /* ================ Processor and Core Peripheral Section ================ */
rgrover1 361:d2405f5a4853 110 /* ================================================================================ */
rgrover1 361:d2405f5a4853 111
rgrover1 361:d2405f5a4853 112 /* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */
rgrover1 361:d2405f5a4853 113 #define __CM0_REV 0x0301 /*!< Cortex-M0 Core Revision */
rgrover1 361:d2405f5a4853 114 #define __MPU_PRESENT 0 /*!< MPU present or not */
rgrover1 361:d2405f5a4853 115 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
rgrover1 361:d2405f5a4853 116 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
rgrover1 361:d2405f5a4853 117 /** @} */ /* End of group Configuration_of_CMSIS */
rgrover1 361:d2405f5a4853 118
rgrover1 361:d2405f5a4853 119 #include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */
rgrover1 361:d2405f5a4853 120 #include "system_nrf51.h" /*!< nRF51 System */
rgrover1 361:d2405f5a4853 121
rgrover1 361:d2405f5a4853 122
rgrover1 361:d2405f5a4853 123 /* ================================================================================ */
rgrover1 361:d2405f5a4853 124 /* ================ Device Specific Peripheral Section ================ */
rgrover1 361:d2405f5a4853 125 /* ================================================================================ */
rgrover1 361:d2405f5a4853 126
rgrover1 361:d2405f5a4853 127
rgrover1 361:d2405f5a4853 128 /** @addtogroup Device_Peripheral_Registers
rgrover1 361:d2405f5a4853 129 * @{
rgrover1 361:d2405f5a4853 130 */
rgrover1 361:d2405f5a4853 131
rgrover1 361:d2405f5a4853 132
rgrover1 361:d2405f5a4853 133 /* ------------------- Start of section using anonymous unions ------------------ */
rgrover1 361:d2405f5a4853 134 #if defined(__CC_ARM)
rgrover1 361:d2405f5a4853 135 #pragma push
rgrover1 361:d2405f5a4853 136 #pragma anon_unions
rgrover1 361:d2405f5a4853 137 #elif defined(__ICCARM__)
rgrover1 361:d2405f5a4853 138 #pragma language=extended
rgrover1 361:d2405f5a4853 139 #elif defined(__GNUC__)
rgrover1 361:d2405f5a4853 140 /* anonymous unions are enabled by default */
rgrover1 361:d2405f5a4853 141 #elif defined(__TMS470__)
rgrover1 361:d2405f5a4853 142 /* anonymous unions are enabled by default */
rgrover1 361:d2405f5a4853 143 #elif defined(__TASKING__)
rgrover1 361:d2405f5a4853 144 #pragma warning 586
rgrover1 361:d2405f5a4853 145 #else
rgrover1 361:d2405f5a4853 146 #warning Not supported compiler type
rgrover1 361:d2405f5a4853 147 #endif
rgrover1 361:d2405f5a4853 148
rgrover1 361:d2405f5a4853 149
rgrover1 361:d2405f5a4853 150 typedef struct {
rgrover1 361:d2405f5a4853 151 __IO uint32_t CPU0; /*!< Configurable priority configuration register for CPU0. */
rgrover1 361:d2405f5a4853 152 __IO uint32_t SPIS1; /*!< Configurable priority configuration register for SPIS1. */
rgrover1 361:d2405f5a4853 153 __IO uint32_t RADIO; /*!< Configurable priority configuration register for RADIO. */
rgrover1 361:d2405f5a4853 154 __IO uint32_t ECB; /*!< Configurable priority configuration register for ECB. */
rgrover1 361:d2405f5a4853 155 __IO uint32_t CCM; /*!< Configurable priority configuration register for CCM. */
rgrover1 361:d2405f5a4853 156 __IO uint32_t AAR; /*!< Configurable priority configuration register for AAR. */
rgrover1 361:d2405f5a4853 157 } AMLI_RAMPRI_Type;
rgrover1 361:d2405f5a4853 158
rgrover1 361:d2405f5a4853 159 typedef struct {
rgrover1 361:d2405f5a4853 160 __IO uint32_t SCK; /*!< Pin select for SCK. */
rgrover1 361:d2405f5a4853 161 __IO uint32_t MOSI; /*!< Pin select for MOSI. */
rgrover1 361:d2405f5a4853 162 __IO uint32_t MISO; /*!< Pin select for MISO. */
rgrover1 361:d2405f5a4853 163 } SPIM_PSEL_Type;
rgrover1 361:d2405f5a4853 164
rgrover1 361:d2405f5a4853 165 typedef struct {
rgrover1 361:d2405f5a4853 166 __IO uint32_t PTR; /*!< Data pointer. */
rgrover1 361:d2405f5a4853 167 __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to receive. */
rgrover1 361:d2405f5a4853 168 __I uint32_t AMOUNT; /*!< Number of bytes received in the last transaction. */
rgrover1 361:d2405f5a4853 169 } SPIM_RXD_Type;
rgrover1 361:d2405f5a4853 170
rgrover1 361:d2405f5a4853 171 typedef struct {
rgrover1 361:d2405f5a4853 172 __IO uint32_t PTR; /*!< Data pointer. */
rgrover1 361:d2405f5a4853 173 __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to send. */
rgrover1 361:d2405f5a4853 174 __I uint32_t AMOUNT; /*!< Number of bytes sent in the last transaction. */
rgrover1 361:d2405f5a4853 175 } SPIM_TXD_Type;
rgrover1 361:d2405f5a4853 176
rgrover1 361:d2405f5a4853 177 typedef struct {
rgrover1 361:d2405f5a4853 178 __O uint32_t EN; /*!< Enable channel group. */
rgrover1 361:d2405f5a4853 179 __O uint32_t DIS; /*!< Disable channel group. */
rgrover1 361:d2405f5a4853 180 } PPI_TASKS_CHG_Type;
rgrover1 361:d2405f5a4853 181
rgrover1 361:d2405f5a4853 182 typedef struct {
rgrover1 361:d2405f5a4853 183 __IO uint32_t EEP; /*!< Channel event end-point. */
rgrover1 361:d2405f5a4853 184 __IO uint32_t TEP; /*!< Channel task end-point. */
rgrover1 361:d2405f5a4853 185 } PPI_CH_Type;
rgrover1 361:d2405f5a4853 186
rgrover1 361:d2405f5a4853 187 typedef struct {
rgrover1 361:d2405f5a4853 188 __I uint32_t PART; /*!< Part code */
rgrover1 361:d2405f5a4853 189 __I uint32_t VARIANT; /*!< Part variant */
rgrover1 361:d2405f5a4853 190 __I uint32_t PACKAGE; /*!< Package option */
rgrover1 361:d2405f5a4853 191 __I uint32_t RAM; /*!< RAM variant */
rgrover1 361:d2405f5a4853 192 __I uint32_t FLASH; /*!< Flash variant */
rgrover1 361:d2405f5a4853 193 __I uint32_t RESERVED[3]; /*!< Reserved */
rgrover1 361:d2405f5a4853 194 } FICR_INFO_Type;
rgrover1 361:d2405f5a4853 195
rgrover1 361:d2405f5a4853 196
rgrover1 361:d2405f5a4853 197 /* ================================================================================ */
rgrover1 361:d2405f5a4853 198 /* ================ POWER ================ */
rgrover1 361:d2405f5a4853 199 /* ================================================================================ */
rgrover1 361:d2405f5a4853 200
rgrover1 361:d2405f5a4853 201
rgrover1 361:d2405f5a4853 202 /**
rgrover1 361:d2405f5a4853 203 * @brief Power Control. (POWER)
rgrover1 361:d2405f5a4853 204 */
rgrover1 361:d2405f5a4853 205
rgrover1 361:d2405f5a4853 206 typedef struct { /*!< POWER Structure */
rgrover1 361:d2405f5a4853 207 __I uint32_t RESERVED0[30];
rgrover1 361:d2405f5a4853 208 __O uint32_t TASKS_CONSTLAT; /*!< Enable constant latency mode. */
rgrover1 361:d2405f5a4853 209 __O uint32_t TASKS_LOWPWR; /*!< Enable low power mode (variable latency). */
rgrover1 361:d2405f5a4853 210 __I uint32_t RESERVED1[34];
rgrover1 361:d2405f5a4853 211 __IO uint32_t EVENTS_POFWARN; /*!< Power failure warning. */
rgrover1 361:d2405f5a4853 212 __I uint32_t RESERVED2[126];
rgrover1 361:d2405f5a4853 213 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 361:d2405f5a4853 214 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 361:d2405f5a4853 215 __I uint32_t RESERVED3[61];
rgrover1 361:d2405f5a4853 216 __IO uint32_t RESETREAS; /*!< Reset reason. */
rgrover1 361:d2405f5a4853 217 __I uint32_t RESERVED4[9];
rgrover1 361:d2405f5a4853 218 __I uint32_t RAMSTATUS; /*!< Ram status register. */
rgrover1 361:d2405f5a4853 219 __I uint32_t RESERVED5[53];
rgrover1 361:d2405f5a4853 220 __O uint32_t SYSTEMOFF; /*!< System off register. */
rgrover1 361:d2405f5a4853 221 __I uint32_t RESERVED6[3];
rgrover1 361:d2405f5a4853 222 __IO uint32_t POFCON; /*!< Power failure configuration. */
rgrover1 361:d2405f5a4853 223 __I uint32_t RESERVED7[2];
rgrover1 361:d2405f5a4853 224 __IO uint32_t GPREGRET; /*!< General purpose retention register. This register is a retained
rgrover1 361:d2405f5a4853 225 register. */
rgrover1 361:d2405f5a4853 226 __I uint32_t RESERVED8;
rgrover1 361:d2405f5a4853 227 __IO uint32_t RAMON; /*!< Ram on/off. */
rgrover1 361:d2405f5a4853 228 __I uint32_t RESERVED9[7];
rgrover1 361:d2405f5a4853 229 __IO uint32_t RESET; /*!< Pin reset functionality configuration register. This register
rgrover1 361:d2405f5a4853 230 is a retained register. */
rgrover1 361:d2405f5a4853 231 __I uint32_t RESERVED10[3];
rgrover1 361:d2405f5a4853 232 __IO uint32_t RAMONB; /*!< Ram on/off. */
rgrover1 361:d2405f5a4853 233 __I uint32_t RESERVED11[8];
rgrover1 361:d2405f5a4853 234 __IO uint32_t DCDCEN; /*!< DCDC converter enable configuration register. */
rgrover1 361:d2405f5a4853 235 __I uint32_t RESERVED12[291];
rgrover1 361:d2405f5a4853 236 __IO uint32_t DCDCFORCE; /*!< DCDC power-up force register. */
rgrover1 361:d2405f5a4853 237 } NRF_POWER_Type;
rgrover1 361:d2405f5a4853 238
rgrover1 361:d2405f5a4853 239
rgrover1 361:d2405f5a4853 240 /* ================================================================================ */
rgrover1 361:d2405f5a4853 241 /* ================ CLOCK ================ */
rgrover1 361:d2405f5a4853 242 /* ================================================================================ */
rgrover1 361:d2405f5a4853 243
rgrover1 361:d2405f5a4853 244
rgrover1 361:d2405f5a4853 245 /**
rgrover1 361:d2405f5a4853 246 * @brief Clock control. (CLOCK)
rgrover1 361:d2405f5a4853 247 */
rgrover1 361:d2405f5a4853 248
rgrover1 361:d2405f5a4853 249 typedef struct { /*!< CLOCK Structure */
rgrover1 361:d2405f5a4853 250 __O uint32_t TASKS_HFCLKSTART; /*!< Start HFCLK clock source. */
rgrover1 361:d2405f5a4853 251 __O uint32_t TASKS_HFCLKSTOP; /*!< Stop HFCLK clock source. */
rgrover1 361:d2405f5a4853 252 __O uint32_t TASKS_LFCLKSTART; /*!< Start LFCLK clock source. */
rgrover1 361:d2405f5a4853 253 __O uint32_t TASKS_LFCLKSTOP; /*!< Stop LFCLK clock source. */
rgrover1 361:d2405f5a4853 254 __O uint32_t TASKS_CAL; /*!< Start calibration of LFCLK RC oscillator. */
rgrover1 361:d2405f5a4853 255 __O uint32_t TASKS_CTSTART; /*!< Start calibration timer. */
rgrover1 361:d2405f5a4853 256 __O uint32_t TASKS_CTSTOP; /*!< Stop calibration timer. */
rgrover1 361:d2405f5a4853 257 __I uint32_t RESERVED0[57];
rgrover1 361:d2405f5a4853 258 __IO uint32_t EVENTS_HFCLKSTARTED; /*!< HFCLK oscillator started. */
rgrover1 361:d2405f5a4853 259 __IO uint32_t EVENTS_LFCLKSTARTED; /*!< LFCLK oscillator started. */
rgrover1 361:d2405f5a4853 260 __I uint32_t RESERVED1;
rgrover1 361:d2405f5a4853 261 __IO uint32_t EVENTS_DONE; /*!< Calibration of LFCLK RC oscillator completed. */
rgrover1 361:d2405f5a4853 262 __IO uint32_t EVENTS_CTTO; /*!< Calibration timer timeout. */
rgrover1 361:d2405f5a4853 263 __I uint32_t RESERVED2[124];
rgrover1 361:d2405f5a4853 264 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 361:d2405f5a4853 265 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 361:d2405f5a4853 266 __I uint32_t RESERVED3[63];
rgrover1 361:d2405f5a4853 267 __I uint32_t HFCLKRUN; /*!< Task HFCLKSTART trigger status. */
rgrover1 361:d2405f5a4853 268 __I uint32_t HFCLKSTAT; /*!< High frequency clock status. */
rgrover1 361:d2405f5a4853 269 __I uint32_t RESERVED4;
rgrover1 361:d2405f5a4853 270 __I uint32_t LFCLKRUN; /*!< Task LFCLKSTART triggered status. */
rgrover1 361:d2405f5a4853 271 __I uint32_t LFCLKSTAT; /*!< Low frequency clock status. */
rgrover1 361:d2405f5a4853 272 __I uint32_t LFCLKSRCCOPY; /*!< Clock source for the LFCLK clock, set when task LKCLKSTART is
rgrover1 361:d2405f5a4853 273 triggered. */
rgrover1 361:d2405f5a4853 274 __I uint32_t RESERVED5[62];
rgrover1 361:d2405f5a4853 275 __IO uint32_t LFCLKSRC; /*!< Clock source for the LFCLK clock. */
rgrover1 361:d2405f5a4853 276 __I uint32_t RESERVED6[7];
rgrover1 361:d2405f5a4853 277 __IO uint32_t CTIV; /*!< Calibration timer interval. */
rgrover1 361:d2405f5a4853 278 __I uint32_t RESERVED7[5];
rgrover1 361:d2405f5a4853 279 __IO uint32_t XTALFREQ; /*!< Crystal frequency. */
rgrover1 361:d2405f5a4853 280 } NRF_CLOCK_Type;
rgrover1 361:d2405f5a4853 281
rgrover1 361:d2405f5a4853 282
rgrover1 361:d2405f5a4853 283 /* ================================================================================ */
rgrover1 361:d2405f5a4853 284 /* ================ MPU ================ */
rgrover1 361:d2405f5a4853 285 /* ================================================================================ */
rgrover1 361:d2405f5a4853 286
rgrover1 361:d2405f5a4853 287
rgrover1 361:d2405f5a4853 288 /**
rgrover1 361:d2405f5a4853 289 * @brief Memory Protection Unit. (MPU)
rgrover1 361:d2405f5a4853 290 */
rgrover1 361:d2405f5a4853 291
rgrover1 361:d2405f5a4853 292 typedef struct { /*!< MPU Structure */
rgrover1 361:d2405f5a4853 293 __I uint32_t RESERVED0[330];
rgrover1 361:d2405f5a4853 294 __IO uint32_t PERR0; /*!< Configuration of peripherals in mpu regions. */
rgrover1 361:d2405f5a4853 295 __IO uint32_t RLENR0; /*!< Length of RAM region 0. */
rgrover1 361:d2405f5a4853 296 __I uint32_t RESERVED1[52];
rgrover1 361:d2405f5a4853 297 __IO uint32_t PROTENSET0; /*!< Erase and write protection bit enable set register. */
rgrover1 361:d2405f5a4853 298 __IO uint32_t PROTENSET1; /*!< Erase and write protection bit enable set register. */
rgrover1 361:d2405f5a4853 299 __IO uint32_t DISABLEINDEBUG; /*!< Disable erase and write protection mechanism in debug mode. */
rgrover1 361:d2405f5a4853 300 __IO uint32_t PROTBLOCKSIZE; /*!< Erase and write protection block size. */
rgrover1 361:d2405f5a4853 301 } NRF_MPU_Type;
rgrover1 361:d2405f5a4853 302
rgrover1 361:d2405f5a4853 303
rgrover1 361:d2405f5a4853 304 /* ================================================================================ */
rgrover1 361:d2405f5a4853 305 /* ================ PU ================ */
rgrover1 361:d2405f5a4853 306 /* ================================================================================ */
rgrover1 361:d2405f5a4853 307
rgrover1 361:d2405f5a4853 308
rgrover1 361:d2405f5a4853 309 /**
rgrover1 361:d2405f5a4853 310 * @brief Patch unit. (PU)
rgrover1 361:d2405f5a4853 311 */
rgrover1 361:d2405f5a4853 312
rgrover1 361:d2405f5a4853 313 typedef struct { /*!< PU Structure */
rgrover1 361:d2405f5a4853 314 __I uint32_t RESERVED0[448];
rgrover1 361:d2405f5a4853 315 __IO uint32_t REPLACEADDR[8]; /*!< Address of first instruction to replace. */
rgrover1 361:d2405f5a4853 316 __I uint32_t RESERVED1[24];
rgrover1 361:d2405f5a4853 317 __IO uint32_t PATCHADDR[8]; /*!< Relative address of patch instructions. */
rgrover1 361:d2405f5a4853 318 __I uint32_t RESERVED2[24];
rgrover1 361:d2405f5a4853 319 __IO uint32_t PATCHEN; /*!< Patch enable register. */
rgrover1 361:d2405f5a4853 320 __IO uint32_t PATCHENSET; /*!< Patch enable register. */
rgrover1 361:d2405f5a4853 321 __IO uint32_t PATCHENCLR; /*!< Patch disable register. */
rgrover1 361:d2405f5a4853 322 } NRF_PU_Type;
rgrover1 361:d2405f5a4853 323
rgrover1 361:d2405f5a4853 324
rgrover1 361:d2405f5a4853 325 /* ================================================================================ */
rgrover1 361:d2405f5a4853 326 /* ================ AMLI ================ */
rgrover1 361:d2405f5a4853 327 /* ================================================================================ */
rgrover1 361:d2405f5a4853 328
rgrover1 361:d2405f5a4853 329
rgrover1 361:d2405f5a4853 330 /**
rgrover1 361:d2405f5a4853 331 * @brief AHB Multi-Layer Interface. (AMLI)
rgrover1 361:d2405f5a4853 332 */
rgrover1 361:d2405f5a4853 333
rgrover1 361:d2405f5a4853 334 typedef struct { /*!< AMLI Structure */
rgrover1 361:d2405f5a4853 335 __I uint32_t RESERVED0[896];
rgrover1 361:d2405f5a4853 336 AMLI_RAMPRI_Type RAMPRI; /*!< RAM configurable priority configuration structure. */
rgrover1 361:d2405f5a4853 337 } NRF_AMLI_Type;
rgrover1 361:d2405f5a4853 338
rgrover1 361:d2405f5a4853 339
rgrover1 361:d2405f5a4853 340 /* ================================================================================ */
rgrover1 361:d2405f5a4853 341 /* ================ RADIO ================ */
rgrover1 361:d2405f5a4853 342 /* ================================================================================ */
rgrover1 361:d2405f5a4853 343
rgrover1 361:d2405f5a4853 344
rgrover1 361:d2405f5a4853 345 /**
rgrover1 361:d2405f5a4853 346 * @brief The radio. (RADIO)
rgrover1 361:d2405f5a4853 347 */
rgrover1 361:d2405f5a4853 348
rgrover1 361:d2405f5a4853 349 typedef struct { /*!< RADIO Structure */
rgrover1 361:d2405f5a4853 350 __O uint32_t TASKS_TXEN; /*!< Enable radio in TX mode. */
rgrover1 361:d2405f5a4853 351 __O uint32_t TASKS_RXEN; /*!< Enable radio in RX mode. */
rgrover1 361:d2405f5a4853 352 __O uint32_t TASKS_START; /*!< Start radio. */
rgrover1 361:d2405f5a4853 353 __O uint32_t TASKS_STOP; /*!< Stop radio. */
rgrover1 361:d2405f5a4853 354 __O uint32_t TASKS_DISABLE; /*!< Disable radio. */
rgrover1 361:d2405f5a4853 355 __O uint32_t TASKS_RSSISTART; /*!< Start the RSSI and take one sample of the receive signal strength. */
rgrover1 361:d2405f5a4853 356 __O uint32_t TASKS_RSSISTOP; /*!< Stop the RSSI measurement. */
rgrover1 361:d2405f5a4853 357 __O uint32_t TASKS_BCSTART; /*!< Start the bit counter. */
rgrover1 361:d2405f5a4853 358 __O uint32_t TASKS_BCSTOP; /*!< Stop the bit counter. */
rgrover1 361:d2405f5a4853 359 __I uint32_t RESERVED0[55];
rgrover1 361:d2405f5a4853 360 __IO uint32_t EVENTS_READY; /*!< Ready event. */
rgrover1 361:d2405f5a4853 361 __IO uint32_t EVENTS_ADDRESS; /*!< Address event. */
rgrover1 361:d2405f5a4853 362 __IO uint32_t EVENTS_PAYLOAD; /*!< Payload event. */
rgrover1 361:d2405f5a4853 363 __IO uint32_t EVENTS_END; /*!< End event. */
rgrover1 361:d2405f5a4853 364 __IO uint32_t EVENTS_DISABLED; /*!< Disable event. */
rgrover1 361:d2405f5a4853 365 __IO uint32_t EVENTS_DEVMATCH; /*!< A device address match occurred on the last received packet. */
rgrover1 361:d2405f5a4853 366 __IO uint32_t EVENTS_DEVMISS; /*!< No device address match occurred on the last received packet. */
rgrover1 361:d2405f5a4853 367 __IO uint32_t EVENTS_RSSIEND; /*!< Sampling of the receive signal strength complete. A new RSSI
rgrover1 361:d2405f5a4853 368 sample is ready for readout at the RSSISAMPLE register. */
rgrover1 361:d2405f5a4853 369 __I uint32_t RESERVED1[2];
rgrover1 361:d2405f5a4853 370 __IO uint32_t EVENTS_BCMATCH; /*!< Bit counter reached bit count value specified in BC register. */
rgrover1 361:d2405f5a4853 371 __I uint32_t RESERVED2[53];
rgrover1 361:d2405f5a4853 372 __IO uint32_t SHORTS; /*!< Shortcuts for the radio. */
rgrover1 361:d2405f5a4853 373 __I uint32_t RESERVED3[64];
rgrover1 361:d2405f5a4853 374 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 361:d2405f5a4853 375 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 361:d2405f5a4853 376 __I uint32_t RESERVED4[61];
rgrover1 361:d2405f5a4853 377 __I uint32_t CRCSTATUS; /*!< CRC status of received packet. */
rgrover1 361:d2405f5a4853 378 __I uint32_t CD; /*!< Carrier detect. */
rgrover1 361:d2405f5a4853 379 __I uint32_t RXMATCH; /*!< Received address. */
rgrover1 361:d2405f5a4853 380 __I uint32_t RXCRC; /*!< Received CRC. */
rgrover1 361:d2405f5a4853 381 __I uint32_t DAI; /*!< Device address match index. */
rgrover1 361:d2405f5a4853 382 __I uint32_t RESERVED5[60];
rgrover1 361:d2405f5a4853 383 __IO uint32_t PACKETPTR; /*!< Packet pointer. Decision point: START task. */
rgrover1 361:d2405f5a4853 384 __IO uint32_t FREQUENCY; /*!< Frequency. */
rgrover1 361:d2405f5a4853 385 __IO uint32_t TXPOWER; /*!< Output power. */
rgrover1 361:d2405f5a4853 386 __IO uint32_t MODE; /*!< Data rate and modulation. */
rgrover1 361:d2405f5a4853 387 __IO uint32_t PCNF0; /*!< Packet configuration 0. */
rgrover1 361:d2405f5a4853 388 __IO uint32_t PCNF1; /*!< Packet configuration 1. */
rgrover1 361:d2405f5a4853 389 __IO uint32_t BASE0; /*!< Radio base address 0. Decision point: START task. */
rgrover1 361:d2405f5a4853 390 __IO uint32_t BASE1; /*!< Radio base address 1. Decision point: START task. */
rgrover1 361:d2405f5a4853 391 __IO uint32_t PREFIX0; /*!< Prefixes bytes for logical addresses 0 to 3. */
rgrover1 361:d2405f5a4853 392 __IO uint32_t PREFIX1; /*!< Prefixes bytes for logical addresses 4 to 7. */
rgrover1 361:d2405f5a4853 393 __IO uint32_t TXADDRESS; /*!< Transmit address select. */
rgrover1 361:d2405f5a4853 394 __IO uint32_t RXADDRESSES; /*!< Receive address select. */
rgrover1 361:d2405f5a4853 395 __IO uint32_t CRCCNF; /*!< CRC configuration. */
rgrover1 361:d2405f5a4853 396 __IO uint32_t CRCPOLY; /*!< CRC polynomial. */
rgrover1 361:d2405f5a4853 397 __IO uint32_t CRCINIT; /*!< CRC initial value. */
rgrover1 361:d2405f5a4853 398 __IO uint32_t TEST; /*!< Test features enable register. */
rgrover1 361:d2405f5a4853 399 __IO uint32_t TIFS; /*!< Inter Frame Spacing in microseconds. */
rgrover1 361:d2405f5a4853 400 __I uint32_t RSSISAMPLE; /*!< RSSI sample. */
rgrover1 361:d2405f5a4853 401 __I uint32_t RESERVED6;
rgrover1 361:d2405f5a4853 402 __I uint32_t STATE; /*!< Current radio state. */
rgrover1 361:d2405f5a4853 403 __IO uint32_t DATAWHITEIV; /*!< Data whitening initial value. */
rgrover1 361:d2405f5a4853 404 __I uint32_t RESERVED7[2];
rgrover1 361:d2405f5a4853 405 __IO uint32_t BCC; /*!< Bit counter compare. */
rgrover1 361:d2405f5a4853 406 __I uint32_t RESERVED8[39];
rgrover1 361:d2405f5a4853 407 __IO uint32_t DAB[8]; /*!< Device address base segment. */
rgrover1 361:d2405f5a4853 408 __IO uint32_t DAP[8]; /*!< Device address prefix. */
rgrover1 361:d2405f5a4853 409 __IO uint32_t DACNF; /*!< Device address match configuration. */
rgrover1 361:d2405f5a4853 410 __I uint32_t RESERVED9[56];
rgrover1 361:d2405f5a4853 411 __IO uint32_t OVERRIDE0; /*!< Trim value override register 0. */
rgrover1 361:d2405f5a4853 412 __IO uint32_t OVERRIDE1; /*!< Trim value override register 1. */
rgrover1 361:d2405f5a4853 413 __IO uint32_t OVERRIDE2; /*!< Trim value override register 2. */
rgrover1 361:d2405f5a4853 414 __IO uint32_t OVERRIDE3; /*!< Trim value override register 3. */
rgrover1 361:d2405f5a4853 415 __IO uint32_t OVERRIDE4; /*!< Trim value override register 4. */
rgrover1 361:d2405f5a4853 416 __I uint32_t RESERVED10[561];
rgrover1 361:d2405f5a4853 417 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 361:d2405f5a4853 418 } NRF_RADIO_Type;
rgrover1 361:d2405f5a4853 419
rgrover1 361:d2405f5a4853 420
rgrover1 361:d2405f5a4853 421 /* ================================================================================ */
rgrover1 361:d2405f5a4853 422 /* ================ UART ================ */
rgrover1 361:d2405f5a4853 423 /* ================================================================================ */
rgrover1 361:d2405f5a4853 424
rgrover1 361:d2405f5a4853 425
rgrover1 361:d2405f5a4853 426 /**
rgrover1 361:d2405f5a4853 427 * @brief Universal Asynchronous Receiver/Transmitter. (UART)
rgrover1 361:d2405f5a4853 428 */
rgrover1 361:d2405f5a4853 429
rgrover1 361:d2405f5a4853 430 typedef struct { /*!< UART Structure */
rgrover1 361:d2405f5a4853 431 __O uint32_t TASKS_STARTRX; /*!< Start UART receiver. */
rgrover1 361:d2405f5a4853 432 __O uint32_t TASKS_STOPRX; /*!< Stop UART receiver. */
rgrover1 361:d2405f5a4853 433 __O uint32_t TASKS_STARTTX; /*!< Start UART transmitter. */
rgrover1 361:d2405f5a4853 434 __O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter. */
rgrover1 361:d2405f5a4853 435 __I uint32_t RESERVED0[3];
rgrover1 361:d2405f5a4853 436 __O uint32_t TASKS_SUSPEND; /*!< Suspend UART. */
rgrover1 361:d2405f5a4853 437 __I uint32_t RESERVED1[56];
rgrover1 361:d2405f5a4853 438 __IO uint32_t EVENTS_CTS; /*!< CTS activated. */
rgrover1 361:d2405f5a4853 439 __IO uint32_t EVENTS_NCTS; /*!< CTS deactivated. */
rgrover1 361:d2405f5a4853 440 __IO uint32_t EVENTS_RXDRDY; /*!< Data received in RXD. */
rgrover1 361:d2405f5a4853 441 __I uint32_t RESERVED2[4];
rgrover1 361:d2405f5a4853 442 __IO uint32_t EVENTS_TXDRDY; /*!< Data sent from TXD. */
rgrover1 361:d2405f5a4853 443 __I uint32_t RESERVED3;
rgrover1 361:d2405f5a4853 444 __IO uint32_t EVENTS_ERROR; /*!< Error detected. */
rgrover1 361:d2405f5a4853 445 __I uint32_t RESERVED4[7];
rgrover1 361:d2405f5a4853 446 __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout. */
rgrover1 361:d2405f5a4853 447 __I uint32_t RESERVED5[46];
rgrover1 361:d2405f5a4853 448 __IO uint32_t SHORTS; /*!< Shortcuts for UART. */
rgrover1 361:d2405f5a4853 449 __I uint32_t RESERVED6[64];
rgrover1 361:d2405f5a4853 450 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 361:d2405f5a4853 451 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 361:d2405f5a4853 452 __I uint32_t RESERVED7[93];
rgrover1 361:d2405f5a4853 453 __IO uint32_t ERRORSRC; /*!< Error source. Write error field to 1 to clear error. */
rgrover1 361:d2405f5a4853 454 __I uint32_t RESERVED8[31];
rgrover1 361:d2405f5a4853 455 __IO uint32_t ENABLE; /*!< Enable UART and acquire IOs. */
rgrover1 361:d2405f5a4853 456 __I uint32_t RESERVED9;
rgrover1 361:d2405f5a4853 457 __IO uint32_t PSELRTS; /*!< Pin select for RTS. */
rgrover1 361:d2405f5a4853 458 __IO uint32_t PSELTXD; /*!< Pin select for TXD. */
rgrover1 361:d2405f5a4853 459 __IO uint32_t PSELCTS; /*!< Pin select for CTS. */
rgrover1 361:d2405f5a4853 460 __IO uint32_t PSELRXD; /*!< Pin select for RXD. */
rgrover1 361:d2405f5a4853 461 __I uint32_t RXD; /*!< RXD register. On read action the buffer pointer is displaced.
rgrover1 361:d2405f5a4853 462 Once read the character is consumed. If read when no character
rgrover1 361:d2405f5a4853 463 available, the UART will stop working. */
rgrover1 361:d2405f5a4853 464 __O uint32_t TXD; /*!< TXD register. */
rgrover1 361:d2405f5a4853 465 __I uint32_t RESERVED10;
rgrover1 361:d2405f5a4853 466 __IO uint32_t BAUDRATE; /*!< UART Baudrate. */
rgrover1 361:d2405f5a4853 467 __I uint32_t RESERVED11[17];
rgrover1 361:d2405f5a4853 468 __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control register. */
rgrover1 361:d2405f5a4853 469 __I uint32_t RESERVED12[675];
rgrover1 361:d2405f5a4853 470 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 361:d2405f5a4853 471 } NRF_UART_Type;
rgrover1 361:d2405f5a4853 472
rgrover1 361:d2405f5a4853 473
rgrover1 361:d2405f5a4853 474 /* ================================================================================ */
rgrover1 361:d2405f5a4853 475 /* ================ SPI ================ */
rgrover1 361:d2405f5a4853 476 /* ================================================================================ */
rgrover1 361:d2405f5a4853 477
rgrover1 361:d2405f5a4853 478
rgrover1 361:d2405f5a4853 479 /**
rgrover1 361:d2405f5a4853 480 * @brief SPI master 0. (SPI)
rgrover1 361:d2405f5a4853 481 */
rgrover1 361:d2405f5a4853 482
rgrover1 361:d2405f5a4853 483 typedef struct { /*!< SPI Structure */
rgrover1 361:d2405f5a4853 484 __I uint32_t RESERVED0[66];
rgrover1 361:d2405f5a4853 485 __IO uint32_t EVENTS_READY; /*!< TXD byte sent and RXD byte received. */
rgrover1 361:d2405f5a4853 486 __I uint32_t RESERVED1[126];
rgrover1 361:d2405f5a4853 487 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 361:d2405f5a4853 488 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 361:d2405f5a4853 489 __I uint32_t RESERVED2[125];
rgrover1 361:d2405f5a4853 490 __IO uint32_t ENABLE; /*!< Enable SPI. */
rgrover1 361:d2405f5a4853 491 __I uint32_t RESERVED3;
rgrover1 361:d2405f5a4853 492 __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
rgrover1 361:d2405f5a4853 493 __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
rgrover1 361:d2405f5a4853 494 __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
rgrover1 361:d2405f5a4853 495 __I uint32_t RESERVED4;
rgrover1 361:d2405f5a4853 496 __I uint32_t RXD; /*!< RX data. */
rgrover1 361:d2405f5a4853 497 __IO uint32_t TXD; /*!< TX data. */
rgrover1 361:d2405f5a4853 498 __I uint32_t RESERVED5;
rgrover1 361:d2405f5a4853 499 __IO uint32_t FREQUENCY; /*!< SPI frequency */
rgrover1 361:d2405f5a4853 500 __I uint32_t RESERVED6[11];
rgrover1 361:d2405f5a4853 501 __IO uint32_t CONFIG; /*!< Configuration register. */
rgrover1 361:d2405f5a4853 502 __I uint32_t RESERVED7[681];
rgrover1 361:d2405f5a4853 503 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 361:d2405f5a4853 504 } NRF_SPI_Type;
rgrover1 361:d2405f5a4853 505
rgrover1 361:d2405f5a4853 506
rgrover1 361:d2405f5a4853 507 /* ================================================================================ */
rgrover1 361:d2405f5a4853 508 /* ================ TWI ================ */
rgrover1 361:d2405f5a4853 509 /* ================================================================================ */
rgrover1 361:d2405f5a4853 510
rgrover1 361:d2405f5a4853 511
rgrover1 361:d2405f5a4853 512 /**
rgrover1 361:d2405f5a4853 513 * @brief Two-wire interface master 0. (TWI)
rgrover1 361:d2405f5a4853 514 */
rgrover1 361:d2405f5a4853 515
rgrover1 361:d2405f5a4853 516 typedef struct { /*!< TWI Structure */
rgrover1 361:d2405f5a4853 517 __O uint32_t TASKS_STARTRX; /*!< Start 2-Wire master receive sequence. */
rgrover1 361:d2405f5a4853 518 __I uint32_t RESERVED0;
rgrover1 361:d2405f5a4853 519 __O uint32_t TASKS_STARTTX; /*!< Start 2-Wire master transmit sequence. */
rgrover1 361:d2405f5a4853 520 __I uint32_t RESERVED1[2];
rgrover1 361:d2405f5a4853 521 __O uint32_t TASKS_STOP; /*!< Stop 2-Wire transaction. */
rgrover1 361:d2405f5a4853 522 __I uint32_t RESERVED2;
rgrover1 361:d2405f5a4853 523 __O uint32_t TASKS_SUSPEND; /*!< Suspend 2-Wire transaction. */
rgrover1 361:d2405f5a4853 524 __O uint32_t TASKS_RESUME; /*!< Resume 2-Wire transaction. */
rgrover1 361:d2405f5a4853 525 __I uint32_t RESERVED3[56];
rgrover1 361:d2405f5a4853 526 __IO uint32_t EVENTS_STOPPED; /*!< Two-wire stopped. */
rgrover1 361:d2405f5a4853 527 __IO uint32_t EVENTS_RXDREADY; /*!< Two-wire ready to deliver new RXD byte received. */
rgrover1 361:d2405f5a4853 528 __I uint32_t RESERVED4[4];
rgrover1 361:d2405f5a4853 529 __IO uint32_t EVENTS_TXDSENT; /*!< Two-wire finished sending last TXD byte. */
rgrover1 361:d2405f5a4853 530 __I uint32_t RESERVED5;
rgrover1 361:d2405f5a4853 531 __IO uint32_t EVENTS_ERROR; /*!< Two-wire error detected. */
rgrover1 361:d2405f5a4853 532 __I uint32_t RESERVED6[4];
rgrover1 361:d2405f5a4853 533 __IO uint32_t EVENTS_BB; /*!< Two-wire byte boundary. */
rgrover1 361:d2405f5a4853 534 __I uint32_t RESERVED7[3];
rgrover1 361:d2405f5a4853 535 __IO uint32_t EVENTS_SUSPENDED; /*!< Two-wire suspended. */
rgrover1 361:d2405f5a4853 536 __I uint32_t RESERVED8[45];
rgrover1 361:d2405f5a4853 537 __IO uint32_t SHORTS; /*!< Shortcuts for TWI. */
rgrover1 361:d2405f5a4853 538 __I uint32_t RESERVED9[64];
rgrover1 361:d2405f5a4853 539 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 361:d2405f5a4853 540 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 361:d2405f5a4853 541 __I uint32_t RESERVED10[110];
rgrover1 361:d2405f5a4853 542 __IO uint32_t ERRORSRC; /*!< Two-wire error source. Write error field to 1 to clear error. */
rgrover1 361:d2405f5a4853 543 __I uint32_t RESERVED11[14];
rgrover1 361:d2405f5a4853 544 __IO uint32_t ENABLE; /*!< Enable two-wire master. */
rgrover1 361:d2405f5a4853 545 __I uint32_t RESERVED12;
rgrover1 361:d2405f5a4853 546 __IO uint32_t PSELSCL; /*!< Pin select for SCL. */
rgrover1 361:d2405f5a4853 547 __IO uint32_t PSELSDA; /*!< Pin select for SDA. */
rgrover1 361:d2405f5a4853 548 __I uint32_t RESERVED13[2];
rgrover1 361:d2405f5a4853 549 __I uint32_t RXD; /*!< RX data register. */
rgrover1 361:d2405f5a4853 550 __IO uint32_t TXD; /*!< TX data register. */
rgrover1 361:d2405f5a4853 551 __I uint32_t RESERVED14;
rgrover1 361:d2405f5a4853 552 __IO uint32_t FREQUENCY; /*!< Two-wire frequency. */
rgrover1 361:d2405f5a4853 553 __I uint32_t RESERVED15[24];
rgrover1 361:d2405f5a4853 554 __IO uint32_t ADDRESS; /*!< Address used in the two-wire transfer. */
rgrover1 361:d2405f5a4853 555 __I uint32_t RESERVED16[668];
rgrover1 361:d2405f5a4853 556 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 361:d2405f5a4853 557 } NRF_TWI_Type;
rgrover1 361:d2405f5a4853 558
rgrover1 361:d2405f5a4853 559
rgrover1 361:d2405f5a4853 560 /* ================================================================================ */
rgrover1 361:d2405f5a4853 561 /* ================ SPIS ================ */
rgrover1 361:d2405f5a4853 562 /* ================================================================================ */
rgrover1 361:d2405f5a4853 563
rgrover1 361:d2405f5a4853 564
rgrover1 361:d2405f5a4853 565 /**
rgrover1 361:d2405f5a4853 566 * @brief SPI slave 1. (SPIS)
rgrover1 361:d2405f5a4853 567 */
rgrover1 361:d2405f5a4853 568
rgrover1 361:d2405f5a4853 569 typedef struct { /*!< SPIS Structure */
rgrover1 361:d2405f5a4853 570 __I uint32_t RESERVED0[9];
rgrover1 361:d2405f5a4853 571 __O uint32_t TASKS_ACQUIRE; /*!< Acquire SPI semaphore. */
rgrover1 361:d2405f5a4853 572 __O uint32_t TASKS_RELEASE; /*!< Release SPI semaphore. */
rgrover1 361:d2405f5a4853 573 __I uint32_t RESERVED1[54];
rgrover1 361:d2405f5a4853 574 __IO uint32_t EVENTS_END; /*!< Granted transaction completed. */
rgrover1 361:d2405f5a4853 575 __I uint32_t RESERVED2[8];
rgrover1 361:d2405f5a4853 576 __IO uint32_t EVENTS_ACQUIRED; /*!< Semaphore acquired. */
rgrover1 361:d2405f5a4853 577 __I uint32_t RESERVED3[53];
rgrover1 361:d2405f5a4853 578 __IO uint32_t SHORTS; /*!< Shortcuts for SPIS. */
rgrover1 361:d2405f5a4853 579 __I uint32_t RESERVED4[64];
rgrover1 361:d2405f5a4853 580 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 361:d2405f5a4853 581 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 361:d2405f5a4853 582 __I uint32_t RESERVED5[61];
rgrover1 361:d2405f5a4853 583 __I uint32_t SEMSTAT; /*!< Semaphore status. */
rgrover1 361:d2405f5a4853 584 __I uint32_t RESERVED6[15];
rgrover1 361:d2405f5a4853 585 __IO uint32_t STATUS; /*!< Status from last transaction. */
rgrover1 361:d2405f5a4853 586 __I uint32_t RESERVED7[47];
rgrover1 361:d2405f5a4853 587 __IO uint32_t ENABLE; /*!< Enable SPIS. */
rgrover1 361:d2405f5a4853 588 __I uint32_t RESERVED8;
rgrover1 361:d2405f5a4853 589 __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
rgrover1 361:d2405f5a4853 590 __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
rgrover1 361:d2405f5a4853 591 __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
rgrover1 361:d2405f5a4853 592 __IO uint32_t PSELCSN; /*!< Pin select for CSN. */
rgrover1 361:d2405f5a4853 593 __I uint32_t RESERVED9[7];
rgrover1 361:d2405f5a4853 594 __IO uint32_t RXDPTR; /*!< RX data pointer. */
rgrover1 361:d2405f5a4853 595 __IO uint32_t MAXRX; /*!< Maximum number of bytes in the receive buffer. */
rgrover1 361:d2405f5a4853 596 __I uint32_t AMOUNTRX; /*!< Number of bytes received in last granted transaction. */
rgrover1 361:d2405f5a4853 597 __I uint32_t RESERVED10;
rgrover1 361:d2405f5a4853 598 __IO uint32_t TXDPTR; /*!< TX data pointer. */
rgrover1 361:d2405f5a4853 599 __IO uint32_t MAXTX; /*!< Maximum number of bytes in the transmit buffer. */
rgrover1 361:d2405f5a4853 600 __I uint32_t AMOUNTTX; /*!< Number of bytes transmitted in last granted transaction. */
rgrover1 361:d2405f5a4853 601 __I uint32_t RESERVED11;
rgrover1 361:d2405f5a4853 602 __IO uint32_t CONFIG; /*!< Configuration register. */
rgrover1 361:d2405f5a4853 603 __I uint32_t RESERVED12;
rgrover1 361:d2405f5a4853 604 __IO uint32_t DEF; /*!< Default character. */
rgrover1 361:d2405f5a4853 605 __I uint32_t RESERVED13[24];
rgrover1 361:d2405f5a4853 606 __IO uint32_t ORC; /*!< Over-read character. */
rgrover1 361:d2405f5a4853 607 __I uint32_t RESERVED14[654];
rgrover1 361:d2405f5a4853 608 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 361:d2405f5a4853 609 } NRF_SPIS_Type;
rgrover1 361:d2405f5a4853 610
rgrover1 361:d2405f5a4853 611
rgrover1 361:d2405f5a4853 612 /* ================================================================================ */
rgrover1 361:d2405f5a4853 613 /* ================ SPIM ================ */
rgrover1 361:d2405f5a4853 614 /* ================================================================================ */
rgrover1 361:d2405f5a4853 615
rgrover1 361:d2405f5a4853 616
rgrover1 361:d2405f5a4853 617 /**
rgrover1 361:d2405f5a4853 618 * @brief SPI master with easyDMA 1. (SPIM)
rgrover1 361:d2405f5a4853 619 */
rgrover1 361:d2405f5a4853 620
rgrover1 361:d2405f5a4853 621 typedef struct { /*!< SPIM Structure */
rgrover1 361:d2405f5a4853 622 __I uint32_t RESERVED0[4];
rgrover1 361:d2405f5a4853 623 __O uint32_t TASKS_START; /*!< Start SPI transaction. */
rgrover1 361:d2405f5a4853 624 __O uint32_t TASKS_STOP; /*!< Stop SPI transaction. */
rgrover1 361:d2405f5a4853 625 __I uint32_t RESERVED1;
rgrover1 361:d2405f5a4853 626 __O uint32_t TASKS_SUSPEND; /*!< Suspend SPI transaction. */
rgrover1 361:d2405f5a4853 627 __O uint32_t TASKS_RESUME; /*!< Resume SPI transaction. */
rgrover1 361:d2405f5a4853 628 __I uint32_t RESERVED2[56];
rgrover1 361:d2405f5a4853 629 __IO uint32_t EVENTS_STOPPED; /*!< SPI transaction has stopped. */
rgrover1 361:d2405f5a4853 630 __I uint32_t RESERVED3[2];
rgrover1 361:d2405f5a4853 631 __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached. */
rgrover1 361:d2405f5a4853 632 __I uint32_t RESERVED4;
rgrover1 361:d2405f5a4853 633 __IO uint32_t EVENTS_END; /*!< End of RXD buffer and TXD buffer reached. */
rgrover1 361:d2405f5a4853 634 __I uint32_t RESERVED5;
rgrover1 361:d2405f5a4853 635 __IO uint32_t EVENTS_ENDTX; /*!< End of TXD buffer reached. */
rgrover1 361:d2405f5a4853 636 __I uint32_t RESERVED6[10];
rgrover1 361:d2405f5a4853 637 __IO uint32_t EVENTS_STARTED; /*!< Transaction started. */
rgrover1 361:d2405f5a4853 638 __I uint32_t RESERVED7[44];
rgrover1 361:d2405f5a4853 639 __IO uint32_t SHORTS; /*!< Shortcuts for SPIM. */
rgrover1 361:d2405f5a4853 640 __I uint32_t RESERVED8[64];
rgrover1 361:d2405f5a4853 641 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 361:d2405f5a4853 642 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 361:d2405f5a4853 643 __I uint32_t RESERVED9[125];
rgrover1 361:d2405f5a4853 644 __IO uint32_t ENABLE; /*!< Enable SPIM. */
rgrover1 361:d2405f5a4853 645 __I uint32_t RESERVED10;
rgrover1 361:d2405f5a4853 646 SPIM_PSEL_Type PSEL; /*!< Pin select configuration. */
rgrover1 361:d2405f5a4853 647 __I uint32_t RESERVED11;
rgrover1 361:d2405f5a4853 648 __I uint32_t RXDDATA; /*!< RXD register. */
rgrover1 361:d2405f5a4853 649 __IO uint32_t TXDDATA; /*!< TXD register. */
rgrover1 361:d2405f5a4853 650 __I uint32_t RESERVED12;
rgrover1 361:d2405f5a4853 651 __IO uint32_t FREQUENCY; /*!< SPI frequency. */
rgrover1 361:d2405f5a4853 652 __I uint32_t RESERVED13[3];
rgrover1 361:d2405f5a4853 653 SPIM_RXD_Type RXD; /*!< RXD EasyDMA configuration and status. */
rgrover1 361:d2405f5a4853 654 __I uint32_t RESERVED14;
rgrover1 361:d2405f5a4853 655 SPIM_TXD_Type TXD; /*!< TXD EasyDMA configuration and status. */
rgrover1 361:d2405f5a4853 656 __I uint32_t RESERVED15;
rgrover1 361:d2405f5a4853 657 __IO uint32_t CONFIG; /*!< Configuration register. */
rgrover1 361:d2405f5a4853 658 __I uint32_t RESERVED16[26];
rgrover1 361:d2405f5a4853 659 __IO uint32_t ORC; /*!< Over-read character. */
rgrover1 361:d2405f5a4853 660 __I uint32_t RESERVED17[654];
rgrover1 361:d2405f5a4853 661 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 361:d2405f5a4853 662 } NRF_SPIM_Type;
rgrover1 361:d2405f5a4853 663
rgrover1 361:d2405f5a4853 664
rgrover1 361:d2405f5a4853 665 /* ================================================================================ */
rgrover1 361:d2405f5a4853 666 /* ================ GPIOTE ================ */
rgrover1 361:d2405f5a4853 667 /* ================================================================================ */
rgrover1 361:d2405f5a4853 668
rgrover1 361:d2405f5a4853 669
rgrover1 361:d2405f5a4853 670 /**
rgrover1 361:d2405f5a4853 671 * @brief GPIO tasks and events. (GPIOTE)
rgrover1 361:d2405f5a4853 672 */
rgrover1 361:d2405f5a4853 673
rgrover1 361:d2405f5a4853 674 typedef struct { /*!< GPIOTE Structure */
rgrover1 361:d2405f5a4853 675 __O uint32_t TASKS_OUT[4]; /*!< Tasks asssociated with GPIOTE channels. */
rgrover1 361:d2405f5a4853 676 __I uint32_t RESERVED0[60];
rgrover1 361:d2405f5a4853 677 __IO uint32_t EVENTS_IN[4]; /*!< Tasks asssociated with GPIOTE channels. */
rgrover1 361:d2405f5a4853 678 __I uint32_t RESERVED1[27];
rgrover1 361:d2405f5a4853 679 __IO uint32_t EVENTS_PORT; /*!< Event generated from multiple pins. */
rgrover1 361:d2405f5a4853 680 __I uint32_t RESERVED2[97];
rgrover1 361:d2405f5a4853 681 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 361:d2405f5a4853 682 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 361:d2405f5a4853 683 __I uint32_t RESERVED3[129];
rgrover1 361:d2405f5a4853 684 __IO uint32_t CONFIG[4]; /*!< Channel configuration registers. */
rgrover1 361:d2405f5a4853 685 __I uint32_t RESERVED4[695];
rgrover1 361:d2405f5a4853 686 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 361:d2405f5a4853 687 } NRF_GPIOTE_Type;
rgrover1 361:d2405f5a4853 688
rgrover1 361:d2405f5a4853 689
rgrover1 361:d2405f5a4853 690 /* ================================================================================ */
rgrover1 361:d2405f5a4853 691 /* ================ ADC ================ */
rgrover1 361:d2405f5a4853 692 /* ================================================================================ */
rgrover1 361:d2405f5a4853 693
rgrover1 361:d2405f5a4853 694
rgrover1 361:d2405f5a4853 695 /**
rgrover1 361:d2405f5a4853 696 * @brief Analog to digital converter. (ADC)
rgrover1 361:d2405f5a4853 697 */
rgrover1 361:d2405f5a4853 698
rgrover1 361:d2405f5a4853 699 typedef struct { /*!< ADC Structure */
rgrover1 361:d2405f5a4853 700 __O uint32_t TASKS_START; /*!< Start an ADC conversion. */
rgrover1 361:d2405f5a4853 701 __O uint32_t TASKS_STOP; /*!< Stop ADC. */
rgrover1 361:d2405f5a4853 702 __I uint32_t RESERVED0[62];
rgrover1 361:d2405f5a4853 703 __IO uint32_t EVENTS_END; /*!< ADC conversion complete. */
rgrover1 361:d2405f5a4853 704 __I uint32_t RESERVED1[128];
rgrover1 361:d2405f5a4853 705 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 361:d2405f5a4853 706 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 361:d2405f5a4853 707 __I uint32_t RESERVED2[61];
rgrover1 361:d2405f5a4853 708 __I uint32_t BUSY; /*!< ADC busy register. */
rgrover1 361:d2405f5a4853 709 __I uint32_t RESERVED3[63];
rgrover1 361:d2405f5a4853 710 __IO uint32_t ENABLE; /*!< ADC enable. */
rgrover1 361:d2405f5a4853 711 __IO uint32_t CONFIG; /*!< ADC configuration register. */
rgrover1 361:d2405f5a4853 712 __I uint32_t RESULT; /*!< Result of ADC conversion. */
rgrover1 361:d2405f5a4853 713 __I uint32_t RESERVED4[700];
rgrover1 361:d2405f5a4853 714 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 361:d2405f5a4853 715 } NRF_ADC_Type;
rgrover1 361:d2405f5a4853 716
rgrover1 361:d2405f5a4853 717
rgrover1 361:d2405f5a4853 718 /* ================================================================================ */
rgrover1 361:d2405f5a4853 719 /* ================ TIMER ================ */
rgrover1 361:d2405f5a4853 720 /* ================================================================================ */
rgrover1 361:d2405f5a4853 721
rgrover1 361:d2405f5a4853 722
rgrover1 361:d2405f5a4853 723 /**
rgrover1 361:d2405f5a4853 724 * @brief Timer 0. (TIMER)
rgrover1 361:d2405f5a4853 725 */
rgrover1 361:d2405f5a4853 726
rgrover1 361:d2405f5a4853 727 typedef struct { /*!< TIMER Structure */
rgrover1 361:d2405f5a4853 728 __O uint32_t TASKS_START; /*!< Start Timer. */
rgrover1 361:d2405f5a4853 729 __O uint32_t TASKS_STOP; /*!< Stop Timer. */
rgrover1 361:d2405f5a4853 730 __O uint32_t TASKS_COUNT; /*!< Increment Timer (In counter mode). */
rgrover1 361:d2405f5a4853 731 __O uint32_t TASKS_CLEAR; /*!< Clear timer. */
rgrover1 361:d2405f5a4853 732 __O uint32_t TASKS_SHUTDOWN; /*!< Shutdown timer. */
rgrover1 361:d2405f5a4853 733 __I uint32_t RESERVED0[11];
rgrover1 361:d2405f5a4853 734 __O uint32_t TASKS_CAPTURE[4]; /*!< Capture Timer value to CC[n] registers. */
rgrover1 361:d2405f5a4853 735 __I uint32_t RESERVED1[60];
rgrover1 361:d2405f5a4853 736 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
rgrover1 361:d2405f5a4853 737 __I uint32_t RESERVED2[44];
rgrover1 361:d2405f5a4853 738 __IO uint32_t SHORTS; /*!< Shortcuts for Timer. */
rgrover1 361:d2405f5a4853 739 __I uint32_t RESERVED3[64];
rgrover1 361:d2405f5a4853 740 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 361:d2405f5a4853 741 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 361:d2405f5a4853 742 __I uint32_t RESERVED4[126];
rgrover1 361:d2405f5a4853 743 __IO uint32_t MODE; /*!< Timer Mode selection. */
rgrover1 361:d2405f5a4853 744 __IO uint32_t BITMODE; /*!< Sets timer behaviour. */
rgrover1 361:d2405f5a4853 745 __I uint32_t RESERVED5;
rgrover1 361:d2405f5a4853 746 __IO uint32_t PRESCALER; /*!< 4-bit prescaler to source clock frequency (max value 9). Source
rgrover1 361:d2405f5a4853 747 clock frequency is divided by 2^SCALE. */
rgrover1 361:d2405f5a4853 748 __I uint32_t RESERVED6[11];
rgrover1 361:d2405f5a4853 749 __IO uint32_t CC[4]; /*!< Capture/compare registers. */
rgrover1 361:d2405f5a4853 750 __I uint32_t RESERVED7[683];
rgrover1 361:d2405f5a4853 751 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 361:d2405f5a4853 752 } NRF_TIMER_Type;
rgrover1 361:d2405f5a4853 753
rgrover1 361:d2405f5a4853 754
rgrover1 361:d2405f5a4853 755 /* ================================================================================ */
rgrover1 361:d2405f5a4853 756 /* ================ RTC ================ */
rgrover1 361:d2405f5a4853 757 /* ================================================================================ */
rgrover1 361:d2405f5a4853 758
rgrover1 361:d2405f5a4853 759
rgrover1 361:d2405f5a4853 760 /**
rgrover1 361:d2405f5a4853 761 * @brief Real time counter 0. (RTC)
rgrover1 361:d2405f5a4853 762 */
rgrover1 361:d2405f5a4853 763
rgrover1 361:d2405f5a4853 764 typedef struct { /*!< RTC Structure */
rgrover1 361:d2405f5a4853 765 __O uint32_t TASKS_START; /*!< Start RTC Counter. */
rgrover1 361:d2405f5a4853 766 __O uint32_t TASKS_STOP; /*!< Stop RTC Counter. */
rgrover1 361:d2405f5a4853 767 __O uint32_t TASKS_CLEAR; /*!< Clear RTC Counter. */
rgrover1 361:d2405f5a4853 768 __O uint32_t TASKS_TRIGOVRFLW; /*!< Set COUNTER to 0xFFFFFFF0. */
rgrover1 361:d2405f5a4853 769 __I uint32_t RESERVED0[60];
rgrover1 361:d2405f5a4853 770 __IO uint32_t EVENTS_TICK; /*!< Event on COUNTER increment. */
rgrover1 361:d2405f5a4853 771 __IO uint32_t EVENTS_OVRFLW; /*!< Event on COUNTER overflow. */
rgrover1 361:d2405f5a4853 772 __I uint32_t RESERVED1[14];
rgrover1 361:d2405f5a4853 773 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
rgrover1 361:d2405f5a4853 774 __I uint32_t RESERVED2[109];
rgrover1 361:d2405f5a4853 775 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 361:d2405f5a4853 776 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 361:d2405f5a4853 777 __I uint32_t RESERVED3[13];
rgrover1 361:d2405f5a4853 778 __IO uint32_t EVTEN; /*!< Configures event enable routing to PPI for each RTC event. */
rgrover1 361:d2405f5a4853 779 __IO uint32_t EVTENSET; /*!< Enable events routing to PPI. The reading of this register gives
rgrover1 361:d2405f5a4853 780 the value of EVTEN. */
rgrover1 361:d2405f5a4853 781 __IO uint32_t EVTENCLR; /*!< Disable events routing to PPI. The reading of this register
rgrover1 361:d2405f5a4853 782 gives the value of EVTEN. */
rgrover1 361:d2405f5a4853 783 __I uint32_t RESERVED4[110];
rgrover1 361:d2405f5a4853 784 __I uint32_t COUNTER; /*!< Current COUNTER value. */
rgrover1 361:d2405f5a4853 785 __IO uint32_t PRESCALER; /*!< 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).
rgrover1 361:d2405f5a4853 786 Must be written when RTC is STOPed. */
rgrover1 361:d2405f5a4853 787 __I uint32_t RESERVED5[13];
rgrover1 361:d2405f5a4853 788 __IO uint32_t CC[4]; /*!< Capture/compare registers. */
rgrover1 361:d2405f5a4853 789 __I uint32_t RESERVED6[683];
rgrover1 361:d2405f5a4853 790 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 361:d2405f5a4853 791 } NRF_RTC_Type;
rgrover1 361:d2405f5a4853 792
rgrover1 361:d2405f5a4853 793
rgrover1 361:d2405f5a4853 794 /* ================================================================================ */
rgrover1 361:d2405f5a4853 795 /* ================ TEMP ================ */
rgrover1 361:d2405f5a4853 796 /* ================================================================================ */
rgrover1 361:d2405f5a4853 797
rgrover1 361:d2405f5a4853 798
rgrover1 361:d2405f5a4853 799 /**
rgrover1 361:d2405f5a4853 800 * @brief Temperature Sensor. (TEMP)
rgrover1 361:d2405f5a4853 801 */
rgrover1 361:d2405f5a4853 802
rgrover1 361:d2405f5a4853 803 typedef struct { /*!< TEMP Structure */
rgrover1 361:d2405f5a4853 804 __O uint32_t TASKS_START; /*!< Start temperature measurement. */
rgrover1 361:d2405f5a4853 805 __O uint32_t TASKS_STOP; /*!< Stop temperature measurement. */
rgrover1 361:d2405f5a4853 806 __I uint32_t RESERVED0[62];
rgrover1 361:d2405f5a4853 807 __IO uint32_t EVENTS_DATARDY; /*!< Temperature measurement complete, data ready event. */
rgrover1 361:d2405f5a4853 808 __I uint32_t RESERVED1[128];
rgrover1 361:d2405f5a4853 809 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 361:d2405f5a4853 810 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 361:d2405f5a4853 811 __I uint32_t RESERVED2[127];
rgrover1 361:d2405f5a4853 812 __I int32_t TEMP; /*!< Die temperature in degC, 2's complement format, 0.25 degC pecision. */
rgrover1 361:d2405f5a4853 813 __I uint32_t RESERVED3[700];
rgrover1 361:d2405f5a4853 814 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 361:d2405f5a4853 815 } NRF_TEMP_Type;
rgrover1 361:d2405f5a4853 816
rgrover1 361:d2405f5a4853 817
rgrover1 361:d2405f5a4853 818 /* ================================================================================ */
rgrover1 361:d2405f5a4853 819 /* ================ RNG ================ */
rgrover1 361:d2405f5a4853 820 /* ================================================================================ */
rgrover1 361:d2405f5a4853 821
rgrover1 361:d2405f5a4853 822
rgrover1 361:d2405f5a4853 823 /**
rgrover1 361:d2405f5a4853 824 * @brief Random Number Generator. (RNG)
rgrover1 361:d2405f5a4853 825 */
rgrover1 361:d2405f5a4853 826
rgrover1 361:d2405f5a4853 827 typedef struct { /*!< RNG Structure */
rgrover1 361:d2405f5a4853 828 __O uint32_t TASKS_START; /*!< Start the random number generator. */
rgrover1 361:d2405f5a4853 829 __O uint32_t TASKS_STOP; /*!< Stop the random number generator. */
rgrover1 361:d2405f5a4853 830 __I uint32_t RESERVED0[62];
rgrover1 361:d2405f5a4853 831 __IO uint32_t EVENTS_VALRDY; /*!< New random number generated and written to VALUE register. */
rgrover1 361:d2405f5a4853 832 __I uint32_t RESERVED1[63];
rgrover1 361:d2405f5a4853 833 __IO uint32_t SHORTS; /*!< Shortcuts for the RNG. */
rgrover1 361:d2405f5a4853 834 __I uint32_t RESERVED2[64];
rgrover1 361:d2405f5a4853 835 __IO uint32_t INTENSET; /*!< Interrupt enable set register */
rgrover1 361:d2405f5a4853 836 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register */
rgrover1 361:d2405f5a4853 837 __I uint32_t RESERVED3[126];
rgrover1 361:d2405f5a4853 838 __IO uint32_t CONFIG; /*!< Configuration register. */
rgrover1 361:d2405f5a4853 839 __I uint32_t VALUE; /*!< RNG random number. */
rgrover1 361:d2405f5a4853 840 __I uint32_t RESERVED4[700];
rgrover1 361:d2405f5a4853 841 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 361:d2405f5a4853 842 } NRF_RNG_Type;
rgrover1 361:d2405f5a4853 843
rgrover1 361:d2405f5a4853 844
rgrover1 361:d2405f5a4853 845 /* ================================================================================ */
rgrover1 361:d2405f5a4853 846 /* ================ ECB ================ */
rgrover1 361:d2405f5a4853 847 /* ================================================================================ */
rgrover1 361:d2405f5a4853 848
rgrover1 361:d2405f5a4853 849
rgrover1 361:d2405f5a4853 850 /**
rgrover1 361:d2405f5a4853 851 * @brief AES ECB Mode Encryption. (ECB)
rgrover1 361:d2405f5a4853 852 */
rgrover1 361:d2405f5a4853 853
rgrover1 361:d2405f5a4853 854 typedef struct { /*!< ECB Structure */
rgrover1 361:d2405f5a4853 855 __O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt. If a crypto operation is running, this
rgrover1 361:d2405f5a4853 856 will not initiate a new encryption and the ERRORECB event will
rgrover1 361:d2405f5a4853 857 be triggered. */
rgrover1 361:d2405f5a4853 858 __O uint32_t TASKS_STOPECB; /*!< Stop current ECB encryption. If a crypto operation is running,
rgrover1 361:d2405f5a4853 859 this will will trigger the ERRORECB event. */
rgrover1 361:d2405f5a4853 860 __I uint32_t RESERVED0[62];
rgrover1 361:d2405f5a4853 861 __IO uint32_t EVENTS_ENDECB; /*!< ECB block encrypt complete. */
rgrover1 361:d2405f5a4853 862 __IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted due to a STOPECB task or due to an
rgrover1 361:d2405f5a4853 863 error. */
rgrover1 361:d2405f5a4853 864 __I uint32_t RESERVED1[127];
rgrover1 361:d2405f5a4853 865 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 361:d2405f5a4853 866 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 361:d2405f5a4853 867 __I uint32_t RESERVED2[126];
rgrover1 361:d2405f5a4853 868 __IO uint32_t ECBDATAPTR; /*!< ECB block encrypt memory pointer. */
rgrover1 361:d2405f5a4853 869 __I uint32_t RESERVED3[701];
rgrover1 361:d2405f5a4853 870 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 361:d2405f5a4853 871 } NRF_ECB_Type;
rgrover1 361:d2405f5a4853 872
rgrover1 361:d2405f5a4853 873
rgrover1 361:d2405f5a4853 874 /* ================================================================================ */
rgrover1 361:d2405f5a4853 875 /* ================ AAR ================ */
rgrover1 361:d2405f5a4853 876 /* ================================================================================ */
rgrover1 361:d2405f5a4853 877
rgrover1 361:d2405f5a4853 878
rgrover1 361:d2405f5a4853 879 /**
rgrover1 361:d2405f5a4853 880 * @brief Accelerated Address Resolver. (AAR)
rgrover1 361:d2405f5a4853 881 */
rgrover1 361:d2405f5a4853 882
rgrover1 361:d2405f5a4853 883 typedef struct { /*!< AAR Structure */
rgrover1 361:d2405f5a4853 884 __O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK
rgrover1 361:d2405f5a4853 885 data structure. */
rgrover1 361:d2405f5a4853 886 __I uint32_t RESERVED0;
rgrover1 361:d2405f5a4853 887 __O uint32_t TASKS_STOP; /*!< Stop resolving addresses. */
rgrover1 361:d2405f5a4853 888 __I uint32_t RESERVED1[61];
rgrover1 361:d2405f5a4853 889 __IO uint32_t EVENTS_END; /*!< Address resolution procedure completed. */
rgrover1 361:d2405f5a4853 890 __IO uint32_t EVENTS_RESOLVED; /*!< Address resolved. */
rgrover1 361:d2405f5a4853 891 __IO uint32_t EVENTS_NOTRESOLVED; /*!< Address not resolved. */
rgrover1 361:d2405f5a4853 892 __I uint32_t RESERVED2[126];
rgrover1 361:d2405f5a4853 893 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 361:d2405f5a4853 894 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 361:d2405f5a4853 895 __I uint32_t RESERVED3[61];
rgrover1 361:d2405f5a4853 896 __I uint32_t STATUS; /*!< Resolution status. */
rgrover1 361:d2405f5a4853 897 __I uint32_t RESERVED4[63];
rgrover1 361:d2405f5a4853 898 __IO uint32_t ENABLE; /*!< Enable AAR. */
rgrover1 361:d2405f5a4853 899 __IO uint32_t NIRK; /*!< Number of Identity root Keys in the IRK data structure. */
rgrover1 361:d2405f5a4853 900 __IO uint32_t IRKPTR; /*!< Pointer to the IRK data structure. */
rgrover1 361:d2405f5a4853 901 __I uint32_t RESERVED5;
rgrover1 361:d2405f5a4853 902 __IO uint32_t ADDRPTR; /*!< Pointer to the resolvable address (6 bytes). */
rgrover1 361:d2405f5a4853 903 __IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
rgrover1 361:d2405f5a4853 904 during resolution. A minimum of 3 bytes must be reserved. */
rgrover1 361:d2405f5a4853 905 __I uint32_t RESERVED6[697];
rgrover1 361:d2405f5a4853 906 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 361:d2405f5a4853 907 } NRF_AAR_Type;
rgrover1 361:d2405f5a4853 908
rgrover1 361:d2405f5a4853 909
rgrover1 361:d2405f5a4853 910 /* ================================================================================ */
rgrover1 361:d2405f5a4853 911 /* ================ CCM ================ */
rgrover1 361:d2405f5a4853 912 /* ================================================================================ */
rgrover1 361:d2405f5a4853 913
rgrover1 361:d2405f5a4853 914
rgrover1 361:d2405f5a4853 915 /**
rgrover1 361:d2405f5a4853 916 * @brief AES CCM Mode Encryption. (CCM)
rgrover1 361:d2405f5a4853 917 */
rgrover1 361:d2405f5a4853 918
rgrover1 361:d2405f5a4853 919 typedef struct { /*!< CCM Structure */
rgrover1 361:d2405f5a4853 920 __O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by
rgrover1 361:d2405f5a4853 921 itself when completed. */
rgrover1 361:d2405f5a4853 922 __O uint32_t TASKS_CRYPT; /*!< Start encrypt/decrypt. This operation will stop by itself when
rgrover1 361:d2405f5a4853 923 completed. */
rgrover1 361:d2405f5a4853 924 __O uint32_t TASKS_STOP; /*!< Stop encrypt/decrypt. */
rgrover1 361:d2405f5a4853 925 __I uint32_t RESERVED0[61];
rgrover1 361:d2405f5a4853 926 __IO uint32_t EVENTS_ENDKSGEN; /*!< Keystream generation completed. */
rgrover1 361:d2405f5a4853 927 __IO uint32_t EVENTS_ENDCRYPT; /*!< Encrypt/decrypt completed. */
rgrover1 361:d2405f5a4853 928 __IO uint32_t EVENTS_ERROR; /*!< Error happened. */
rgrover1 361:d2405f5a4853 929 __I uint32_t RESERVED1[61];
rgrover1 361:d2405f5a4853 930 __IO uint32_t SHORTS; /*!< Shortcuts for the CCM. */
rgrover1 361:d2405f5a4853 931 __I uint32_t RESERVED2[64];
rgrover1 361:d2405f5a4853 932 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 361:d2405f5a4853 933 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 361:d2405f5a4853 934 __I uint32_t RESERVED3[61];
rgrover1 361:d2405f5a4853 935 __I uint32_t MICSTATUS; /*!< CCM RX MIC check result. */
rgrover1 361:d2405f5a4853 936 __I uint32_t RESERVED4[63];
rgrover1 361:d2405f5a4853 937 __IO uint32_t ENABLE; /*!< CCM enable. */
rgrover1 361:d2405f5a4853 938 __IO uint32_t MODE; /*!< Operation mode. */
rgrover1 361:d2405f5a4853 939 __IO uint32_t CNFPTR; /*!< Pointer to a data structure holding AES key and NONCE vector. */
rgrover1 361:d2405f5a4853 940 __IO uint32_t INPTR; /*!< Pointer to the input packet. */
rgrover1 361:d2405f5a4853 941 __IO uint32_t OUTPTR; /*!< Pointer to the output packet. */
rgrover1 361:d2405f5a4853 942 __IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
rgrover1 361:d2405f5a4853 943 during resolution. A minimum of 43 bytes must be reserved. */
rgrover1 361:d2405f5a4853 944 __I uint32_t RESERVED5[697];
rgrover1 361:d2405f5a4853 945 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 361:d2405f5a4853 946 } NRF_CCM_Type;
rgrover1 361:d2405f5a4853 947
rgrover1 361:d2405f5a4853 948
rgrover1 361:d2405f5a4853 949 /* ================================================================================ */
rgrover1 361:d2405f5a4853 950 /* ================ WDT ================ */
rgrover1 361:d2405f5a4853 951 /* ================================================================================ */
rgrover1 361:d2405f5a4853 952
rgrover1 361:d2405f5a4853 953
rgrover1 361:d2405f5a4853 954 /**
rgrover1 361:d2405f5a4853 955 * @brief Watchdog Timer. (WDT)
rgrover1 361:d2405f5a4853 956 */
rgrover1 361:d2405f5a4853 957
rgrover1 361:d2405f5a4853 958 typedef struct { /*!< WDT Structure */
rgrover1 361:d2405f5a4853 959 __O uint32_t TASKS_START; /*!< Start the watchdog. */
rgrover1 361:d2405f5a4853 960 __I uint32_t RESERVED0[63];
rgrover1 361:d2405f5a4853 961 __IO uint32_t EVENTS_TIMEOUT; /*!< Watchdog timeout. */
rgrover1 361:d2405f5a4853 962 __I uint32_t RESERVED1[128];
rgrover1 361:d2405f5a4853 963 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 361:d2405f5a4853 964 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 361:d2405f5a4853 965 __I uint32_t RESERVED2[61];
rgrover1 361:d2405f5a4853 966 __I uint32_t RUNSTATUS; /*!< Watchdog running status. */
rgrover1 361:d2405f5a4853 967 __I uint32_t REQSTATUS; /*!< Request status. */
rgrover1 361:d2405f5a4853 968 __I uint32_t RESERVED3[63];
rgrover1 361:d2405f5a4853 969 __IO uint32_t CRV; /*!< Counter reload value in number of 32kiHz clock cycles. */
rgrover1 361:d2405f5a4853 970 __IO uint32_t RREN; /*!< Reload request enable. */
rgrover1 361:d2405f5a4853 971 __IO uint32_t CONFIG; /*!< Configuration register. */
rgrover1 361:d2405f5a4853 972 __I uint32_t RESERVED4[60];
rgrover1 361:d2405f5a4853 973 __O uint32_t RR[8]; /*!< Reload requests registers. */
rgrover1 361:d2405f5a4853 974 __I uint32_t RESERVED5[631];
rgrover1 361:d2405f5a4853 975 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 361:d2405f5a4853 976 } NRF_WDT_Type;
rgrover1 361:d2405f5a4853 977
rgrover1 361:d2405f5a4853 978
rgrover1 361:d2405f5a4853 979 /* ================================================================================ */
rgrover1 361:d2405f5a4853 980 /* ================ QDEC ================ */
rgrover1 361:d2405f5a4853 981 /* ================================================================================ */
rgrover1 361:d2405f5a4853 982
rgrover1 361:d2405f5a4853 983
rgrover1 361:d2405f5a4853 984 /**
rgrover1 361:d2405f5a4853 985 * @brief Rotary decoder. (QDEC)
rgrover1 361:d2405f5a4853 986 */
rgrover1 361:d2405f5a4853 987
rgrover1 361:d2405f5a4853 988 typedef struct { /*!< QDEC Structure */
rgrover1 361:d2405f5a4853 989 __O uint32_t TASKS_START; /*!< Start the quadrature decoder. */
rgrover1 361:d2405f5a4853 990 __O uint32_t TASKS_STOP; /*!< Stop the quadrature decoder. */
rgrover1 361:d2405f5a4853 991 __O uint32_t TASKS_READCLRACC; /*!< Transfers the content from ACC registers to ACCREAD registers,
rgrover1 361:d2405f5a4853 992 and clears the ACC registers. */
rgrover1 361:d2405f5a4853 993 __I uint32_t RESERVED0[61];
rgrover1 361:d2405f5a4853 994 __IO uint32_t EVENTS_SAMPLERDY; /*!< A new sample is written to the sample register. */
rgrover1 361:d2405f5a4853 995 __IO uint32_t EVENTS_REPORTRDY; /*!< REPORTPER number of samples accumulated in ACC register, and
rgrover1 361:d2405f5a4853 996 ACC register different than zero. */
rgrover1 361:d2405f5a4853 997 __IO uint32_t EVENTS_ACCOF; /*!< ACC or ACCDBL register overflow. */
rgrover1 361:d2405f5a4853 998 __I uint32_t RESERVED1[61];
rgrover1 361:d2405f5a4853 999 __IO uint32_t SHORTS; /*!< Shortcuts for the QDEC. */
rgrover1 361:d2405f5a4853 1000 __I uint32_t RESERVED2[64];
rgrover1 361:d2405f5a4853 1001 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 361:d2405f5a4853 1002 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 361:d2405f5a4853 1003 __I uint32_t RESERVED3[125];
rgrover1 361:d2405f5a4853 1004 __IO uint32_t ENABLE; /*!< Enable the QDEC. */
rgrover1 361:d2405f5a4853 1005 __IO uint32_t LEDPOL; /*!< LED output pin polarity. */
rgrover1 361:d2405f5a4853 1006 __IO uint32_t SAMPLEPER; /*!< Sample period. */
rgrover1 361:d2405f5a4853 1007 __I int32_t SAMPLE; /*!< Motion sample value. */
rgrover1 361:d2405f5a4853 1008 __IO uint32_t REPORTPER; /*!< Number of samples to generate an EVENT_REPORTRDY. */
rgrover1 361:d2405f5a4853 1009 __I int32_t ACC; /*!< Accumulated valid transitions register. */
rgrover1 361:d2405f5a4853 1010 __I int32_t ACCREAD; /*!< Snapshot of ACC register. Value generated by the TASKS_READCLEACC
rgrover1 361:d2405f5a4853 1011 task. */
rgrover1 361:d2405f5a4853 1012 __IO uint32_t PSELLED; /*!< Pin select for LED output. */
rgrover1 361:d2405f5a4853 1013 __IO uint32_t PSELA; /*!< Pin select for phase A input. */
rgrover1 361:d2405f5a4853 1014 __IO uint32_t PSELB; /*!< Pin select for phase B input. */
rgrover1 361:d2405f5a4853 1015 __IO uint32_t DBFEN; /*!< Enable debouncer input filters. */
rgrover1 361:d2405f5a4853 1016 __I uint32_t RESERVED4[5];
rgrover1 361:d2405f5a4853 1017 __IO uint32_t LEDPRE; /*!< Time LED is switched ON before the sample. */
rgrover1 361:d2405f5a4853 1018 __I uint32_t ACCDBL; /*!< Accumulated double (error) transitions register. */
rgrover1 361:d2405f5a4853 1019 __I uint32_t ACCDBLREAD; /*!< Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC
rgrover1 361:d2405f5a4853 1020 task. */
rgrover1 361:d2405f5a4853 1021 __I uint32_t RESERVED5[684];
rgrover1 361:d2405f5a4853 1022 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 361:d2405f5a4853 1023 } NRF_QDEC_Type;
rgrover1 361:d2405f5a4853 1024
rgrover1 361:d2405f5a4853 1025
rgrover1 361:d2405f5a4853 1026 /* ================================================================================ */
rgrover1 361:d2405f5a4853 1027 /* ================ LPCOMP ================ */
rgrover1 361:d2405f5a4853 1028 /* ================================================================================ */
rgrover1 361:d2405f5a4853 1029
rgrover1 361:d2405f5a4853 1030
rgrover1 361:d2405f5a4853 1031 /**
rgrover1 361:d2405f5a4853 1032 * @brief Low power comparator. (LPCOMP)
rgrover1 361:d2405f5a4853 1033 */
rgrover1 361:d2405f5a4853 1034
rgrover1 361:d2405f5a4853 1035 typedef struct { /*!< LPCOMP Structure */
rgrover1 361:d2405f5a4853 1036 __O uint32_t TASKS_START; /*!< Start the comparator. */
rgrover1 361:d2405f5a4853 1037 __O uint32_t TASKS_STOP; /*!< Stop the comparator. */
rgrover1 361:d2405f5a4853 1038 __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value. */
rgrover1 361:d2405f5a4853 1039 __I uint32_t RESERVED0[61];
rgrover1 361:d2405f5a4853 1040 __IO uint32_t EVENTS_READY; /*!< LPCOMP is ready and output is valid. */
rgrover1 361:d2405f5a4853 1041 __IO uint32_t EVENTS_DOWN; /*!< Input voltage crossed the threshold going down. */
rgrover1 361:d2405f5a4853 1042 __IO uint32_t EVENTS_UP; /*!< Input voltage crossed the threshold going up. */
rgrover1 361:d2405f5a4853 1043 __IO uint32_t EVENTS_CROSS; /*!< Input voltage crossed the threshold in any direction. */
rgrover1 361:d2405f5a4853 1044 __I uint32_t RESERVED1[60];
rgrover1 361:d2405f5a4853 1045 __IO uint32_t SHORTS; /*!< Shortcuts for the LPCOMP. */
rgrover1 361:d2405f5a4853 1046 __I uint32_t RESERVED2[64];
rgrover1 361:d2405f5a4853 1047 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 361:d2405f5a4853 1048 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 361:d2405f5a4853 1049 __I uint32_t RESERVED3[61];
rgrover1 361:d2405f5a4853 1050 __I uint32_t RESULT; /*!< Result of last compare. */
rgrover1 361:d2405f5a4853 1051 __I uint32_t RESERVED4[63];
rgrover1 361:d2405f5a4853 1052 __IO uint32_t ENABLE; /*!< Enable the LPCOMP. */
rgrover1 361:d2405f5a4853 1053 __IO uint32_t PSEL; /*!< Input pin select. */
rgrover1 361:d2405f5a4853 1054 __IO uint32_t REFSEL; /*!< Reference select. */
rgrover1 361:d2405f5a4853 1055 __IO uint32_t EXTREFSEL; /*!< External reference select. */
rgrover1 361:d2405f5a4853 1056 __I uint32_t RESERVED5[4];
rgrover1 361:d2405f5a4853 1057 __IO uint32_t ANADETECT; /*!< Analog detect configuration. */
rgrover1 361:d2405f5a4853 1058 __I uint32_t RESERVED6[694];
rgrover1 361:d2405f5a4853 1059 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 361:d2405f5a4853 1060 } NRF_LPCOMP_Type;
rgrover1 361:d2405f5a4853 1061
rgrover1 361:d2405f5a4853 1062
rgrover1 361:d2405f5a4853 1063 /* ================================================================================ */
rgrover1 361:d2405f5a4853 1064 /* ================ SWI ================ */
rgrover1 361:d2405f5a4853 1065 /* ================================================================================ */
rgrover1 361:d2405f5a4853 1066
rgrover1 361:d2405f5a4853 1067
rgrover1 361:d2405f5a4853 1068 /**
rgrover1 361:d2405f5a4853 1069 * @brief SW Interrupts. (SWI)
rgrover1 361:d2405f5a4853 1070 */
rgrover1 361:d2405f5a4853 1071
rgrover1 361:d2405f5a4853 1072 typedef struct { /*!< SWI Structure */
rgrover1 361:d2405f5a4853 1073 __I uint32_t UNUSED; /*!< Unused. */
rgrover1 361:d2405f5a4853 1074 } NRF_SWI_Type;
rgrover1 361:d2405f5a4853 1075
rgrover1 361:d2405f5a4853 1076
rgrover1 361:d2405f5a4853 1077 /* ================================================================================ */
rgrover1 361:d2405f5a4853 1078 /* ================ NVMC ================ */
rgrover1 361:d2405f5a4853 1079 /* ================================================================================ */
rgrover1 361:d2405f5a4853 1080
rgrover1 361:d2405f5a4853 1081
rgrover1 361:d2405f5a4853 1082 /**
rgrover1 361:d2405f5a4853 1083 * @brief Non Volatile Memory Controller. (NVMC)
rgrover1 361:d2405f5a4853 1084 */
rgrover1 361:d2405f5a4853 1085
rgrover1 361:d2405f5a4853 1086 typedef struct { /*!< NVMC Structure */
rgrover1 361:d2405f5a4853 1087 __I uint32_t RESERVED0[256];
rgrover1 361:d2405f5a4853 1088 __I uint32_t READY; /*!< Ready flag. */
rgrover1 361:d2405f5a4853 1089 __I uint32_t RESERVED1[64];
rgrover1 361:d2405f5a4853 1090 __IO uint32_t CONFIG; /*!< Configuration register. */
rgrover1 361:d2405f5a4853 1091 __IO uint32_t ERASEPAGE; /*!< Register for erasing a non-protected non-volatile memory page. */
rgrover1 361:d2405f5a4853 1092 __IO uint32_t ERASEALL; /*!< Register for erasing all non-volatile user memory. */
rgrover1 361:d2405f5a4853 1093 __IO uint32_t ERASEPROTECTEDPAGE; /*!< Register for erasing a protected non-volatile memory page. */
rgrover1 361:d2405f5a4853 1094 __IO uint32_t ERASEUICR; /*!< Register for start erasing User Information Congfiguration Registers. */
rgrover1 361:d2405f5a4853 1095 } NRF_NVMC_Type;
rgrover1 361:d2405f5a4853 1096
rgrover1 361:d2405f5a4853 1097
rgrover1 361:d2405f5a4853 1098 /* ================================================================================ */
rgrover1 361:d2405f5a4853 1099 /* ================ PPI ================ */
rgrover1 361:d2405f5a4853 1100 /* ================================================================================ */
rgrover1 361:d2405f5a4853 1101
rgrover1 361:d2405f5a4853 1102
rgrover1 361:d2405f5a4853 1103 /**
rgrover1 361:d2405f5a4853 1104 * @brief PPI controller. (PPI)
rgrover1 361:d2405f5a4853 1105 */
rgrover1 361:d2405f5a4853 1106
rgrover1 361:d2405f5a4853 1107 typedef struct { /*!< PPI Structure */
rgrover1 361:d2405f5a4853 1108 PPI_TASKS_CHG_Type TASKS_CHG[4]; /*!< Channel group tasks. */
rgrover1 361:d2405f5a4853 1109 __I uint32_t RESERVED0[312];
rgrover1 361:d2405f5a4853 1110 __IO uint32_t CHEN; /*!< Channel enable. */
rgrover1 361:d2405f5a4853 1111 __IO uint32_t CHENSET; /*!< Channel enable set. */
rgrover1 361:d2405f5a4853 1112 __IO uint32_t CHENCLR; /*!< Channel enable clear. */
rgrover1 361:d2405f5a4853 1113 __I uint32_t RESERVED1;
rgrover1 361:d2405f5a4853 1114 PPI_CH_Type CH[16]; /*!< PPI Channel. */
rgrover1 361:d2405f5a4853 1115 __I uint32_t RESERVED2[156];
rgrover1 361:d2405f5a4853 1116 __IO uint32_t CHG[4]; /*!< Channel group configuration. */
rgrover1 361:d2405f5a4853 1117 } NRF_PPI_Type;
rgrover1 361:d2405f5a4853 1118
rgrover1 361:d2405f5a4853 1119
rgrover1 361:d2405f5a4853 1120 /* ================================================================================ */
rgrover1 361:d2405f5a4853 1121 /* ================ FICR ================ */
rgrover1 361:d2405f5a4853 1122 /* ================================================================================ */
rgrover1 361:d2405f5a4853 1123
rgrover1 361:d2405f5a4853 1124
rgrover1 361:d2405f5a4853 1125 /**
rgrover1 361:d2405f5a4853 1126 * @brief Factory Information Configuration. (FICR)
rgrover1 361:d2405f5a4853 1127 */
rgrover1 361:d2405f5a4853 1128
rgrover1 361:d2405f5a4853 1129 typedef struct { /*!< FICR Structure */
rgrover1 361:d2405f5a4853 1130 __I uint32_t RESERVED0[4];
rgrover1 361:d2405f5a4853 1131 __I uint32_t CODEPAGESIZE; /*!< Code memory page size in bytes. */
rgrover1 361:d2405f5a4853 1132 __I uint32_t CODESIZE; /*!< Code memory size in pages. */
rgrover1 361:d2405f5a4853 1133 __I uint32_t RESERVED1[4];
rgrover1 361:d2405f5a4853 1134 __I uint32_t CLENR0; /*!< Length of code region 0 in bytes. */
rgrover1 361:d2405f5a4853 1135 __I uint32_t PPFC; /*!< Pre-programmed factory code present. */
rgrover1 361:d2405f5a4853 1136 __I uint32_t RESERVED2;
rgrover1 361:d2405f5a4853 1137 __I uint32_t NUMRAMBLOCK; /*!< Number of individualy controllable RAM blocks. */
rgrover1 361:d2405f5a4853 1138
rgrover1 361:d2405f5a4853 1139 union {
rgrover1 361:d2405f5a4853 1140 __I uint32_t SIZERAMBLOCK[4]; /*!< Deprecated array of size of RAM block in bytes. This name is
rgrover1 361:d2405f5a4853 1141 kept for backward compatinility purposes. Use SIZERAMBLOCKS
rgrover1 361:d2405f5a4853 1142 instead. */
rgrover1 361:d2405f5a4853 1143 __I uint32_t SIZERAMBLOCKS; /*!< Size of RAM blocks in bytes. */
rgrover1 361:d2405f5a4853 1144 };
rgrover1 361:d2405f5a4853 1145 __I uint32_t RESERVED3[5];
rgrover1 361:d2405f5a4853 1146 __I uint32_t CONFIGID; /*!< Configuration identifier. */
rgrover1 361:d2405f5a4853 1147 __I uint32_t DEVICEID[2]; /*!< Device identifier. */
rgrover1 361:d2405f5a4853 1148 __I uint32_t RESERVED4[6];
rgrover1 361:d2405f5a4853 1149 __I uint32_t ER[4]; /*!< Encryption root. */
rgrover1 361:d2405f5a4853 1150 __I uint32_t IR[4]; /*!< Identity root. */
rgrover1 361:d2405f5a4853 1151 __I uint32_t DEVICEADDRTYPE; /*!< Device address type. */
rgrover1 361:d2405f5a4853 1152 __I uint32_t DEVICEADDR[2]; /*!< Device address. */
rgrover1 361:d2405f5a4853 1153 __I uint32_t OVERRIDEEN; /*!< Radio calibration override enable. */
rgrover1 361:d2405f5a4853 1154 __I uint32_t NRF_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for NRF_1Mbit
rgrover1 361:d2405f5a4853 1155 mode. */
rgrover1 361:d2405f5a4853 1156 __I uint32_t RESERVED5[10];
rgrover1 361:d2405f5a4853 1157 __I uint32_t BLE_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit
rgrover1 361:d2405f5a4853 1158 mode. */
rgrover1 361:d2405f5a4853 1159 FICR_INFO_Type INFO; /*!< Device info */
rgrover1 361:d2405f5a4853 1160 } NRF_FICR_Type;
rgrover1 361:d2405f5a4853 1161
rgrover1 361:d2405f5a4853 1162
rgrover1 361:d2405f5a4853 1163 /* ================================================================================ */
rgrover1 361:d2405f5a4853 1164 /* ================ UICR ================ */
rgrover1 361:d2405f5a4853 1165 /* ================================================================================ */
rgrover1 361:d2405f5a4853 1166
rgrover1 361:d2405f5a4853 1167
rgrover1 361:d2405f5a4853 1168 /**
rgrover1 361:d2405f5a4853 1169 * @brief User Information Configuration. (UICR)
rgrover1 361:d2405f5a4853 1170 */
rgrover1 361:d2405f5a4853 1171
rgrover1 361:d2405f5a4853 1172 typedef struct { /*!< UICR Structure */
rgrover1 361:d2405f5a4853 1173 __IO uint32_t CLENR0; /*!< Length of code region 0. */
rgrover1 361:d2405f5a4853 1174 __IO uint32_t RBPCONF; /*!< Readback protection configuration. */
rgrover1 361:d2405f5a4853 1175 __IO uint32_t XTALFREQ; /*!< Reset value for CLOCK XTALFREQ register. */
rgrover1 361:d2405f5a4853 1176 __I uint32_t RESERVED0;
rgrover1 361:d2405f5a4853 1177 __I uint32_t FWID; /*!< Firmware ID. */
rgrover1 361:d2405f5a4853 1178 __IO uint32_t BOOTLOADERADDR; /*!< Bootloader start address. */
rgrover1 361:d2405f5a4853 1179 } NRF_UICR_Type;
rgrover1 361:d2405f5a4853 1180
rgrover1 361:d2405f5a4853 1181
rgrover1 361:d2405f5a4853 1182 /* ================================================================================ */
rgrover1 361:d2405f5a4853 1183 /* ================ GPIO ================ */
rgrover1 361:d2405f5a4853 1184 /* ================================================================================ */
rgrover1 361:d2405f5a4853 1185
rgrover1 361:d2405f5a4853 1186
rgrover1 361:d2405f5a4853 1187 /**
rgrover1 361:d2405f5a4853 1188 * @brief General purpose input and output. (GPIO)
rgrover1 361:d2405f5a4853 1189 */
rgrover1 361:d2405f5a4853 1190
rgrover1 361:d2405f5a4853 1191 typedef struct { /*!< GPIO Structure */
rgrover1 361:d2405f5a4853 1192 __I uint32_t RESERVED0[321];
rgrover1 361:d2405f5a4853 1193 __IO uint32_t OUT; /*!< Write GPIO port. */
rgrover1 361:d2405f5a4853 1194 __IO uint32_t OUTSET; /*!< Set individual bits in GPIO port. */
rgrover1 361:d2405f5a4853 1195 __IO uint32_t OUTCLR; /*!< Clear individual bits in GPIO port. */
rgrover1 361:d2405f5a4853 1196 __I uint32_t IN; /*!< Read GPIO port. */
rgrover1 361:d2405f5a4853 1197 __IO uint32_t DIR; /*!< Direction of GPIO pins. */
rgrover1 361:d2405f5a4853 1198 __IO uint32_t DIRSET; /*!< DIR set register. */
rgrover1 361:d2405f5a4853 1199 __IO uint32_t DIRCLR; /*!< DIR clear register. */
rgrover1 361:d2405f5a4853 1200 __I uint32_t RESERVED1[120];
rgrover1 361:d2405f5a4853 1201 __IO uint32_t PIN_CNF[32]; /*!< Configuration of GPIO pins. */
rgrover1 361:d2405f5a4853 1202 } NRF_GPIO_Type;
rgrover1 361:d2405f5a4853 1203
rgrover1 361:d2405f5a4853 1204
rgrover1 361:d2405f5a4853 1205 /* -------------------- End of section using anonymous unions ------------------- */
rgrover1 361:d2405f5a4853 1206 #if defined(__CC_ARM)
rgrover1 361:d2405f5a4853 1207 #pragma pop
rgrover1 361:d2405f5a4853 1208 #elif defined(__ICCARM__)
rgrover1 361:d2405f5a4853 1209 /* leave anonymous unions enabled */
rgrover1 361:d2405f5a4853 1210 #elif defined(__GNUC__)
rgrover1 361:d2405f5a4853 1211 /* anonymous unions are enabled by default */
rgrover1 361:d2405f5a4853 1212 #elif defined(__TMS470__)
rgrover1 361:d2405f5a4853 1213 /* anonymous unions are enabled by default */
rgrover1 361:d2405f5a4853 1214 #elif defined(__TASKING__)
rgrover1 361:d2405f5a4853 1215 #pragma warning restore
rgrover1 361:d2405f5a4853 1216 #else
rgrover1 361:d2405f5a4853 1217 #warning Not supported compiler type
rgrover1 361:d2405f5a4853 1218 #endif
rgrover1 361:d2405f5a4853 1219
rgrover1 361:d2405f5a4853 1220
rgrover1 361:d2405f5a4853 1221
rgrover1 361:d2405f5a4853 1222
rgrover1 361:d2405f5a4853 1223 /* ================================================================================ */
rgrover1 361:d2405f5a4853 1224 /* ================ Peripheral memory map ================ */
rgrover1 361:d2405f5a4853 1225 /* ================================================================================ */
rgrover1 361:d2405f5a4853 1226
rgrover1 361:d2405f5a4853 1227 #define NRF_POWER_BASE 0x40000000UL
rgrover1 361:d2405f5a4853 1228 #define NRF_CLOCK_BASE 0x40000000UL
rgrover1 361:d2405f5a4853 1229 #define NRF_MPU_BASE 0x40000000UL
rgrover1 361:d2405f5a4853 1230 #define NRF_PU_BASE 0x40000000UL
rgrover1 361:d2405f5a4853 1231 #define NRF_AMLI_BASE 0x40000000UL
rgrover1 361:d2405f5a4853 1232 #define NRF_RADIO_BASE 0x40001000UL
rgrover1 361:d2405f5a4853 1233 #define NRF_UART0_BASE 0x40002000UL
rgrover1 361:d2405f5a4853 1234 #define NRF_SPI0_BASE 0x40003000UL
rgrover1 361:d2405f5a4853 1235 #define NRF_TWI0_BASE 0x40003000UL
rgrover1 361:d2405f5a4853 1236 #define NRF_SPI1_BASE 0x40004000UL
rgrover1 361:d2405f5a4853 1237 #define NRF_TWI1_BASE 0x40004000UL
rgrover1 361:d2405f5a4853 1238 #define NRF_SPIS1_BASE 0x40004000UL
rgrover1 361:d2405f5a4853 1239 #define NRF_SPIM1_BASE 0x40004000UL
rgrover1 361:d2405f5a4853 1240 #define NRF_GPIOTE_BASE 0x40006000UL
rgrover1 361:d2405f5a4853 1241 #define NRF_ADC_BASE 0x40007000UL
rgrover1 361:d2405f5a4853 1242 #define NRF_TIMER0_BASE 0x40008000UL
rgrover1 361:d2405f5a4853 1243 #define NRF_TIMER1_BASE 0x40009000UL
rgrover1 361:d2405f5a4853 1244 #define NRF_TIMER2_BASE 0x4000A000UL
rgrover1 361:d2405f5a4853 1245 #define NRF_RTC0_BASE 0x4000B000UL
rgrover1 361:d2405f5a4853 1246 #define NRF_TEMP_BASE 0x4000C000UL
rgrover1 361:d2405f5a4853 1247 #define NRF_RNG_BASE 0x4000D000UL
rgrover1 361:d2405f5a4853 1248 #define NRF_ECB_BASE 0x4000E000UL
rgrover1 361:d2405f5a4853 1249 #define NRF_AAR_BASE 0x4000F000UL
rgrover1 361:d2405f5a4853 1250 #define NRF_CCM_BASE 0x4000F000UL
rgrover1 361:d2405f5a4853 1251 #define NRF_WDT_BASE 0x40010000UL
rgrover1 361:d2405f5a4853 1252 #define NRF_RTC1_BASE 0x40011000UL
rgrover1 361:d2405f5a4853 1253 #define NRF_QDEC_BASE 0x40012000UL
rgrover1 361:d2405f5a4853 1254 #define NRF_LPCOMP_BASE 0x40013000UL
rgrover1 361:d2405f5a4853 1255 #define NRF_SWI_BASE 0x40014000UL
rgrover1 361:d2405f5a4853 1256 #define NRF_NVMC_BASE 0x4001E000UL
rgrover1 361:d2405f5a4853 1257 #define NRF_PPI_BASE 0x4001F000UL
rgrover1 361:d2405f5a4853 1258 #define NRF_FICR_BASE 0x10000000UL
rgrover1 361:d2405f5a4853 1259 #define NRF_UICR_BASE 0x10001000UL
rgrover1 361:d2405f5a4853 1260 #define NRF_GPIO_BASE 0x50000000UL
rgrover1 361:d2405f5a4853 1261
rgrover1 361:d2405f5a4853 1262
rgrover1 361:d2405f5a4853 1263 /* ================================================================================ */
rgrover1 361:d2405f5a4853 1264 /* ================ Peripheral declaration ================ */
rgrover1 361:d2405f5a4853 1265 /* ================================================================================ */
rgrover1 361:d2405f5a4853 1266
rgrover1 361:d2405f5a4853 1267 #define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE)
rgrover1 361:d2405f5a4853 1268 #define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE)
rgrover1 361:d2405f5a4853 1269 #define NRF_MPU ((NRF_MPU_Type *) NRF_MPU_BASE)
rgrover1 361:d2405f5a4853 1270 #define NRF_PU ((NRF_PU_Type *) NRF_PU_BASE)
rgrover1 361:d2405f5a4853 1271 #define NRF_AMLI ((NRF_AMLI_Type *) NRF_AMLI_BASE)
rgrover1 361:d2405f5a4853 1272 #define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE)
rgrover1 361:d2405f5a4853 1273 #define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE)
rgrover1 361:d2405f5a4853 1274 #define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE)
rgrover1 361:d2405f5a4853 1275 #define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE)
rgrover1 361:d2405f5a4853 1276 #define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE)
rgrover1 361:d2405f5a4853 1277 #define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE)
rgrover1 361:d2405f5a4853 1278 #define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE)
rgrover1 361:d2405f5a4853 1279 #define NRF_SPIM1 ((NRF_SPIM_Type *) NRF_SPIM1_BASE)
rgrover1 361:d2405f5a4853 1280 #define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE)
rgrover1 361:d2405f5a4853 1281 #define NRF_ADC ((NRF_ADC_Type *) NRF_ADC_BASE)
rgrover1 361:d2405f5a4853 1282 #define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE)
rgrover1 361:d2405f5a4853 1283 #define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE)
rgrover1 361:d2405f5a4853 1284 #define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE)
rgrover1 361:d2405f5a4853 1285 #define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE)
rgrover1 361:d2405f5a4853 1286 #define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE)
rgrover1 361:d2405f5a4853 1287 #define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE)
rgrover1 361:d2405f5a4853 1288 #define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE)
rgrover1 361:d2405f5a4853 1289 #define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE)
rgrover1 361:d2405f5a4853 1290 #define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE)
rgrover1 361:d2405f5a4853 1291 #define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE)
rgrover1 361:d2405f5a4853 1292 #define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE)
rgrover1 361:d2405f5a4853 1293 #define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE)
rgrover1 361:d2405f5a4853 1294 #define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE)
rgrover1 361:d2405f5a4853 1295 #define NRF_SWI ((NRF_SWI_Type *) NRF_SWI_BASE)
rgrover1 361:d2405f5a4853 1296 #define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE)
rgrover1 361:d2405f5a4853 1297 #define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE)
rgrover1 361:d2405f5a4853 1298 #define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE)
rgrover1 361:d2405f5a4853 1299 #define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE)
rgrover1 361:d2405f5a4853 1300 #define NRF_GPIO ((NRF_GPIO_Type *) NRF_GPIO_BASE)
rgrover1 361:d2405f5a4853 1301
rgrover1 361:d2405f5a4853 1302
rgrover1 361:d2405f5a4853 1303 /** @} */ /* End of group Device_Peripheral_Registers */
rgrover1 361:d2405f5a4853 1304 /** @} */ /* End of group nRF51 */
rgrover1 361:d2405f5a4853 1305 /** @} */ /* End of group Nordic Semiconductor */
rgrover1 361:d2405f5a4853 1306
rgrover1 361:d2405f5a4853 1307 #ifdef __cplusplus
rgrover1 361:d2405f5a4853 1308 }
rgrover1 361:d2405f5a4853 1309 #endif
rgrover1 361:d2405f5a4853 1310
rgrover1 361:d2405f5a4853 1311
rgrover1 361:d2405f5a4853 1312 #endif /* nRF51_H */
rgrover1 361:d2405f5a4853 1313