Randal Riedinger
RETRO ROBOT E
Dependents: RETRO_ROBOT_SC16IS750E
Fork of
SC16IS750
by 
Wim Huiskamp
SC16IS750.h@6:b57b71c0879a, 2015-03-02 (annotated)
- Committer:
- RLRiedinger
- Date:
- Mon Mar 02 04:20:07 2015 +0000
- Revision:
- 6:b57b71c0879a
- Parent:
- 5:ff3e57bebb6a
RETRO ROBOT E
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| RLRiedinger | 6:b57b71c0879a | 1 | /* |
| RLRiedinger | 6:b57b71c0879a | 2 | * SC16IS750 I2C or SPI to UART bridge |
| wim | 3:9783b6bde958 | 3 | * v0.1 WH, Nov 2013, Sparkfun WiFly Shield code library alpha 0 used as example, Added I2C I/F and many more methods. |
| wim | 3:9783b6bde958 | 4 | * https://forum.sparkfun.com/viewtopic.php?f=13&t=21846 |
| wim | 4:12446ee9f9c8 | 5 | * v0.2 WH, Feb 2014, Added Doxygen Documentation, Added Hardware Reset pin methods. |
| wim | 4:12446ee9f9c8 | 6 | * v0.3 WH, Dec 2014, Added support for SC16IS752 dual UART. |
| wim | 5:ff3e57bebb6a | 7 | * v0.4 WH, Dec 2014, Added Repeated Start for I2C readRegister(). Set I2C clock at 100kb/s. Fixed and added some comments. |
| wim | 0:d64854a60f95 | 8 | * |
| wim | 0:d64854a60f95 | 9 | * Permission is hereby granted, free of charge, to any person obtaining a copy of this software |
| wim | 0:d64854a60f95 | 10 | * and associated documentation files (the "Software"), to deal in the Software without restriction, |
| wim | 0:d64854a60f95 | 11 | * including without limitation the rights to use, copy, modify, merge, publish, distribute, |
| wim | 0:d64854a60f95 | 12 | * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is |
| wim | 0:d64854a60f95 | 13 | * furnished to do so, subject to the following conditions: |
| wim | 0:d64854a60f95 | 14 | * |
| wim | 0:d64854a60f95 | 15 | * The above copyright notice and this permission notice shall be included in all copies or |
| wim | 0:d64854a60f95 | 16 | * substantial portions of the Software. |
| wim | 0:d64854a60f95 | 17 | * |
| wim | 0:d64854a60f95 | 18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING |
| wim | 0:d64854a60f95 | 19 | * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| wim | 0:d64854a60f95 | 20 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, |
| wim | 0:d64854a60f95 | 21 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| wim | 0:d64854a60f95 | 22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| wim | 0:d64854a60f95 | 23 | */ |
| RLRiedinger | 6:b57b71c0879a | 24 | |
| wim | 0:d64854a60f95 | 25 | #ifndef _SC16IS750_H |
| wim | 0:d64854a60f95 | 26 | #define _SC16IS750_H |
| wim | 0:d64854a60f95 | 27 | |
| RLRiedinger | 6:b57b71c0879a | 28 | #include "Stream.h" |
| wim | 3:9783b6bde958 | 29 | |
| wim | 3:9783b6bde958 | 30 | //#include <SerialBase.h> |
| wim | 3:9783b6bde958 | 31 | |
| RLRiedinger | 6:b57b71c0879a | 32 | // I2C Slaveaddresses A1 A0 |
| wim | 1:0440152c5387 | 33 | |
| RLRiedinger | 6:b57b71c0879a | 34 | #define SC16IS750_SA0 0x90 // VDD VDD |
| RLRiedinger | 6:b57b71c0879a | 35 | #define SC16IS750_SA1 0x92 // VDD VSS |
| RLRiedinger | 6:b57b71c0879a | 36 | #define SC16IS750_SA2 0x94 // VDD SCL |
| RLRiedinger | 6:b57b71c0879a | 37 | #define SC16IS750_SA3 0x95 // VDD SDA |
| RLRiedinger | 6:b57b71c0879a | 38 | #define SC16IS750_SA4 0x98 // VSS VDD |
| RLRiedinger | 6:b57b71c0879a | 39 | #define SC16IS750_SA5 0x9A // VSS VSS |
| RLRiedinger | 6:b57b71c0879a | 40 | #define SC16IS750_SA6 0x9C // VSS SCL |
| RLRiedinger | 6:b57b71c0879a | 41 | #define SC16IS750_SA7 0x9E // VSS SDA |
| RLRiedinger | 6:b57b71c0879a | 42 | #define SC16IS750_SA8 0xA0 // SCL VDD |
| RLRiedinger | 6:b57b71c0879a | 43 | #define SC16IS750_SA9 0xA2 // SCL VSS |
| RLRiedinger | 6:b57b71c0879a | 44 | #define SC16IS750_SA10 0xA4 // SCL SCL |
| RLRiedinger | 6:b57b71c0879a | 45 | #define SC16IS750_SA11 0xA6 // SCL SDA |
| RLRiedinger | 6:b57b71c0879a | 46 | #define SC16IS750_SA12 0xA8 // SDA VDD |
| RLRiedinger | 6:b57b71c0879a | 47 | #define SC16IS750_SA13 0xAA // SDA VSS |
| RLRiedinger | 6:b57b71c0879a | 48 | #define SC16IS750_SA14 0xAC // SDA SCL |
| RLRiedinger | 6:b57b71c0879a | 49 | #define SC16IS750_SA15 0xAE // SDA SDA |
| RLRiedinger | 6:b57b71c0879a | 50 | |
| RLRiedinger | 6:b57b71c0879a | 51 | // Default I2C Slaveaddress |
| RLRiedinger | 6:b57b71c0879a | 52 | |
| wim | 2:76cb93b511f2 | 53 | #define SC16IS750_DEFAULT_ADDR SC16IS750_SA0 |
| wim | 2:76cb93b511f2 | 54 | |
| RLRiedinger | 6:b57b71c0879a | 55 | /* |
| RLRiedinger | 6:b57b71c0879a | 56 | * See datasheet section 7.8 for configuring the |
| RLRiedinger | 6:b57b71c0879a | 57 | * "Programmable baud rate generator" |
| RLRiedinger | 6:b57b71c0879a | 58 | */ |
| wim | 2:76cb93b511f2 | 59 | |
| RLRiedinger | 6:b57b71c0879a | 60 | #define SC16IS750_PRESCALER_1 1 // Default prescaler after reset |
| RLRiedinger | 6:b57b71c0879a | 61 | #define SC16IS750_PRESCALER_4 4 // Selectable by setting MCR[7] |
| RLRiedinger | 6:b57b71c0879a | 62 | #define SC16IS750_PRESCALER SC16IS750_PRESCALER_1 |
| wim | 0:d64854a60f95 | 63 | |
| RLRiedinger | 6:b57b71c0879a | 64 | // Default baudrate |
| RLRiedinger | 6:b57b71c0879a | 65 | |
| wim | 3:9783b6bde958 | 66 | #define SC16IS750_DEFAULT_BAUDRATE 9600 |
| wim | 0:d64854a60f95 | 67 | |
| RLRiedinger | 6:b57b71c0879a | 68 | /* |
| RLRiedinger | 6:b57b71c0879a | 69 | * See section 8.3 of the datasheet for definitions |
| RLRiedinger | 6:b57b71c0879a | 70 | * of bits in the FIFO Control Register (FCR) |
| RLRiedinger | 6:b57b71c0879a | 71 | */ |
| wim | 1:0440152c5387 | 72 | |
| wim | 2:76cb93b511f2 | 73 | #define FCR_RX_IRQ_60 (3 << 6) |
| wim | 2:76cb93b511f2 | 74 | #define FCR_RX_IRQ_56 (2 << 6) |
| wim | 2:76cb93b511f2 | 75 | #define FCR_RX_IRQ_16 (1 << 6) |
| wim | 2:76cb93b511f2 | 76 | #define FCR_RX_IRQ_8 (0 << 6) |
| RLRiedinger | 6:b57b71c0879a | 77 | |
| RLRiedinger | 6:b57b71c0879a | 78 | // TX Level only accessible when EFR[4] is set |
| RLRiedinger | 6:b57b71c0879a | 79 | |
| wim | 2:76cb93b511f2 | 80 | #define FCR_TX_IRQ_56 (3 << 4) |
| wim | 2:76cb93b511f2 | 81 | #define FCR_TX_IRQ_32 (2 << 4) |
| wim | 2:76cb93b511f2 | 82 | #define FCR_TX_IRQ_16 (1 << 4) |
| wim | 2:76cb93b511f2 | 83 | #define FCR_TX_IRQ_8 (0 << 4) |
| RLRiedinger | 6:b57b71c0879a | 84 | |
| RLRiedinger | 6:b57b71c0879a | 85 | // #define FCR_RESERVED (1 << 3) |
| RLRiedinger | 6:b57b71c0879a | 86 | |
| wim | 3:9783b6bde958 | 87 | #define FCR_TX_FIFO_RST (1 << 2) |
| wim | 3:9783b6bde958 | 88 | #define FCR_RX_FIFO_RST (1 << 1) |
| wim | 1:0440152c5387 | 89 | #define FCR_ENABLE_FIFO (1 << 0) |
| wim | 1:0440152c5387 | 90 | |
| RLRiedinger | 6:b57b71c0879a | 91 | // FIFO size |
| RLRiedinger | 6:b57b71c0879a | 92 | |
| wim | 2:76cb93b511f2 | 93 | #define SC16IS750_FIFO_RX 64 |
| wim | 2:76cb93b511f2 | 94 | #define SC16IS750_FIFO_TX 64 |
| wim | 1:0440152c5387 | 95 | |
| RLRiedinger | 6:b57b71c0879a | 96 | /* |
| RLRiedinger | 6:b57b71c0879a | 97 | * See section 8.4 of the datasheet for definitions |
| RLRiedinger | 6:b57b71c0879a | 98 | * of bits in the Line Control Register (LCR) |
| RLRiedinger | 6:b57b71c0879a | 99 | */ |
| wim | 1:0440152c5387 | 100 | |
| wim | 2:76cb93b511f2 | 101 | #define LCR_BITS5 0x00 |
| wim | 2:76cb93b511f2 | 102 | #define LCR_BITS6 0x01 |
| wim | 2:76cb93b511f2 | 103 | #define LCR_BITS7 0x02 |
| wim | 2:76cb93b511f2 | 104 | #define LCR_BITS8 0x03 |
| wim | 1:0440152c5387 | 105 | |
| wim | 2:76cb93b511f2 | 106 | #define LCR_BITS1 0x00 |
| wim | 2:76cb93b511f2 | 107 | #define LCR_BITS2 0x04 |
| wim | 1:0440152c5387 | 108 | |
| wim | 2:76cb93b511f2 | 109 | #define LCR_NONE 0x00 |
| wim | 2:76cb93b511f2 | 110 | #define LCR_ODD 0x08 |
| wim | 2:76cb93b511f2 | 111 | #define LCR_EVEN 0x18 |
| wim | 2:76cb93b511f2 | 112 | #define LCR_FORCED1 0x28 |
| wim | 2:76cb93b511f2 | 113 | #define LCR_FORCED0 0x38 |
| wim | 2:76cb93b511f2 | 114 | |
| wim | 2:76cb93b511f2 | 115 | #define LCR_BRK_ENA 0x40 |
| wim | 2:76cb93b511f2 | 116 | #define LCR_BRK_DIS 0x00 |
| wim | 1:0440152c5387 | 117 | |
| wim | 2:76cb93b511f2 | 118 | #define LCR_ENABLE_DIV 0x80 |
| wim | 2:76cb93b511f2 | 119 | #define LCR_DISABLE_DIV 0x00 |
| wim | 2:76cb93b511f2 | 120 | |
| wim | 2:76cb93b511f2 | 121 | #define LCR_ENABLE_ENHANCED_FUNCTIONS (0xBF) |
| wim | 1:0440152c5387 | 122 | |
| RLRiedinger | 6:b57b71c0879a | 123 | /* |
| RLRiedinger | 6:b57b71c0879a | 124 | * See section 8.5 of the datasheet for definitions |
| RLRiedinger | 6:b57b71c0879a | 125 | * of bits in the Line status register (LSR) |
| RLRiedinger | 6:b57b71c0879a | 126 | */ |
| wim | 1:0440152c5387 | 127 | |
| RLRiedinger | 6:b57b71c0879a | 128 | #define LSR_DR (0x01) // Data ready in RX FIFO |
| RLRiedinger | 6:b57b71c0879a | 129 | #define LSR_OE (0x02) // Overrun error |
| RLRiedinger | 6:b57b71c0879a | 130 | #define LSR_PE (0x04) // Parity error |
| RLRiedinger | 6:b57b71c0879a | 131 | #define LSR_FE (0x08) // Framing error |
| RLRiedinger | 6:b57b71c0879a | 132 | #define LSR_BI (0x10) // Break interrupt |
| RLRiedinger | 6:b57b71c0879a | 133 | #define LSR_THRE (0x20) // Transmitter holding register (FIFO empty) |
| RLRiedinger | 6:b57b71c0879a | 134 | #define LSR_TEMT (0x40) // Transmitter empty (FIFO and TSR both empty) |
| RLRiedinger | 6:b57b71c0879a | 135 | #define LSR_FFE (0x80) // At least one PE, FE or BI in FIFO |
| wim | 1:0440152c5387 | 136 | |
| RLRiedinger | 6:b57b71c0879a | 137 | /* |
| RLRiedinger | 6:b57b71c0879a | 138 | * See section 8.6 of the datasheet for definitions |
| RLRiedinger | 6:b57b71c0879a | 139 | * of bits in the Modem control register (MCR) |
| RLRiedinger | 6:b57b71c0879a | 140 | */ |
| wim | 2:76cb93b511f2 | 141 | |
| RLRiedinger | 6:b57b71c0879a | 142 | #define MCR_MDTR (1 << 0) // Data Terminal Ready pin control. |
| RLRiedinger | 6:b57b71c0879a | 143 | #define MCR_MRTS (1 << 1) // Request to Send pin control when not in Auto RTS mode. |
| RLRiedinger | 6:b57b71c0879a | 144 | |
| wim | 3:9783b6bde958 | 145 | //MCR[2] only accessible when EFR[4] is set |
| RLRiedinger | 6:b57b71c0879a | 146 | |
| wim | 2:76cb93b511f2 | 147 | #define MCR_ENABLE_TCR_TLR (1 << 2) |
| wim | 2:76cb93b511f2 | 148 | #define MCR_ENABLE_LOOPBACK (1 << 4) |
| RLRiedinger | 6:b57b71c0879a | 149 | |
| wim | 3:9783b6bde958 | 150 | //MCR[7:5] only accessible when EFR[4] is set |
| RLRiedinger | 6:b57b71c0879a | 151 | |
| wim | 2:76cb93b511f2 | 152 | #define MCR_ENABLE_XON_ANY_CHAR (1 << 5) |
| wim | 2:76cb93b511f2 | 153 | #define MCR_ENABLE_IRDA (1 << 6) |
| wim | 2:76cb93b511f2 | 154 | #define MCR_PRESCALE_1 (0 << 7) |
| wim | 2:76cb93b511f2 | 155 | #define MCR_PRESCALE_4 (1 << 7) |
| wim | 2:76cb93b511f2 | 156 | |
| RLRiedinger | 6:b57b71c0879a | 157 | /* |
| RLRiedinger | 6:b57b71c0879a | 158 | * See section 8.7 of the datasheet for definitions |
| RLRiedinger | 6:b57b71c0879a | 159 | * of bits in the Modem status register (MSR) |
| RLRiedinger | 6:b57b71c0879a | 160 | */ |
| wim | 1:0440152c5387 | 161 | |
| RLRiedinger | 6:b57b71c0879a | 162 | #define MSR_DCTS (1 << 0) // Delta CTS - CTS Changed State |
| RLRiedinger | 6:b57b71c0879a | 163 | #define MSR_DDSR (1 << 1) // Delta DSR - DSR Changed State |
| RLRiedinger | 6:b57b71c0879a | 164 | #define MSR_DDI (1 << 2) // Delta DI - DI Changed State |
| RLRiedinger | 6:b57b71c0879a | 165 | #define MSR_DCD (1 << 3) // Delta CD - CD Changed State |
| RLRiedinger | 6:b57b71c0879a | 166 | #define MSR_CTS (1 << 4) // CTS State - Complement of NCTS pin |
| RLRiedinger | 6:b57b71c0879a | 167 | |
| wim | 3:9783b6bde958 | 168 | //MSR[7:5] only accessible when GPIO[7:4] are set as modem pin |
| RLRiedinger | 6:b57b71c0879a | 169 | |
| RLRiedinger | 6:b57b71c0879a | 170 | #define MSR_DSR (1 << 5) // DSR State - Complement of NDSR pin |
| RLRiedinger | 6:b57b71c0879a | 171 | #define MSR_RI (1 << 6) // RI State - Complement of NRI pin |
| RLRiedinger | 6:b57b71c0879a | 172 | #define MSR_CD (1 << 7) // CD State - Complement of NCD pin |
| wim | 2:76cb93b511f2 | 173 | |
| RLRiedinger | 6:b57b71c0879a | 174 | /* |
| RLRiedinger | 6:b57b71c0879a | 175 | * See section 8.8 of the datasheet for definitions |
| RLRiedinger | 6:b57b71c0879a | 176 | * of bits in the Interrupt enable register (IER) |
| RLRiedinger | 6:b57b71c0879a | 177 | */ |
| wim | 2:76cb93b511f2 | 178 | |
| RLRiedinger | 6:b57b71c0879a | 179 | #define IER_ERHRI (0x01) // Enable received data available interrupt |
| RLRiedinger | 6:b57b71c0879a | 180 | #define IER_ETHRI (0x02) // Enable transmitter holding register empty interrupt |
| RLRiedinger | 6:b57b71c0879a | 181 | #define IER_ELSI (0x04) // Enable receiver line status interrupt |
| RLRiedinger | 6:b57b71c0879a | 182 | #define IER_EMSI (0x08) // Enable modem status interrupt |
| RLRiedinger | 6:b57b71c0879a | 183 | |
| wim | 3:9783b6bde958 | 184 | //IER[7:5] only accessible when EFR[4] is set |
| wim | 1:0440152c5387 | 185 | |
| RLRiedinger | 6:b57b71c0879a | 186 | #define IER_SLEEP (0x10) // Enable sleep mode |
| RLRiedinger | 6:b57b71c0879a | 187 | #define IER_XOFFI (0x20) // Enable XOFF interrupt |
| RLRiedinger | 6:b57b71c0879a | 188 | #define IER_RTSI (0x40) // Enable RTS interrupt |
| RLRiedinger | 6:b57b71c0879a | 189 | #define IER_CTSI (0x80) // Enable CTS interrupt |
| wim | 1:0440152c5387 | 190 | |
| RLRiedinger | 6:b57b71c0879a | 191 | /* |
| RLRiedinger | 6:b57b71c0879a | 192 | * See section 8.9 of the datasheet for definitions |
| RLRiedinger | 6:b57b71c0879a | 193 | * of bits in the Interrupt identification register (IIR) |
| RLRiedinger | 6:b57b71c0879a | 194 | * Bit 0 is set to 0 if an IRQ is pending. |
| RLRiedinger | 6:b57b71c0879a | 195 | * Bits 1..5 are used to identify the IRQ source. |
| RLRiedinger | 6:b57b71c0879a | 196 | */ |
| RLRiedinger | 6:b57b71c0879a | 197 | |
| RLRiedinger | 6:b57b71c0879a | 198 | #define IIR_IRQ_NOT_PENDING (0x01) // IRQ Not Pending |
| RLRiedinger | 6:b57b71c0879a | 199 | #define IIR_TX_EMPTY (0x02) // THR Interrupt |
| RLRiedinger | 6:b57b71c0879a | 200 | #define IIR_RX_DATA (0x04) // RHR Interrupt |
| RLRiedinger | 6:b57b71c0879a | 201 | #define IIR_RX_ERROR (0x06) // Line Status Error Interrupt |
| RLRiedinger | 6:b57b71c0879a | 202 | #define IIR_RX_TIMEOUT (0x0B) // RX Timeout Interrupt |
| RLRiedinger | 6:b57b71c0879a | 203 | #define IIR_RX_XOFF (0x10) // RX XOff Interrupt |
| RLRiedinger | 6:b57b71c0879a | 204 | #define IIR_DCTS_DRTS (0x20) // Delta CTS or RTS Interrupt |
| RLRiedinger | 6:b57b71c0879a | 205 | #define IIR_DIO (0x30) // Delta GPIO pin Interrupt |
| wim | 3:9783b6bde958 | 206 | |
| wim | 2:76cb93b511f2 | 207 | #define IIR_BITS_USED (0x07) |
| wim | 2:76cb93b511f2 | 208 | |
| RLRiedinger | 6:b57b71c0879a | 209 | /* |
| RLRiedinger | 6:b57b71c0879a | 210 | * See section 8.10 of the datasheet for definitions |
| RLRiedinger | 6:b57b71c0879a | 211 | * of bits in the Enhanced Features Register (EFR) |
| RLRiedinger | 6:b57b71c0879a | 212 | */ |
| wim | 2:76cb93b511f2 | 213 | |
| wim | 2:76cb93b511f2 | 214 | #define EFR_ENABLE_CTS (1 << 7) |
| wim | 2:76cb93b511f2 | 215 | #define EFR_ENABLE_RTS (1 << 6) |
| wim | 2:76cb93b511f2 | 216 | #define EFR_ENABLE_XOFF2_CHAR_DETECT (1 << 5) |
| wim | 2:76cb93b511f2 | 217 | #define EFR_ENABLE_ENHANCED_FUNCTIONS (1 << 4) |
| RLRiedinger | 6:b57b71c0879a | 218 | |
| wim | 2:76cb93b511f2 | 219 | // EFR[3:0] are used to define Software Flow Control mode |
| RLRiedinger | 6:b57b71c0879a | 220 | |
| wim | 2:76cb93b511f2 | 221 | // See section 7.3 |
| RLRiedinger | 6:b57b71c0879a | 222 | |
| wim | 2:76cb93b511f2 | 223 | #define EFR_DISABLE_TX_FLOW_CTRL (0x0 << 2) |
| wim | 2:76cb93b511f2 | 224 | #define EFR_TX_XON2_XOFF2 (0x1 << 2) |
| wim | 2:76cb93b511f2 | 225 | #define EFR_TX_XON1_XOFF1 (0x2 << 2) |
| wim | 2:76cb93b511f2 | 226 | #define EFR_TX_XON2_1_XOFF2_1 (0x3 << 2) |
| wim | 2:76cb93b511f2 | 227 | |
| wim | 2:76cb93b511f2 | 228 | #define EFR_DISABLE_RX_FLOW_CTRL (0x0 << 0) |
| wim | 2:76cb93b511f2 | 229 | #define EFR_RX_XON2_XOFF2 (0x1 << 0) |
| wim | 2:76cb93b511f2 | 230 | #define EFR_RX_XON1_XOFF1 (0x2 << 0) |
| wim | 2:76cb93b511f2 | 231 | #define EFR_RX_XON2_1_XOFF2_1 (0x3 << 0) |
| wim | 2:76cb93b511f2 | 232 | |
| wim | 2:76cb93b511f2 | 233 | #define EFR_TX_XON2_XOFF2_RX_FLOW (0x1 << 2) | (0x3 << 0) |
| wim | 2:76cb93b511f2 | 234 | #define EFR_TX_XON1_XOFF1_RX_FLOW (0x2 << 2) | (0x3 << 0) |
| wim | 2:76cb93b511f2 | 235 | #define EFR_TX_XON2_1_XOFF2_1_RX_FLOW (0x3 << 2) | (0x3 << 0) |
| wim | 1:0440152c5387 | 236 | |
| RLRiedinger | 6:b57b71c0879a | 237 | /* |
| RLRiedinger | 6:b57b71c0879a | 238 | * See section 8.12 of the datasheet for definitions |
| RLRiedinger | 6:b57b71c0879a | 239 | * of bits in the Transmission Control Register (TCR) |
| RLRiedinger | 6:b57b71c0879a | 240 | * These levels control when RTS is asserted or de-asserted and auto RTS is enabled. Note that XON/XOFF is not supported in this lib. |
| RLRiedinger | 6:b57b71c0879a | 241 | * Trigger level to halt transmission to the device : 0..15 (meaning 0-60 with a granularity of 4) |
| RLRiedinger | 6:b57b71c0879a | 242 | * RTS is de-asserted when RX FIFO is above the set trigger level (i.e. buffer is getting full) |
| RLRiedinger | 6:b57b71c0879a | 243 | * Trigger level to resume transmission to the device : 0..15 (meaning 0-60 with a granularity of 4) |
| RLRiedinger | 6:b57b71c0879a | 244 | * RTS is asserted again when RX FIFO drops below the set trigger level (i.e. buffer has room again) |
| RLRiedinger | 6:b57b71c0879a | 245 | */ |
| wim | 1:0440152c5387 | 246 | |
| wim | 2:76cb93b511f2 | 247 | #define TCR_HALT_DEFAULT (0x0E) |
| wim | 3:9783b6bde958 | 248 | #define TCR_RESUME_DEFAULT (0x08) |
| wim | 2:76cb93b511f2 | 249 | |
| RLRiedinger | 6:b57b71c0879a | 250 | /* |
| RLRiedinger | 6:b57b71c0879a | 251 | * See section 8.12 of the datasheet for definitions |
| RLRiedinger | 6:b57b71c0879a | 252 | * Note: The device will stop transmissions from the TX FIFO when CTS is de-asserted by external receiver and |
| RLRiedinger | 6:b57b71c0879a | 253 | * auto CTS is enabled. Note that XON/XOFF is not supported in this lib. |
| RLRiedinger | 6:b57b71c0879a | 254 | */ |
| RLRiedinger | 6:b57b71c0879a | 255 | |
| RLRiedinger | 6:b57b71c0879a | 256 | /* |
| RLRiedinger | 6:b57b71c0879a | 257 | * See section 7.5 and 8.13 of the datasheet for definitions |
| RLRiedinger | 6:b57b71c0879a | 258 | * of bits in the Trigger Level Register (TLR) control when an IRQ is generated. |
| RLRiedinger | 6:b57b71c0879a | 259 | * Trigger level for TX interrupt: 0..15 (meaning 0-60 with a granularity of 4) |
| RLRiedinger | 6:b57b71c0879a | 260 | * IRQ when TX FIFO is above the set trigger level (i.e. buffer is getting full) |
| RLRiedinger | 6:b57b71c0879a | 261 | * Trigger level for RX interrupt: 0..15 (meaning 0-60 with a granularity of 4) |
| RLRiedinger | 6:b57b71c0879a | 262 | * IRQ when RX FIFO is above the set trigger level (i.e. data is waiting to be read) |
| RLRiedinger | 6:b57b71c0879a | 263 | */ |
| RLRiedinger | 6:b57b71c0879a | 264 | |
| wim | 2:76cb93b511f2 | 265 | #define TLR_TX_DEFAULT (0x0E) |
| wim | 2:76cb93b511f2 | 266 | #define TLR_RX_DEFAULT (0x04) |
| wim | 2:76cb93b511f2 | 267 | |
| RLRiedinger | 6:b57b71c0879a | 268 | /* |
| RLRiedinger | 6:b57b71c0879a | 269 | * |
| RLRiedinger | 6:b57b71c0879a | 270 | * See section 8.16, 8.17, 8.18 of the datasheet for definitions |
| RLRiedinger | 6:b57b71c0879a | 271 | * of bits in the IO Direction (IODIR), IO State (IOSTATE) and IO Interrupt Enable register (IOINTENA) |
| RLRiedinger | 6:b57b71c0879a | 272 | * |
| RLRiedinger | 6:b57b71c0879a | 273 | * Basically a direct mapping of register bits to GPIO pin. |
| RLRiedinger | 6:b57b71c0879a | 274 | */ |
| wim | 3:9783b6bde958 | 275 | |
| RLRiedinger | 6:b57b71c0879a | 276 | /* |
| RLRiedinger | 6:b57b71c0879a | 277 | * See section 8.19 of the datasheet for definitions |
| RLRiedinger | 6:b57b71c0879a | 278 | * of bits in the IO Control register (IOC) |
| RLRiedinger | 6:b57b71c0879a | 279 | * |
| RLRiedinger | 6:b57b71c0879a | 280 | * Bit 0 is set to 0 to enable latch of IO inputs. |
| RLRiedinger | 6:b57b71c0879a | 281 | * Bit 1 is set to enable GPIO[7-4] as /RI, /CD, /DTR, /DST. |
| RLRiedinger | 6:b57b71c0879a | 282 | * Bit 2 is set to enable software reset. |
| RLRiedinger | 6:b57b71c0879a | 283 | */ |
| RLRiedinger | 6:b57b71c0879a | 284 | |
| wim | 2:76cb93b511f2 | 285 | #define IOC_ENA_LATCH (0x01) |
| RLRiedinger | 6:b57b71c0879a | 286 | #define IOC_ENA_MODEM (0x02) // Set GPIO[7:4] pins to modem functions |
| wim | 3:9783b6bde958 | 287 | #define IOC_SW_RST (0x04) |
| wim | 3:9783b6bde958 | 288 | |
| RLRiedinger | 6:b57b71c0879a | 289 | /* |
| RLRiedinger | 6:b57b71c0879a | 290 | * See section 8.20 of the datasheet for definitions |
| RLRiedinger | 6:b57b71c0879a | 291 | * of bits in the Extra Features Control register (EFCR) |
| RLRiedinger | 6:b57b71c0879a | 292 | */ |
| wim | 2:76cb93b511f2 | 293 | |
| wim | 3:9783b6bde958 | 294 | #define EFCR_ENA_RS485 (0x01) |
| wim | 3:9783b6bde958 | 295 | #define EFCR_DIS_RX (0x02) |
| wim | 3:9783b6bde958 | 296 | #define EFCR_DIS_TX (0x04) |
| wim | 3:9783b6bde958 | 297 | #define EFCR_ENA_TX_RTS (0x10) |
| wim | 3:9783b6bde958 | 298 | #define EFCR_INV_RTS_RS485 (0x20) |
| wim | 3:9783b6bde958 | 299 | #define EFCR_ENA_IRDA (0x80) |
| wim | 2:76cb93b511f2 | 300 | |
| wim | 0:d64854a60f95 | 301 | // See Chapter 11 of datasheet |
| RLRiedinger | 6:b57b71c0879a | 302 | |
| wim | 2:76cb93b511f2 | 303 | #define SPI_READ_MODE_FLAG (0x80) |
| wim | 0:d64854a60f95 | 304 | |
| RLRiedinger | 6:b57b71c0879a | 305 | /* |
| RLRiedinger | 6:b57b71c0879a | 306 | * Abstract class SC16IS750 for a bridge between either SPI or I2C and a Serial port |
| RLRiedinger | 6:b57b71c0879a | 307 | * |
| RLRiedinger | 6:b57b71c0879a | 308 | * Supports both SPI and I2C interfaces through derived classes |
| RLRiedinger | 6:b57b71c0879a | 309 | * |
| RLRiedinger | 6:b57b71c0879a | 310 | * @code |
| RLRiedinger | 6:b57b71c0879a | 311 | * |
| RLRiedinger | 6:b57b71c0879a | 312 | * @endcode |
| RLRiedinger | 6:b57b71c0879a | 313 | */ |
| wim | 0:d64854a60f95 | 314 | |
| wim | 3:9783b6bde958 | 315 | //class SC16IS750 { |
| wim | 3:9783b6bde958 | 316 | //class SC16IS750 : public SerialBase, public Stream { // Wrong, Serialbase can not be constructed for NC,NC |
| RLRiedinger | 6:b57b71c0879a | 317 | |
| RLRiedinger | 6:b57b71c0879a | 318 | class SC16IS750 : public Stream { |
| RLRiedinger | 6:b57b71c0879a | 319 | |
| wim | 0:d64854a60f95 | 320 | public: |
| wim | 0:d64854a60f95 | 321 | |
| wim | 0:d64854a60f95 | 322 | // SC16IS750 Register definitions (shifted to align) |
| RLRiedinger | 6:b57b71c0879a | 323 | |
| RLRiedinger | 6:b57b71c0879a | 324 | enum RegisterName { |
| RLRiedinger | 6:b57b71c0879a | 325 | |
| wim | 1:0440152c5387 | 326 | /* |
| wim | 1:0440152c5387 | 327 | * 16750 addresses. Registers accessed when LCR[7] = 0. |
| RLRiedinger | 6:b57b71c0879a | 328 | */ |
| RLRiedinger | 6:b57b71c0879a | 329 | |
| RLRiedinger | 6:b57b71c0879a | 330 | RHR = 0x00 << 3, // Rx buffer register - Read access |
| RLRiedinger | 6:b57b71c0879a | 331 | THR = 0x00 << 3, // Tx holding register - Write access |
| RLRiedinger | 6:b57b71c0879a | 332 | IER = 0x01 << 3, // Interrupt enable reg - RD/WR access |
| wim | 1:0440152c5387 | 333 | |
| wim | 1:0440152c5387 | 334 | /* |
| wim | 1:0440152c5387 | 335 | * 16750 addresses. Registers accessed when LCR[7] = 1. |
| RLRiedinger | 6:b57b71c0879a | 336 | */ |
| RLRiedinger | 6:b57b71c0879a | 337 | |
| RLRiedinger | 6:b57b71c0879a | 338 | DLL = 0x00 << 3, // Divisor latch (LSB) - RD/WR access |
| RLRiedinger | 6:b57b71c0879a | 339 | DLH = 0x01 << 3, // Divisor latch (MSB) - RD/WR access |
| wim | 1:0440152c5387 | 340 | |
| wim | 1:0440152c5387 | 341 | /* |
| wim | 1:0440152c5387 | 342 | * 16750 addresses. IIR/FCR is accessed when LCR[7:0] <> 0xBF. |
| wim | 1:0440152c5387 | 343 | * Bit 5 of the FCR register is accessed when LCR[7] = 1. |
| RLRiedinger | 6:b57b71c0879a | 344 | */ |
| RLRiedinger | 6:b57b71c0879a | 345 | |
| RLRiedinger | 6:b57b71c0879a | 346 | IIR = 0x02 << 3, // Interrupt id. register - Read only |
| RLRiedinger | 6:b57b71c0879a | 347 | FCR = 0x02 << 3, // FIFO control register - Write only |
| RLRiedinger | 6:b57b71c0879a | 348 | |
| wim | 1:0440152c5387 | 349 | /* |
| wim | 1:0440152c5387 | 350 | * 16750 addresses. EFR is accessed when LCR[7:0] = 0xBF. |
| RLRiedinger | 6:b57b71c0879a | 351 | */ |
| RLRiedinger | 6:b57b71c0879a | 352 | |
| RLRiedinger | 6:b57b71c0879a | 353 | EFR = 0x02 << 3, // Enhanced features reg - RD/WR access |
| wim | 1:0440152c5387 | 354 | |
| wim | 1:0440152c5387 | 355 | /* |
| wim | 1:0440152c5387 | 356 | * 16750 addresses. |
| RLRiedinger | 6:b57b71c0879a | 357 | */ |
| RLRiedinger | 6:b57b71c0879a | 358 | |
| RLRiedinger | 6:b57b71c0879a | 359 | LCR = 0x03 << 3, // Line control register - RD/WR access |
| RLRiedinger | 6:b57b71c0879a | 360 | |
| wim | 1:0440152c5387 | 361 | /* |
| wim | 1:0440152c5387 | 362 | * 16750 addresses. MCR/LSR is accessed when LCR[7:0] <> 0xBF. |
| wim | 1:0440152c5387 | 363 | * Bit 7 of the MCR register is accessed when EFR[4] = 1. |
| RLRiedinger | 6:b57b71c0879a | 364 | */ |
| RLRiedinger | 6:b57b71c0879a | 365 | |
| RLRiedinger | 6:b57b71c0879a | 366 | MCR = 0x04 << 3, // Modem control register - RD/WR access |
| RLRiedinger | 6:b57b71c0879a | 367 | LSR = 0x05 << 3, // Line status register - Read only |
| wim | 1:0440152c5387 | 368 | |
| wim | 1:0440152c5387 | 369 | /* |
| wim | 1:0440152c5387 | 370 | * 16750 addresses. MSR/SPR is accessed when LCR[7:0] <> 0xBF. |
| wim | 1:0440152c5387 | 371 | * MSR, SPR register is accessed when EFR[1]=0 and MCR[2]=0. |
| RLRiedinger | 6:b57b71c0879a | 372 | */ |
| RLRiedinger | 6:b57b71c0879a | 373 | |
| RLRiedinger | 6:b57b71c0879a | 374 | MSR = 0x06 << 3, // Modem status register - Read only |
| RLRiedinger | 6:b57b71c0879a | 375 | SPR = 0x07 << 3, // Scratchpad register - RD/WR access |
| RLRiedinger | 6:b57b71c0879a | 376 | |
| wim | 1:0440152c5387 | 377 | /* |
| wim | 1:0440152c5387 | 378 | * 16750 addresses. TCR/TLR is accessed when LCR[7:0] <> 0xBF. |
| wim | 1:0440152c5387 | 379 | * TCR, TLR register is accessed when EFR[1]=1 and MCR[2]=1. |
| RLRiedinger | 6:b57b71c0879a | 380 | */ |
| RLRiedinger | 6:b57b71c0879a | 381 | |
| RLRiedinger | 6:b57b71c0879a | 382 | TCR = 0x06 << 3, // Transmission control register - RD/WR access |
| RLRiedinger | 6:b57b71c0879a | 383 | TLR = 0x07 << 3, // Trigger level register - RD/WR access |
| wim | 1:0440152c5387 | 384 | |
| wim | 1:0440152c5387 | 385 | /* |
| wim | 1:0440152c5387 | 386 | * 16750 addresses. XON, XOFF is accessed when LCR[7:0] = 0xBF. |
| RLRiedinger | 6:b57b71c0879a | 387 | */ |
| RLRiedinger | 6:b57b71c0879a | 388 | |
| RLRiedinger | 6:b57b71c0879a | 389 | XON1 = 0x04 << 3, // XON1 register - RD/WR access |
| RLRiedinger | 6:b57b71c0879a | 390 | XON2 = 0x05 << 3, // XON2 register - RD/WR access |
| RLRiedinger | 6:b57b71c0879a | 391 | XOFF1 = 0x06 << 3, // XOFF1 register - RD/WR access |
| RLRiedinger | 6:b57b71c0879a | 392 | XOFF2 = 0x07 << 3, // XOFF2 register - RD/WR access |
| wim | 1:0440152c5387 | 393 | |
| wim | 1:0440152c5387 | 394 | /* |
| wim | 1:0440152c5387 | 395 | * 16750 addresses. |
| RLRiedinger | 6:b57b71c0879a | 396 | */ |
| RLRiedinger | 6:b57b71c0879a | 397 | |
| RLRiedinger | 6:b57b71c0879a | 398 | TXLVL = 0x08 << 3, // TX FIFO Level register - Read only |
| RLRiedinger | 6:b57b71c0879a | 399 | RXLVL = 0x09 << 3, // RX FIFO Level register - Read only |
| RLRiedinger | 6:b57b71c0879a | 400 | IODIR = 0x0A << 3, // IO Pin Direction reg - RD/WR access |
| RLRiedinger | 6:b57b71c0879a | 401 | IOSTATE = 0x0B << 3, // IO Pin State reg - RD/WR access |
| RLRiedinger | 6:b57b71c0879a | 402 | IOINTENA = 0x0C << 3, // IO Interrupt Enable - RD/WR access |
| RLRiedinger | 6:b57b71c0879a | 403 | // reserved = 0x0D << 3, |
| RLRiedinger | 6:b57b71c0879a | 404 | IOCTRL = 0x0E << 3, // IO Control register - RD/WR access |
| RLRiedinger | 6:b57b71c0879a | 405 | EFCR = 0x0F << 3, // Extra features reg - RD/WR access |
| wim | 1:0440152c5387 | 406 | |
| wim | 0:d64854a60f95 | 407 | } ; |
| wim | 0:d64854a60f95 | 408 | |
| wim | 1:0440152c5387 | 409 | // This enum used to be part of SerialBase class (access via SerialBase.h). |
| RLRiedinger | 6:b57b71c0879a | 410 | // It seems not be supported anymore. The enums for Parity have moved to Serial now.. |
| RLRiedinger | 6:b57b71c0879a | 411 | |
| wim | 1:0440152c5387 | 412 | enum Flow { |
| RLRiedinger | 6:b57b71c0879a | 413 | |
| wim | 1:0440152c5387 | 414 | Disabled = 0, |
| wim | 1:0440152c5387 | 415 | RTS, |
| wim | 1:0440152c5387 | 416 | CTS, |
| wim | 1:0440152c5387 | 417 | RTSCTS |
| RLRiedinger | 6:b57b71c0879a | 418 | |
| wim | 1:0440152c5387 | 419 | }; |
| wim | 1:0440152c5387 | 420 | |
| wim | 4:12446ee9f9c8 | 421 | // SC16IS752 Channel definitions (shifted to align) |
| RLRiedinger | 6:b57b71c0879a | 422 | |
| RLRiedinger | 6:b57b71c0879a | 423 | enum ChannelName { |
| RLRiedinger | 6:b57b71c0879a | 424 | |
| wim | 4:12446ee9f9c8 | 425 | Channel_A = 0x00 << 1, |
| RLRiedinger | 6:b57b71c0879a | 426 | Channel_B = 0x01 << 1 |
| RLRiedinger | 6:b57b71c0879a | 427 | |
| wim | 4:12446ee9f9c8 | 428 | }; |
| wim | 1:0440152c5387 | 429 | |
| wim | 0:d64854a60f95 | 430 | // SC16IS750 configuration register values |
| wim | 1:0440152c5387 | 431 | // Several configuration registers are write-only. Need to save values to allow restoring. |
| RLRiedinger | 6:b57b71c0879a | 432 | |
| wim | 0:d64854a60f95 | 433 | struct SC16IS750_cfg { |
| RLRiedinger | 6:b57b71c0879a | 434 | |
| wim | 0:d64854a60f95 | 435 | char baudrate; |
| wim | 0:d64854a60f95 | 436 | char dataformat; |
| wim | 0:d64854a60f95 | 437 | char flowctrl; |
| wim | 1:0440152c5387 | 438 | char fifoformat; |
| RLRiedinger | 6:b57b71c0879a | 439 | bool fifoenable; |
| RLRiedinger | 6:b57b71c0879a | 440 | |
| wim | 0:d64854a60f95 | 441 | }; |
| wim | 0:d64854a60f95 | 442 | |
| RLRiedinger | 6:b57b71c0879a | 443 | /* |
| RLRiedinger | 6:b57b71c0879a | 444 | * Determine if there is a character available to read. |
| RLRiedinger | 6:b57b71c0879a | 445 | * This is data that's already arrived and stored in the receive |
| RLRiedinger | 6:b57b71c0879a | 446 | * buffer (which holds 64 chars). |
| RLRiedinger | 6:b57b71c0879a | 447 | * |
| RLRiedinger | 6:b57b71c0879a | 448 | * @return 1 if there is a character available to read, 0 otherwise |
| RLRiedinger | 6:b57b71c0879a | 449 | */ |
| wim | 0:d64854a60f95 | 450 | |
| wim | 1:0440152c5387 | 451 | int readable(); |
| wim | 0:d64854a60f95 | 452 | |
| RLRiedinger | 6:b57b71c0879a | 453 | /* |
| RLRiedinger | 6:b57b71c0879a | 454 | * Determine how many characters are available to read. |
| RLRiedinger | 6:b57b71c0879a | 455 | * This is data that's already arrived and stored in the receive |
| RLRiedinger | 6:b57b71c0879a | 456 | * buffer (which holds 64 chars). |
| RLRiedinger | 6:b57b71c0879a | 457 | * |
| RLRiedinger | 6:b57b71c0879a | 458 | * @return int Characters available to read |
| RLRiedinger | 6:b57b71c0879a | 459 | */ |
| RLRiedinger | 6:b57b71c0879a | 460 | |
| wim | 1:0440152c5387 | 461 | int readableCount(); |
| wim | 0:d64854a60f95 | 462 | |
| RLRiedinger | 6:b57b71c0879a | 463 | /* |
| RLRiedinger | 6:b57b71c0879a | 464 | * Determine if there is space available to write a character. |
| RLRiedinger | 6:b57b71c0879a | 465 | * @return 1 if there is a space for a character to write, 0 otherwise |
| RLRiedinger | 6:b57b71c0879a | 466 | */ |
| RLRiedinger | 6:b57b71c0879a | 467 | |
| wim | 1:0440152c5387 | 468 | int writable(); |
| wim | 2:76cb93b511f2 | 469 | |
| RLRiedinger | 6:b57b71c0879a | 470 | /* |
| RLRiedinger | 6:b57b71c0879a | 471 | * Determine how much space available for writing characters. |
| RLRiedinger | 6:b57b71c0879a | 472 | * This considers data that's already stored in the transmit |
| RLRiedinger | 6:b57b71c0879a | 473 | * buffer (which holds 64 chars). |
| RLRiedinger | 6:b57b71c0879a | 474 | * |
| RLRiedinger | 6:b57b71c0879a | 475 | * @return int character space available to write |
| RLRiedinger | 6:b57b71c0879a | 476 | */ |
| RLRiedinger | 6:b57b71c0879a | 477 | |
| wim | 1:0440152c5387 | 478 | int writableCount(); |
| wim | 1:0440152c5387 | 479 | |
| RLRiedinger | 6:b57b71c0879a | 480 | /* |
| RLRiedinger | 6:b57b71c0879a | 481 | * |
| RLRiedinger | 6:b57b71c0879a | 482 | * Read char from UART Bridge. |
| RLRiedinger | 6:b57b71c0879a | 483 | * Acts in the same manner as 'Serial.read()'. |
| RLRiedinger | 6:b57b71c0879a | 484 | * @param none |
| RLRiedinger | 6:b57b71c0879a | 485 | * @return char read or -1 if no data available. |
| RLRiedinger | 6:b57b71c0879a | 486 | */ |
| RLRiedinger | 6:b57b71c0879a | 487 | |
| wim | 1:0440152c5387 | 488 | int getc(); |
| wim | 1:0440152c5387 | 489 | |
| RLRiedinger | 6:b57b71c0879a | 490 | /* |
| RLRiedinger | 6:b57b71c0879a | 491 | * |
| RLRiedinger | 6:b57b71c0879a | 492 | * Write char to UART Bridge. Blocking when no free space in FIFO |
| RLRiedinger | 6:b57b71c0879a | 493 | * @param value char to be written |
| RLRiedinger | 6:b57b71c0879a | 494 | * @return value written |
| RLRiedinger | 6:b57b71c0879a | 495 | */ |
| RLRiedinger | 6:b57b71c0879a | 496 | |
| wim | 4:12446ee9f9c8 | 497 | int putc(int c); |
| wim | 4:12446ee9f9c8 | 498 | |
| wim | 4:12446ee9f9c8 | 499 | #if DOXYGEN_ONLY |
| RLRiedinger | 6:b57b71c0879a | 500 | |
| RLRiedinger | 6:b57b71c0879a | 501 | /* |
| RLRiedinger | 6:b57b71c0879a | 502 | * Write a formatted string to the UART Bridge. Blocking when no free space in FIFO |
| RLRiedinger | 6:b57b71c0879a | 503 | * |
| RLRiedinger | 6:b57b71c0879a | 504 | * @param format A printf-style format string, followed by the |
| RLRiedinger | 6:b57b71c0879a | 505 | * variables to use in formatting the string. |
| RLRiedinger | 6:b57b71c0879a | 506 | */ |
| RLRiedinger | 6:b57b71c0879a | 507 | |
| wim | 4:12446ee9f9c8 | 508 | int printf(const char* format, ...); |
| RLRiedinger | 6:b57b71c0879a | 509 | |
| wim | 4:12446ee9f9c8 | 510 | #endif |
| wim | 1:0440152c5387 | 511 | |
| RLRiedinger | 6:b57b71c0879a | 512 | /* |
| RLRiedinger | 6:b57b71c0879a | 513 | * |
| RLRiedinger | 6:b57b71c0879a | 514 | * Write char string to UART Bridge. Blocking when no free space in FIFO |
| RLRiedinger | 6:b57b71c0879a | 515 | * @param *str char string to be written |
| RLRiedinger | 6:b57b71c0879a | 516 | * @return none |
| RLRiedinger | 6:b57b71c0879a | 517 | */ |
| wim | 2:76cb93b511f2 | 518 | |
| wim | 3:9783b6bde958 | 519 | void writeString(const char *str); |
| wim | 3:9783b6bde958 | 520 | |
| RLRiedinger | 6:b57b71c0879a | 521 | /* |
| RLRiedinger | 6:b57b71c0879a | 522 | * Write byte array to UART Bridge. Blocking when no free space in FIFO |
| RLRiedinger | 6:b57b71c0879a | 523 | * @param *data byte array to be written |
| RLRiedinger | 6:b57b71c0879a | 524 | * @param len number of bytes to write |
| RLRiedinger | 6:b57b71c0879a | 525 | * @return none |
| RLRiedinger | 6:b57b71c0879a | 526 | */ |
| wim | 3:9783b6bde958 | 527 | |
| wim | 3:9783b6bde958 | 528 | void writeBytes(const char *data, int len); |
| wim | 0:d64854a60f95 | 529 | |
| RLRiedinger | 6:b57b71c0879a | 530 | /* |
| RLRiedinger | 6:b57b71c0879a | 531 | * Set baudrate of the serial port. |
| RLRiedinger | 6:b57b71c0879a | 532 | * @param baud integer baudrate (4800, 9600 etc) |
| RLRiedinger | 6:b57b71c0879a | 533 | * @return none |
| RLRiedinger | 6:b57b71c0879a | 534 | */ |
| RLRiedinger | 6:b57b71c0879a | 535 | |
| RLRiedinger | 6:b57b71c0879a | 536 | void baud(unsigned long SC16IS750_XTAL_FREQ = 14745600UL, int baudrate = SC16IS750_DEFAULT_BAUDRATE); |
| wim | 0:d64854a60f95 | 537 | |
| RLRiedinger | 6:b57b71c0879a | 538 | /* |
| RLRiedinger | 6:b57b71c0879a | 539 | * Set the transmission format used by the serial port. |
| RLRiedinger | 6:b57b71c0879a | 540 | * @param bits The number of bits in a word (5-8; default = 8) |
| RLRiedinger | 6:b57b71c0879a | 541 | * @param parity The parity used (Serial::None, Serial::Odd, Serial::Even, Serial::Forced1, Serial::Forced0; default = Serial::None) |
| RLRiedinger | 6:b57b71c0879a | 542 | * @param stop_bits The number of stop bits (1 or 2; default = 1) |
| RLRiedinger | 6:b57b71c0879a | 543 | * @return none |
| RLRiedinger | 6:b57b71c0879a | 544 | */ |
| RLRiedinger | 6:b57b71c0879a | 545 | |
| RLRiedinger | 6:b57b71c0879a | 546 | void format(int bits = 8, Serial::Parity parity = Serial::None, int stop_bits = 1); |
| wim | 2:76cb93b511f2 | 547 | |
| wim | 1:0440152c5387 | 548 | #if(0) |
| RLRiedinger | 6:b57b71c0879a | 549 | |
| RLRiedinger | 6:b57b71c0879a | 550 | /* |
| RLRiedinger | 6:b57b71c0879a | 551 | * Attach a function to call whenever a serial interrupt is generated |
| RLRiedinger | 6:b57b71c0879a | 552 | * |
| RLRiedinger | 6:b57b71c0879a | 553 | * @param fptr A pointer to a void function, or 0 to set as none |
| RLRiedinger | 6:b57b71c0879a | 554 | * @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty) |
| RLRiedinger | 6:b57b71c0879a | 555 | */ |
| RLRiedinger | 6:b57b71c0879a | 556 | |
| wim | 1:0440152c5387 | 557 | void attach(void (*fptr)(void), IrqType type=RxIrq); |
| wim | 1:0440152c5387 | 558 | |
| RLRiedinger | 6:b57b71c0879a | 559 | /* |
| RLRiedinger | 6:b57b71c0879a | 560 | * Attach a member function to call whenever a serial interrupt is generated |
| RLRiedinger | 6:b57b71c0879a | 561 | * |
| RLRiedinger | 6:b57b71c0879a | 562 | * @param tptr pointer to the object to call the member function on |
| RLRiedinger | 6:b57b71c0879a | 563 | * @param mptr pointer to the member function to be called |
| RLRiedinger | 6:b57b71c0879a | 564 | * @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty) |
| RLRiedinger | 6:b57b71c0879a | 565 | * @return none |
| RLRiedinger | 6:b57b71c0879a | 566 | */ |
| RLRiedinger | 6:b57b71c0879a | 567 | |
| RLRiedinger | 6:b57b71c0879a | 568 | template<typename T> |
| RLRiedinger | 6:b57b71c0879a | 569 | |
| RLRiedinger | 6:b57b71c0879a | 570 | void attach(T* tptr, void (T::*mptr)(void), IrqType type=RxIrq) { |
| RLRiedinger | 6:b57b71c0879a | 571 | |
| RLRiedinger | 6:b57b71c0879a | 572 | if ((mptr != NULL) && (tptr != NULL)) { |
| RLRiedinger | 6:b57b71c0879a | 573 | |
| RLRiedinger | 6:b57b71c0879a | 574 | _irq[type].attach(tptr, mptr); |
| RLRiedinger | 6:b57b71c0879a | 575 | serial_irq_set(&_serial, (SerialIrq)type, 1); |
| RLRiedinger | 6:b57b71c0879a | 576 | |
| RLRiedinger | 6:b57b71c0879a | 577 | } |
| RLRiedinger | 6:b57b71c0879a | 578 | |
| RLRiedinger | 6:b57b71c0879a | 579 | } |
| RLRiedinger | 6:b57b71c0879a | 580 | |
| wim | 1:0440152c5387 | 581 | #endif |
| wim | 1:0440152c5387 | 582 | |
| RLRiedinger | 6:b57b71c0879a | 583 | /* |
| RLRiedinger | 6:b57b71c0879a | 584 | * Generate a break condition on the serial line |
| RLRiedinger | 6:b57b71c0879a | 585 | * @param none |
| RLRiedinger | 6:b57b71c0879a | 586 | * @return none |
| RLRiedinger | 6:b57b71c0879a | 587 | */ |
| RLRiedinger | 6:b57b71c0879a | 588 | |
| wim | 1:0440152c5387 | 589 | void send_break(); |
| wim | 0:d64854a60f95 | 590 | |
| RLRiedinger | 6:b57b71c0879a | 591 | /* |
| RLRiedinger | 6:b57b71c0879a | 592 | * Set a break condition on the serial line |
| RLRiedinger | 6:b57b71c0879a | 593 | * @param enable break condition |
| RLRiedinger | 6:b57b71c0879a | 594 | * @return none |
| RLRiedinger | 6:b57b71c0879a | 595 | */ |
| wim | 1:0440152c5387 | 596 | |
| RLRiedinger | 6:b57b71c0879a | 597 | void set_break(bool enable = false); |
| wim | 1:0440152c5387 | 598 | |
| RLRiedinger | 6:b57b71c0879a | 599 | /* |
| RLRiedinger | 6:b57b71c0879a | 600 | * Set the flow control type on the serial port |
| RLRiedinger | 6:b57b71c0879a | 601 | * Added for compatibility with Serial Class. |
| RLRiedinger | 6:b57b71c0879a | 602 | * SC16IS750 supports only Flow, Pins can not be selected. |
| RLRiedinger | 6:b57b71c0879a | 603 | * This method sets hardware flow control levels. SC16IS750 supports XON/XOFF, but this is not implemented. |
| RLRiedinger | 6:b57b71c0879a | 604 | * |
| RLRiedinger | 6:b57b71c0879a | 605 | * @param type the flow control type (Disabled, RTS, CTS, RTSCTS) |
| RLRiedinger | 6:b57b71c0879a | 606 | * @param flow1 the first flow control pin (RTS for RTS or RTSCTS, CTS for CTS) |
| RLRiedinger | 6:b57b71c0879a | 607 | * @param flow2 the second flow control pin (CTS for RTSCTS) |
| RLRiedinger | 6:b57b71c0879a | 608 | * @return none |
| RLRiedinger | 6:b57b71c0879a | 609 | */ |
| wim | 2:76cb93b511f2 | 610 | |
| RLRiedinger | 6:b57b71c0879a | 611 | void set_flow_control(Flow type = Disabled, PinName flow1 = NC, PinName flow2 = NC); |
| wim | 2:76cb93b511f2 | 612 | |
| RLRiedinger | 6:b57b71c0879a | 613 | /* |
| RLRiedinger | 6:b57b71c0879a | 614 | * Set the RX FIFO flow control levels |
| RLRiedinger | 6:b57b71c0879a | 615 | * This method sets hardware flow control levels. SC16IS750 supports XON/XOFF, but this is not implemented. |
| RLRiedinger | 6:b57b71c0879a | 616 | * Should be called BEFORE Auto RTS is enabled. |
| RLRiedinger | 6:b57b71c0879a | 617 | * |
| RLRiedinger | 6:b57b71c0879a | 618 | * @param resume trigger level to resume transmission (0..15, meaning 0-60 with a granularity of 4) |
| RLRiedinger | 6:b57b71c0879a | 619 | * @param halt trigger level to resume transmission (0..15, meaning 0-60 with granularity of 4) |
| RLRiedinger | 6:b57b71c0879a | 620 | * @return none |
| RLRiedinger | 6:b57b71c0879a | 621 | */ |
| RLRiedinger | 6:b57b71c0879a | 622 | |
| wim | 2:76cb93b511f2 | 623 | void set_flow_triggers(int resume = TCR_RESUME_DEFAULT, int halt = TCR_HALT_DEFAULT); |
| wim | 2:76cb93b511f2 | 624 | |
| RLRiedinger | 6:b57b71c0879a | 625 | /* |
| RLRiedinger | 6:b57b71c0879a | 626 | * Set the Modem Control register |
| RLRiedinger | 6:b57b71c0879a | 627 | * This method sets prescaler, enables TCR and TLR |
| RLRiedinger | 6:b57b71c0879a | 628 | * |
| RLRiedinger | 6:b57b71c0879a | 629 | * @param none |
| RLRiedinger | 6:b57b71c0879a | 630 | * @return none |
| RLRiedinger | 6:b57b71c0879a | 631 | */ |
| wim | 2:76cb93b511f2 | 632 | |
| wim | 2:76cb93b511f2 | 633 | void set_modem_control(); |
| RLRiedinger | 6:b57b71c0879a | 634 | |
| RLRiedinger | 6:b57b71c0879a | 635 | /* |
| RLRiedinger | 6:b57b71c0879a | 636 | * |
| RLRiedinger | 6:b57b71c0879a | 637 | * Check that UART is connected and operational. |
| RLRiedinger | 6:b57b71c0879a | 638 | * @param none |
| RLRiedinger | 6:b57b71c0879a | 639 | * @return bool true when connected, false otherwise |
| RLRiedinger | 6:b57b71c0879a | 640 | */ |
| wim | 2:76cb93b511f2 | 641 | |
| wim | 0:d64854a60f95 | 642 | bool connected(); |
| wim | 0:d64854a60f95 | 643 | |
| RLRiedinger | 6:b57b71c0879a | 644 | /* |
| RLRiedinger | 6:b57b71c0879a | 645 | * FIFO control, sets TX and RX IRQ trigger levels and enables FIFO and save in _config |
| RLRiedinger | 6:b57b71c0879a | 646 | * Note FCR[5:4] (=TX_IRQ_LVL) only accessible when EFR[4] is set (enhanced functions enable) |
| RLRiedinger | 6:b57b71c0879a | 647 | * Note TLR only accessible when EFR[4] is set (enhanced functions enable) and MCR[2] is set |
| RLRiedinger | 6:b57b71c0879a | 648 | * @param none |
| RLRiedinger | 6:b57b71c0879a | 649 | * @return none |
| RLRiedinger | 6:b57b71c0879a | 650 | */ |
| wim | 2:76cb93b511f2 | 651 | |
| wim | 2:76cb93b511f2 | 652 | void set_fifo_control(); |
| wim | 2:76cb93b511f2 | 653 | |
| RLRiedinger | 6:b57b71c0879a | 654 | /* |
| RLRiedinger | 6:b57b71c0879a | 655 | * Flush the UART FIFOs while maintaining current FIFO mode. |
| RLRiedinger | 6:b57b71c0879a | 656 | * @param none |
| RLRiedinger | 6:b57b71c0879a | 657 | * @return none |
| RLRiedinger | 6:b57b71c0879a | 658 | */ |
| wim | 1:0440152c5387 | 659 | |
| wim | 1:0440152c5387 | 660 | void flush(); |
| wim | 0:d64854a60f95 | 661 | |
| RLRiedinger | 6:b57b71c0879a | 662 | /* |
| RLRiedinger | 6:b57b71c0879a | 663 | * Set direction of I/O port pins. |
| RLRiedinger | 6:b57b71c0879a | 664 | * This method is specific to the SPI-I2C UART and not found on the 16750 |
| RLRiedinger | 6:b57b71c0879a | 665 | * Note: The SC16IS752 does not have separate GPIOs for Channel_A and Channel_B. |
| RLRiedinger | 6:b57b71c0879a | 666 | * @param bits Bitpattern for I/O (1=output, 0=input) |
| RLRiedinger | 6:b57b71c0879a | 667 | * @return none |
| RLRiedinger | 6:b57b71c0879a | 668 | */ |
| wim | 1:0440152c5387 | 669 | |
| wim | 1:0440152c5387 | 670 | void ioSetDirection(unsigned char bits); |
| wim | 0:d64854a60f95 | 671 | |
| RLRiedinger | 6:b57b71c0879a | 672 | /* |
| RLRiedinger | 6:b57b71c0879a | 673 | * Set bits of I/O port pins. |
| RLRiedinger | 6:b57b71c0879a | 674 | * This method is specific to the SPI-I2C UART and not found on the 16750 |
| RLRiedinger | 6:b57b71c0879a | 675 | * Note: The SC16IS752 does not have separate GPIOs for Channel_A and Channel_B. |
| RLRiedinger | 6:b57b71c0879a | 676 | * @param bits Bitpattern for I/O (1= set output bit, 0 = clear output bit) |
| RLRiedinger | 6:b57b71c0879a | 677 | * @return none |
| RLRiedinger | 6:b57b71c0879a | 678 | */ |
| RLRiedinger | 6:b57b71c0879a | 679 | |
| wim | 1:0440152c5387 | 680 | void ioSetState(unsigned char bits); |
| wim | 1:0440152c5387 | 681 | |
| RLRiedinger | 6:b57b71c0879a | 682 | /* |
| RLRiedinger | 6:b57b71c0879a | 683 | * Get bits of I/O port pins. |
| RLRiedinger | 6:b57b71c0879a | 684 | * This method is specific to the SPI-I2C UART and not found on the 16750 |
| RLRiedinger | 6:b57b71c0879a | 685 | * Note: The SC16IS752 does not have separate GPIOs for Channel_A and Channel_B. |
| RLRiedinger | 6:b57b71c0879a | 686 | * @param none |
| RLRiedinger | 6:b57b71c0879a | 687 | * @return bits Bitpattern for I/O (1= bit set, 0 = bit cleared) |
| RLRiedinger | 6:b57b71c0879a | 688 | */ |
| RLRiedinger | 6:b57b71c0879a | 689 | |
| wim | 1:0440152c5387 | 690 | unsigned char ioGetState(); |
| wim | 1:0440152c5387 | 691 | |
| RLRiedinger | 6:b57b71c0879a | 692 | /* |
| RLRiedinger | 6:b57b71c0879a | 693 | * Software Reset SC16IS750 device. |
| RLRiedinger | 6:b57b71c0879a | 694 | * This method is specific to the SPI-I2C UART and not found on the 16750 |
| RLRiedinger | 6:b57b71c0879a | 695 | * Note: The SC16IS752 does not have separate Reset for Channel_A and Channel_B. |
| RLRiedinger | 6:b57b71c0879a | 696 | * @param none |
| RLRiedinger | 6:b57b71c0879a | 697 | * @return none |
| RLRiedinger | 6:b57b71c0879a | 698 | */ |
| wim | 1:0440152c5387 | 699 | |
| wim | 1:0440152c5387 | 700 | void swReset(); |
| wim | 1:0440152c5387 | 701 | |
| RLRiedinger | 6:b57b71c0879a | 702 | /* |
| RLRiedinger | 6:b57b71c0879a | 703 | * Hardware Reset SC16IS750 device. |
| RLRiedinger | 6:b57b71c0879a | 704 | * Pure virtual, must be declared in derived class. |
| RLRiedinger | 6:b57b71c0879a | 705 | * This method is only functional when the Reset pin has been declared and is also connected |
| RLRiedinger | 6:b57b71c0879a | 706 | * @param none |
| RLRiedinger | 6:b57b71c0879a | 707 | * @return none |
| RLRiedinger | 6:b57b71c0879a | 708 | */ |
| wim | 0:d64854a60f95 | 709 | |
| wim | 4:12446ee9f9c8 | 710 | virtual void hwReset() =0; |
| wim | 4:12446ee9f9c8 | 711 | |
| RLRiedinger | 6:b57b71c0879a | 712 | /* |
| RLRiedinger | 6:b57b71c0879a | 713 | * Write value to internal register. |
| RLRiedinger | 6:b57b71c0879a | 714 | * Pure virtual, must be declared in derived class. |
| RLRiedinger | 6:b57b71c0879a | 715 | * @param registerAddress The address of the Register (enum RegisterName) |
| RLRiedinger | 6:b57b71c0879a | 716 | * @param data The 8bit value to write |
| RLRiedinger | 6:b57b71c0879a | 717 | * @return none |
| RLRiedinger | 6:b57b71c0879a | 718 | */ |
| RLRiedinger | 6:b57b71c0879a | 719 | |
| wim | 1:0440152c5387 | 720 | virtual void writeRegister (RegisterName register_address, char data ) =0; |
| wim | 0:d64854a60f95 | 721 | |
| RLRiedinger | 6:b57b71c0879a | 722 | /* |
| RLRiedinger | 6:b57b71c0879a | 723 | * Read value from internal register. |
| RLRiedinger | 6:b57b71c0879a | 724 | * Pure virtual, must be declared in derived class. |
| RLRiedinger | 6:b57b71c0879a | 725 | * @param registerAddress The address of the Register (enum RegisterName) |
| RLRiedinger | 6:b57b71c0879a | 726 | * @return char The 8bit value read from the register |
| RLRiedinger | 6:b57b71c0879a | 727 | */ |
| RLRiedinger | 6:b57b71c0879a | 728 | |
| wim | 1:0440152c5387 | 729 | virtual char readRegister (RegisterName register_address ) =0; |
| wim | 1:0440152c5387 | 730 | |
| RLRiedinger | 6:b57b71c0879a | 731 | /* |
| RLRiedinger | 6:b57b71c0879a | 732 | * Write multiple datavalues to Transmitregister. |
| RLRiedinger | 6:b57b71c0879a | 733 | * More Efficient implementation than writing individual bytes |
| RLRiedinger | 6:b57b71c0879a | 734 | * Pure virtual, must be declared in derived class. |
| RLRiedinger | 6:b57b71c0879a | 735 | * @param char* databytes The pointer to the block of data |
| RLRiedinger | 6:b57b71c0879a | 736 | * @param len The number of bytes to write |
| RLRiedinger | 6:b57b71c0879a | 737 | * @return none |
| RLRiedinger | 6:b57b71c0879a | 738 | */ |
| RLRiedinger | 6:b57b71c0879a | 739 | |
| wim | 3:9783b6bde958 | 740 | virtual void writeDataBlock (const char *data, int len ) =0; |
| wim | 3:9783b6bde958 | 741 | |
| RLRiedinger | 6:b57b71c0879a | 742 | /* |
| RLRiedinger | 6:b57b71c0879a | 743 | * Initialise internal registers |
| RLRiedinger | 6:b57b71c0879a | 744 | * Should be in protection section. Public for testing purposes |
| RLRiedinger | 6:b57b71c0879a | 745 | * If initialisation fails this method does not return. |
| RLRiedinger | 6:b57b71c0879a | 746 | * @param none |
| RLRiedinger | 6:b57b71c0879a | 747 | * @return none |
| RLRiedinger | 6:b57b71c0879a | 748 | */ |
| wim | 0:d64854a60f95 | 749 | |
| wim | 1:0440152c5387 | 750 | void _init(); |
| wim | 1:0440152c5387 | 751 | |
| wim | 0:d64854a60f95 | 752 | protected: |
| RLRiedinger | 6:b57b71c0879a | 753 | |
| RLRiedinger | 6:b57b71c0879a | 754 | // protected is accessible to derived classes, but not to external users |
| wim | 2:76cb93b511f2 | 755 | |
| RLRiedinger | 6:b57b71c0879a | 756 | /* |
| RLRiedinger | 6:b57b71c0879a | 757 | * Constructor is protected for this abstract Class |
| RLRiedinger | 6:b57b71c0879a | 758 | */ |
| RLRiedinger | 6:b57b71c0879a | 759 | |
| wim | 1:0440152c5387 | 760 | SC16IS750(); |
| wim | 1:0440152c5387 | 761 | |
| RLRiedinger | 6:b57b71c0879a | 762 | /* |
| RLRiedinger | 6:b57b71c0879a | 763 | * Needed to implement Stream |
| RLRiedinger | 6:b57b71c0879a | 764 | * |
| RLRiedinger | 6:b57b71c0879a | 765 | * Read char from UART Bridge. |
| RLRiedinger | 6:b57b71c0879a | 766 | * Acts in the same manner as 'Serial.read()'. |
| RLRiedinger | 6:b57b71c0879a | 767 | * @param none |
| RLRiedinger | 6:b57b71c0879a | 768 | * @return char read or -1 if no data available. |
| RLRiedinger | 6:b57b71c0879a | 769 | */ |
| RLRiedinger | 6:b57b71c0879a | 770 | |
| wim | 3:9783b6bde958 | 771 | virtual int _getc() { |
| RLRiedinger | 6:b57b71c0879a | 772 | |
| wim | 3:9783b6bde958 | 773 | return getc(); |
| RLRiedinger | 6:b57b71c0879a | 774 | |
| wim | 3:9783b6bde958 | 775 | } |
| wim | 3:9783b6bde958 | 776 | |
| RLRiedinger | 6:b57b71c0879a | 777 | /* |
| RLRiedinger | 6:b57b71c0879a | 778 | * Needed to implement Stream |
| RLRiedinger | 6:b57b71c0879a | 779 | * |
| RLRiedinger | 6:b57b71c0879a | 780 | * Write char to UART Bridge. Blocking when no free space in FIFO |
| RLRiedinger | 6:b57b71c0879a | 781 | * @param value char to be written |
| RLRiedinger | 6:b57b71c0879a | 782 | * @return value written |
| RLRiedinger | 6:b57b71c0879a | 783 | */ |
| wim | 3:9783b6bde958 | 784 | |
| wim | 3:9783b6bde958 | 785 | virtual int _putc(int c) { |
| RLRiedinger | 6:b57b71c0879a | 786 | |
| RLRiedinger | 6:b57b71c0879a | 787 | return putc(c); |
| RLRiedinger | 6:b57b71c0879a | 788 | |
| wim | 3:9783b6bde958 | 789 | } |
| wim | 3:9783b6bde958 | 790 | |
| RLRiedinger | 6:b57b71c0879a | 791 | /* |
| RLRiedinger | 6:b57b71c0879a | 792 | * Needed to implement Stream |
| RLRiedinger | 6:b57b71c0879a | 793 | * |
| RLRiedinger | 6:b57b71c0879a | 794 | */ |
| RLRiedinger | 6:b57b71c0879a | 795 | |
| wim | 3:9783b6bde958 | 796 | virtual int peek() {return 0;}; |
| wim | 3:9783b6bde958 | 797 | |
| wim | 2:76cb93b511f2 | 798 | // Save config settings |
| RLRiedinger | 6:b57b71c0879a | 799 | |
| wim | 0:d64854a60f95 | 800 | SC16IS750_cfg _config; |
| wim | 0:d64854a60f95 | 801 | |
| wim | 0:d64854a60f95 | 802 | private: |
| RLRiedinger | 6:b57b71c0879a | 803 | |
| RLRiedinger | 6:b57b71c0879a | 804 | // private is not accessible to derived classes, nor external users |
| wim | 1:0440152c5387 | 805 | |
| wim | 0:d64854a60f95 | 806 | }; |
| wim | 0:d64854a60f95 | 807 | |
| RLRiedinger | 6:b57b71c0879a | 808 | /* |
| RLRiedinger | 6:b57b71c0879a | 809 | * Class SC16IS750_SPI for a bridge between SPI and a Serial port |
| wim | 0:d64854a60f95 | 810 | * |
| wim | 0:d64854a60f95 | 811 | * @code |
| wim | 0:d64854a60f95 | 812 | * #include "mbed.h" |
| wim | 0:d64854a60f95 | 813 | * #include "SC16IS750.h" |
| wim | 0:d64854a60f95 | 814 | * |
| wim | 0:d64854a60f95 | 815 | * SPI spi(PTD2, PTD3, PTD1); //MOSI, MISO, SCK |
| wim | 0:d64854a60f95 | 816 | * SC16IS750_SPI serial_spi(&spi, PTD0); |
| wim | 0:d64854a60f95 | 817 | * |
| wim | 0:d64854a60f95 | 818 | * Serial pc(USBTX,USBRX); |
| wim | 0:d64854a60f95 | 819 | * |
| wim | 0:d64854a60f95 | 820 | * int main() { |
| wim | 0:d64854a60f95 | 821 | * pc.printf("\nHello World!\n"); |
| wim | 0:d64854a60f95 | 822 | * |
| wim | 0:d64854a60f95 | 823 | * while(1) { |
| wim | 0:d64854a60f95 | 824 | * serial_spi.ioSetState(0x00); |
| wim | 0:d64854a60f95 | 825 | * wait(0.5); |
| wim | 2:76cb93b511f2 | 826 | * serial_spi.ioSetState(0xFF); |
| wim | 2:76cb93b511f2 | 827 | * wait(0.5); |
| wim | 2:76cb93b511f2 | 828 | * serial_spi.putc('*'); |
| wim | 0:d64854a60f95 | 829 | * pc.putc('*'); |
| wim | 0:d64854a60f95 | 830 | * } |
| wim | 0:d64854a60f95 | 831 | * } |
| wim | 0:d64854a60f95 | 832 | * |
| wim | 0:d64854a60f95 | 833 | * @endcode |
| wim | 0:d64854a60f95 | 834 | */ |
| RLRiedinger | 6:b57b71c0879a | 835 | |
| wim | 0:d64854a60f95 | 836 | class SC16IS750_SPI : public SC16IS750 { |
| RLRiedinger | 6:b57b71c0879a | 837 | |
| wim | 0:d64854a60f95 | 838 | public: |
| wim | 0:d64854a60f95 | 839 | |
| RLRiedinger | 6:b57b71c0879a | 840 | /* |
| RLRiedinger | 6:b57b71c0879a | 841 | * Create an SC16IS750_SPI object using a specified SPI bus and CS |
| RLRiedinger | 6:b57b71c0879a | 842 | * |
| RLRiedinger | 6:b57b71c0879a | 843 | * @param SPI &spi the SPI port to connect to |
| RLRiedinger | 6:b57b71c0879a | 844 | * @param cs Pinname of the CS pin (active low) |
| RLRiedinger | 6:b57b71c0879a | 845 | * @param rst Pinname for Reset pin (active low) Optional, Default = NC |
| RLRiedinger | 6:b57b71c0879a | 846 | */ |
| RLRiedinger | 6:b57b71c0879a | 847 | |
| wim | 4:12446ee9f9c8 | 848 | SC16IS750_SPI(SPI *spi, PinName cs, PinName rst = NC); |
| wim | 4:12446ee9f9c8 | 849 | |
| RLRiedinger | 6:b57b71c0879a | 850 | /* |
| RLRiedinger | 6:b57b71c0879a | 851 | * Destruct SC16IS750_SPI bridge object |
| RLRiedinger | 6:b57b71c0879a | 852 | * |
| RLRiedinger | 6:b57b71c0879a | 853 | * @param none |
| RLRiedinger | 6:b57b71c0879a | 854 | * @return none |
| RLRiedinger | 6:b57b71c0879a | 855 | */ |
| RLRiedinger | 6:b57b71c0879a | 856 | |
| wim | 4:12446ee9f9c8 | 857 | virtual ~SC16IS750_SPI(); |
| wim | 4:12446ee9f9c8 | 858 | |
| RLRiedinger | 6:b57b71c0879a | 859 | /* |
| RLRiedinger | 6:b57b71c0879a | 860 | * Write value to internal register. |
| RLRiedinger | 6:b57b71c0879a | 861 | * @param registerAddress The address of the Register (enum RegisterName) |
| RLRiedinger | 6:b57b71c0879a | 862 | * @param data The 8bit value to write |
| RLRiedinger | 6:b57b71c0879a | 863 | * @return none |
| RLRiedinger | 6:b57b71c0879a | 864 | */ |
| wim | 0:d64854a60f95 | 865 | |
| wim | 0:d64854a60f95 | 866 | virtual void writeRegister(SC16IS750::RegisterName registerAddress, char data); |
| wim | 0:d64854a60f95 | 867 | |
| RLRiedinger | 6:b57b71c0879a | 868 | /* |
| RLRiedinger | 6:b57b71c0879a | 869 | * Read value from internal register. |
| RLRiedinger | 6:b57b71c0879a | 870 | * @param registerAddress The address of the Register (enum RegisterName) |
| RLRiedinger | 6:b57b71c0879a | 871 | * @return char The 8bit value read from the register |
| RLRiedinger | 6:b57b71c0879a | 872 | */ |
| RLRiedinger | 6:b57b71c0879a | 873 | |
| wim | 0:d64854a60f95 | 874 | virtual char readRegister(SC16IS750::RegisterName registerAddress); |
| wim | 0:d64854a60f95 | 875 | |
| RLRiedinger | 6:b57b71c0879a | 876 | /* |
| RLRiedinger | 6:b57b71c0879a | 877 | * Write multiple datavalues to Transmitregister. |
| RLRiedinger | 6:b57b71c0879a | 878 | * More Efficient implementation than writing individual bytes |
| RLRiedinger | 6:b57b71c0879a | 879 | * Assume that previous check confirmed that the FIFO has sufficient free space to store the data |
| RLRiedinger | 6:b57b71c0879a | 880 | * |
| RLRiedinger | 6:b57b71c0879a | 881 | * @param char* databytes The pointer to the block of data |
| RLRiedinger | 6:b57b71c0879a | 882 | * @param len The number of bytes to write |
| RLRiedinger | 6:b57b71c0879a | 883 | * @return none |
| RLRiedinger | 6:b57b71c0879a | 884 | */ |
| RLRiedinger | 6:b57b71c0879a | 885 | |
| wim | 3:9783b6bde958 | 886 | virtual void writeDataBlock (const char *data, int len ); |
| wim | 3:9783b6bde958 | 887 | |
| RLRiedinger | 6:b57b71c0879a | 888 | /* |
| RLRiedinger | 6:b57b71c0879a | 889 | * Hardware Reset SC16IS750 device. |
| RLRiedinger | 6:b57b71c0879a | 890 | * This method is only functional when the Reset pin has been declared and is also connected |
| RLRiedinger | 6:b57b71c0879a | 891 | * @param none |
| RLRiedinger | 6:b57b71c0879a | 892 | * @return none |
| RLRiedinger | 6:b57b71c0879a | 893 | */ |
| RLRiedinger | 6:b57b71c0879a | 894 | |
| wim | 4:12446ee9f9c8 | 895 | virtual void hwReset(); |
| wim | 4:12446ee9f9c8 | 896 | |
| wim | 0:d64854a60f95 | 897 | protected: |
| RLRiedinger | 6:b57b71c0879a | 898 | |
| RLRiedinger | 6:b57b71c0879a | 899 | // protected is accessible to derived classes, but not to external users |
| wim | 0:d64854a60f95 | 900 | |
| wim | 0:d64854a60f95 | 901 | private: |
| RLRiedinger | 6:b57b71c0879a | 902 | |
| RLRiedinger | 6:b57b71c0879a | 903 | SPI *_spi; // SPI bus reference |
| RLRiedinger | 6:b57b71c0879a | 904 | DigitalOut _cs; // CS of SPI device (active low) |
| wim | 4:12446ee9f9c8 | 905 | |
| RLRiedinger | 6:b57b71c0879a | 906 | /* |
| RLRiedinger | 6:b57b71c0879a | 907 | * Optional Hardware Reset pin for the bridge device (active low) |
| RLRiedinger | 6:b57b71c0879a | 908 | * Default PinName value is NC |
| RLRiedinger | 6:b57b71c0879a | 909 | */ |
| RLRiedinger | 6:b57b71c0879a | 910 | |
| RLRiedinger | 6:b57b71c0879a | 911 | DigitalOut* _reset; // Reset the Bridge device (active low) |
| wim | 0:d64854a60f95 | 912 | |
| wim | 0:d64854a60f95 | 913 | }; |
| wim | 0:d64854a60f95 | 914 | |
| RLRiedinger | 6:b57b71c0879a | 915 | /* |
| RLRiedinger | 6:b57b71c0879a | 916 | * Class SC16IS750_I2C for a bridge between I2C and a Serial port |
| wim | 0:d64854a60f95 | 917 | * |
| wim | 0:d64854a60f95 | 918 | * @code |
| wim | 0:d64854a60f95 | 919 | * #include "mbed.h" |
| wim | 0:d64854a60f95 | 920 | * #include "SC16IS750.h" |
| wim | 0:d64854a60f95 | 921 | * |
| RLRiedinger | 6:b57b71c0879a | 922 | * I2C i2c(PTE0, PTE1); // SDA, SCL |
| wim | 5:ff3e57bebb6a | 923 | * SC16IS750_I2C serial_i2c(&i2c, SC16IS750_DEFAULT_ADDR); |
| wim | 0:d64854a60f95 | 924 | * |
| wim | 0:d64854a60f95 | 925 | * Serial pc(USBTX,USBRX); |
| wim | 0:d64854a60f95 | 926 | * |
| wim | 0:d64854a60f95 | 927 | * int main() { |
| wim | 0:d64854a60f95 | 928 | * pc.printf("\nHello World!\n"); |
| wim | 0:d64854a60f95 | 929 | * |
| wim | 0:d64854a60f95 | 930 | * while(1) { |
| wim | 0:d64854a60f95 | 931 | * serial_i2c.ioSetState(0x00); |
| wim | 0:d64854a60f95 | 932 | * wait(0.5); |
| wim | 2:76cb93b511f2 | 933 | * serial_i2c.ioSetState(0xFF); |
| wim | 2:76cb93b511f2 | 934 | * wait(0.5); |
| wim | 2:76cb93b511f2 | 935 | * serial_i2c.putc('*'); |
| wim | 0:d64854a60f95 | 936 | * pc.putc('*'); |
| wim | 0:d64854a60f95 | 937 | * } |
| wim | 0:d64854a60f95 | 938 | * } |
| wim | 0:d64854a60f95 | 939 | * |
| wim | 0:d64854a60f95 | 940 | * @endcode |
| wim | 0:d64854a60f95 | 941 | */ |
| RLRiedinger | 6:b57b71c0879a | 942 | |
| wim | 0:d64854a60f95 | 943 | class SC16IS750_I2C : public SC16IS750 { |
| RLRiedinger | 6:b57b71c0879a | 944 | |
| wim | 0:d64854a60f95 | 945 | public: |
| wim | 0:d64854a60f95 | 946 | |
| RLRiedinger | 6:b57b71c0879a | 947 | /* |
| RLRiedinger | 6:b57b71c0879a | 948 | * Create an SC16IS750_I2C object using a specified I2C bus and slaveaddress |
| RLRiedinger | 6:b57b71c0879a | 949 | * |
| RLRiedinger | 6:b57b71c0879a | 950 | * @param I2C &i2c the I2C port to connect to |
| RLRiedinger | 6:b57b71c0879a | 951 | * @param char deviceAddress the address of the SC16IS750 |
| RLRiedinger | 6:b57b71c0879a | 952 | * @param rst Pinname for Reset pin (active low) Optional, Default = NC |
| RLRiedinger | 6:b57b71c0879a | 953 | */ |
| RLRiedinger | 6:b57b71c0879a | 954 | |
| wim | 4:12446ee9f9c8 | 955 | SC16IS750_I2C(I2C *i2c, uint8_t deviceAddress = SC16IS750_DEFAULT_ADDR, PinName rst = NC); |
| wim | 4:12446ee9f9c8 | 956 | |
| RLRiedinger | 6:b57b71c0879a | 957 | /* |
| RLRiedinger | 6:b57b71c0879a | 958 | * Destruct SC16IS750_I2C bridge object |
| RLRiedinger | 6:b57b71c0879a | 959 | * |
| RLRiedinger | 6:b57b71c0879a | 960 | * @param none |
| RLRiedinger | 6:b57b71c0879a | 961 | * @return none |
| RLRiedinger | 6:b57b71c0879a | 962 | */ |
| wim | 4:12446ee9f9c8 | 963 | |
| wim | 4:12446ee9f9c8 | 964 | virtual ~SC16IS750_I2C(); |
| wim | 4:12446ee9f9c8 | 965 | |
| RLRiedinger | 6:b57b71c0879a | 966 | /* |
| RLRiedinger | 6:b57b71c0879a | 967 | * Write value to internal register. |
| RLRiedinger | 6:b57b71c0879a | 968 | * @param registerAddress The address of the Register (enum RegisterName) |
| RLRiedinger | 6:b57b71c0879a | 969 | * @param data The 8bit value to write |
| RLRiedinger | 6:b57b71c0879a | 970 | * @return none |
| RLRiedinger | 6:b57b71c0879a | 971 | */ |
| wim | 0:d64854a60f95 | 972 | |
| wim | 0:d64854a60f95 | 973 | virtual void writeRegister(SC16IS750::RegisterName register_address, char data ); |
| wim | 0:d64854a60f95 | 974 | |
| RLRiedinger | 6:b57b71c0879a | 975 | /* |
| RLRiedinger | 6:b57b71c0879a | 976 | * Read value from internal register. |
| RLRiedinger | 6:b57b71c0879a | 977 | * @param registerAddress The address of the Register (enum RegisterName) |
| RLRiedinger | 6:b57b71c0879a | 978 | * @return char The 8bit value read from the register |
| RLRiedinger | 6:b57b71c0879a | 979 | */ |
| RLRiedinger | 6:b57b71c0879a | 980 | |
| wim | 0:d64854a60f95 | 981 | virtual char readRegister(SC16IS750::RegisterName register_address ); |
| wim | 0:d64854a60f95 | 982 | |
| RLRiedinger | 6:b57b71c0879a | 983 | /* |
| RLRiedinger | 6:b57b71c0879a | 984 | * Write multiple datavalues to Transmitregister. |
| RLRiedinger | 6:b57b71c0879a | 985 | * More Efficient implementation than writing individual bytes |
| RLRiedinger | 6:b57b71c0879a | 986 | * Assume that previous check confirmed that the FIFO has sufficient free space to store the data |
| RLRiedinger | 6:b57b71c0879a | 987 | * Pure virtual, must be declared in derived class. |
| RLRiedinger | 6:b57b71c0879a | 988 | * @param char* databytes The pointer to the block of data |
| RLRiedinger | 6:b57b71c0879a | 989 | * @param len The number of bytes to write |
| RLRiedinger | 6:b57b71c0879a | 990 | * @return none |
| RLRiedinger | 6:b57b71c0879a | 991 | */ |
| wim | 3:9783b6bde958 | 992 | |
| wim | 3:9783b6bde958 | 993 | virtual void writeDataBlock (const char *data, int len ); |
| RLRiedinger | 6:b57b71c0879a | 994 | |
| RLRiedinger | 6:b57b71c0879a | 995 | /* |
| RLRiedinger | 6:b57b71c0879a | 996 | * Hardware Reset SC16IS750 device. |
| RLRiedinger | 6:b57b71c0879a | 997 | * This method is only functional when the Reset pin has been declared and is also connected |
| RLRiedinger | 6:b57b71c0879a | 998 | * @param none |
| RLRiedinger | 6:b57b71c0879a | 999 | * @return none |
| RLRiedinger | 6:b57b71c0879a | 1000 | */ |
| wim | 4:12446ee9f9c8 | 1001 | |
| wim | 4:12446ee9f9c8 | 1002 | virtual void hwReset(); |
| wim | 4:12446ee9f9c8 | 1003 | |
| wim | 0:d64854a60f95 | 1004 | protected: |
| RLRiedinger | 6:b57b71c0879a | 1005 | |
| RLRiedinger | 6:b57b71c0879a | 1006 | // Protected is accessible to derived classes, but not to external users |
| wim | 0:d64854a60f95 | 1007 | |
| wim | 0:d64854a60f95 | 1008 | private: |
| RLRiedinger | 6:b57b71c0879a | 1009 | |
| RLRiedinger | 6:b57b71c0879a | 1010 | I2C *_i2c; // I2C bus reference |
| RLRiedinger | 6:b57b71c0879a | 1011 | uint8_t _slaveAddress; // I2C Slave address of device |
| wim | 4:12446ee9f9c8 | 1012 | |
| RLRiedinger | 6:b57b71c0879a | 1013 | /* |
| RLRiedinger | 6:b57b71c0879a | 1014 | * Optional Hardware Reset pin for the bridge device (active low) |
| RLRiedinger | 6:b57b71c0879a | 1015 | * Default PinName value is NC |
| RLRiedinger | 6:b57b71c0879a | 1016 | */ |
| RLRiedinger | 6:b57b71c0879a | 1017 | |
| RLRiedinger | 6:b57b71c0879a | 1018 | DigitalOut* _reset; // Reset the Bridge device (active low) |
| wim | 4:12446ee9f9c8 | 1019 | |
| wim | 4:12446ee9f9c8 | 1020 | }; |
| wim | 4:12446ee9f9c8 | 1021 | |
| RLRiedinger | 6:b57b71c0879a | 1022 | /* |
| RLRiedinger | 6:b57b71c0879a | 1023 | * Class SC16IS752_SPI for a bridge between SPI and a Serial port |
| wim | 4:12446ee9f9c8 | 1024 | * |
| wim | 4:12446ee9f9c8 | 1025 | * @code |
| wim | 4:12446ee9f9c8 | 1026 | * #include "mbed.h" |
| wim | 4:12446ee9f9c8 | 1027 | * #include "SC16IS750.h" |
| wim | 4:12446ee9f9c8 | 1028 | * |
| RLRiedinger | 6:b57b71c0879a | 1029 | * SPI spi(PTD2, PTD3, PTD1); // MOSI, MISO, SCK |
| wim | 4:12446ee9f9c8 | 1030 | * SC16IS750_SPI serial_spi(&spi, PTD0, NC, SC16IS750::Channel_B); |
| wim | 4:12446ee9f9c8 | 1031 | * |
| wim | 4:12446ee9f9c8 | 1032 | * Serial pc(USBTX,USBRX); |
| wim | 4:12446ee9f9c8 | 1033 | * |
| wim | 4:12446ee9f9c8 | 1034 | * int main() { |
| wim | 4:12446ee9f9c8 | 1035 | * pc.printf("\nHello World!\n"); |
| wim | 4:12446ee9f9c8 | 1036 | * |
| wim | 4:12446ee9f9c8 | 1037 | * while(1) { |
| wim | 4:12446ee9f9c8 | 1038 | * serial_spi.ioSetState(0x00); |
| wim | 4:12446ee9f9c8 | 1039 | * wait(0.5); |
| wim | 4:12446ee9f9c8 | 1040 | * serial_spi.ioSetState(0xFF); |
| wim | 4:12446ee9f9c8 | 1041 | * wait(0.5); |
| wim | 4:12446ee9f9c8 | 1042 | * serial_spi.putc('*'); |
| wim | 4:12446ee9f9c8 | 1043 | * pc.putc('*'); |
| wim | 4:12446ee9f9c8 | 1044 | * } |
| wim | 4:12446ee9f9c8 | 1045 | * } |
| wim | 4:12446ee9f9c8 | 1046 | * |
| wim | 4:12446ee9f9c8 | 1047 | * @endcode |
| wim | 4:12446ee9f9c8 | 1048 | */ |
| RLRiedinger | 6:b57b71c0879a | 1049 | |
| wim | 4:12446ee9f9c8 | 1050 | class SC16IS752_SPI : public SC16IS750 { |
| RLRiedinger | 6:b57b71c0879a | 1051 | |
| wim | 4:12446ee9f9c8 | 1052 | public: |
| wim | 4:12446ee9f9c8 | 1053 | |
| RLRiedinger | 6:b57b71c0879a | 1054 | /* |
| RLRiedinger | 6:b57b71c0879a | 1055 | * Create an SC16IS752_SPI object using a specified SPI bus and CS |
| RLRiedinger | 6:b57b71c0879a | 1056 | * Note: The SC16IS752 does not have separate GPIOs for Channel_A and Channel_B. |
| RLRiedinger | 6:b57b71c0879a | 1057 | * Note: The SC16IS752 does not have separate Reset for Channel_A and Channel_B. |
| RLRiedinger | 6:b57b71c0879a | 1058 | * |
| RLRiedinger | 6:b57b71c0879a | 1059 | * @param SPI &spi the SPI port to connect to |
| RLRiedinger | 6:b57b71c0879a | 1060 | * @param cs Pinname of the CS pin (active low) |
| RLRiedinger | 6:b57b71c0879a | 1061 | * @param rst Pinname for Reset pin (active low) Optional, Default = NC |
| RLRiedinger | 6:b57b71c0879a | 1062 | * @param channel UART ChannelName, Default = Channel_A |
| RLRiedinger | 6:b57b71c0879a | 1063 | */ |
| RLRiedinger | 6:b57b71c0879a | 1064 | |
| wim | 4:12446ee9f9c8 | 1065 | SC16IS752_SPI(SPI *spi, PinName cs, PinName rst = NC, ChannelName channel = SC16IS750::Channel_A ); |
| wim | 4:12446ee9f9c8 | 1066 | |
| RLRiedinger | 6:b57b71c0879a | 1067 | /* |
| RLRiedinger | 6:b57b71c0879a | 1068 | * Destruct SC16IS752_SPI bridge object |
| RLRiedinger | 6:b57b71c0879a | 1069 | * |
| RLRiedinger | 6:b57b71c0879a | 1070 | * @param none |
| RLRiedinger | 6:b57b71c0879a | 1071 | * @return none |
| RLRiedinger | 6:b57b71c0879a | 1072 | */ |
| RLRiedinger | 6:b57b71c0879a | 1073 | |
| wim | 4:12446ee9f9c8 | 1074 | virtual ~SC16IS752_SPI(); |
| wim | 4:12446ee9f9c8 | 1075 | |
| RLRiedinger | 6:b57b71c0879a | 1076 | /* |
| RLRiedinger | 6:b57b71c0879a | 1077 | * Write value to internal register. |
| RLRiedinger | 6:b57b71c0879a | 1078 | * @param registerAddress The address of the Register (enum RegisterName) |
| RLRiedinger | 6:b57b71c0879a | 1079 | * @param data The 8bit value to write |
| RLRiedinger | 6:b57b71c0879a | 1080 | * @return none |
| RLRiedinger | 6:b57b71c0879a | 1081 | */ |
| wim | 4:12446ee9f9c8 | 1082 | |
| wim | 4:12446ee9f9c8 | 1083 | virtual void writeRegister(SC16IS750::RegisterName registerAddress, char data); |
| wim | 4:12446ee9f9c8 | 1084 | |
| RLRiedinger | 6:b57b71c0879a | 1085 | /* |
| RLRiedinger | 6:b57b71c0879a | 1086 | * Read value from internal register. |
| RLRiedinger | 6:b57b71c0879a | 1087 | * @param registerAddress The address of the Register (enum RegisterName) |
| RLRiedinger | 6:b57b71c0879a | 1088 | * @return char The 8bit value read from the register |
| RLRiedinger | 6:b57b71c0879a | 1089 | */ |
| RLRiedinger | 6:b57b71c0879a | 1090 | |
| wim | 4:12446ee9f9c8 | 1091 | virtual char readRegister(SC16IS750::RegisterName registerAddress); |
| wim | 4:12446ee9f9c8 | 1092 | |
| RLRiedinger | 6:b57b71c0879a | 1093 | /* |
| RLRiedinger | 6:b57b71c0879a | 1094 | * Write multiple datavalues to Transmitregister. |
| RLRiedinger | 6:b57b71c0879a | 1095 | * More Efficient implementation than writing individual bytes |
| RLRiedinger | 6:b57b71c0879a | 1096 | * Assume that previous check confirmed that the FIFO has sufficient free space to store the data |
| RLRiedinger | 6:b57b71c0879a | 1097 | * |
| RLRiedinger | 6:b57b71c0879a | 1098 | * @param char* databytes The pointer to the block of data |
| RLRiedinger | 6:b57b71c0879a | 1099 | * @param len The number of bytes to write |
| RLRiedinger | 6:b57b71c0879a | 1100 | * @return none |
| RLRiedinger | 6:b57b71c0879a | 1101 | */ |
| RLRiedinger | 6:b57b71c0879a | 1102 | |
| wim | 4:12446ee9f9c8 | 1103 | virtual void writeDataBlock (const char *data, int len ); |
| wim | 4:12446ee9f9c8 | 1104 | |
| RLRiedinger | 6:b57b71c0879a | 1105 | /* |
| RLRiedinger | 6:b57b71c0879a | 1106 | * Hardware Reset SC16IS750 device. |
| RLRiedinger | 6:b57b71c0879a | 1107 | * This method is only functional when the Reset pin has been declared and is also connected |
| RLRiedinger | 6:b57b71c0879a | 1108 | * @param none |
| RLRiedinger | 6:b57b71c0879a | 1109 | * @return none |
| RLRiedinger | 6:b57b71c0879a | 1110 | */ |
| RLRiedinger | 6:b57b71c0879a | 1111 | |
| wim | 4:12446ee9f9c8 | 1112 | virtual void hwReset(); |
| wim | 4:12446ee9f9c8 | 1113 | |
| wim | 4:12446ee9f9c8 | 1114 | protected: |
| RLRiedinger | 6:b57b71c0879a | 1115 | |
| RLRiedinger | 6:b57b71c0879a | 1116 | // protected is accessible to derived classes, but not to external users |
| wim | 4:12446ee9f9c8 | 1117 | |
| wim | 4:12446ee9f9c8 | 1118 | private: |
| RLRiedinger | 6:b57b71c0879a | 1119 | |
| wim | 4:12446ee9f9c8 | 1120 | SPI *_spi; //SPI bus reference |
| wim | 4:12446ee9f9c8 | 1121 | DigitalOut _cs; //CS of SPI device (active low) |
| wim | 4:12446ee9f9c8 | 1122 | |
| RLRiedinger | 6:b57b71c0879a | 1123 | /* |
| RLRiedinger | 6:b57b71c0879a | 1124 | * Optional Hardware Reset pin for the bridge device (active low) |
| RLRiedinger | 6:b57b71c0879a | 1125 | * Default PinName value is NC |
| RLRiedinger | 6:b57b71c0879a | 1126 | */ |
| RLRiedinger | 6:b57b71c0879a | 1127 | |
| wim | 4:12446ee9f9c8 | 1128 | DigitalOut* _reset; //Reset the Bridge device (active low) |
| wim | 4:12446ee9f9c8 | 1129 | |
| wim | 4:12446ee9f9c8 | 1130 | // Save Channel setting |
| RLRiedinger | 6:b57b71c0879a | 1131 | |
| wim | 4:12446ee9f9c8 | 1132 | ChannelName _channel; |
| RLRiedinger | 6:b57b71c0879a | 1133 | |
| wim | 4:12446ee9f9c8 | 1134 | }; |
| wim | 4:12446ee9f9c8 | 1135 | |
| RLRiedinger | 6:b57b71c0879a | 1136 | /* |
| RLRiedinger | 6:b57b71c0879a | 1137 | * Class SC16IS752_I2C for a bridge between I2C and a Serial port |
| wim | 4:12446ee9f9c8 | 1138 | * |
| wim | 4:12446ee9f9c8 | 1139 | * @code |
| wim | 4:12446ee9f9c8 | 1140 | * #include "mbed.h" |
| wim | 4:12446ee9f9c8 | 1141 | * #include "SC16IS750.h" |
| wim | 4:12446ee9f9c8 | 1142 | * |
| wim | 4:12446ee9f9c8 | 1143 | * I2C i2c(PTE0, PTE1); //SDA, SCL |
| wim | 5:ff3e57bebb6a | 1144 | * SC16IS752_I2C serial_i2c(&i2c, SC16IS750_DEFAULT_ADDR, NC, SC16IS750::Channel_A); |
| wim | 4:12446ee9f9c8 | 1145 | * |
| wim | 4:12446ee9f9c8 | 1146 | * Serial pc(USBTX,USBRX); |
| wim | 4:12446ee9f9c8 | 1147 | * |
| wim | 4:12446ee9f9c8 | 1148 | * int main() { |
| wim | 4:12446ee9f9c8 | 1149 | * pc.printf("\nHello World!\n"); |
| wim | 4:12446ee9f9c8 | 1150 | * |
| wim | 4:12446ee9f9c8 | 1151 | * while(1) { |
| wim | 4:12446ee9f9c8 | 1152 | * serial_i2c.ioSetState(0x00); |
| wim | 4:12446ee9f9c8 | 1153 | * wait(0.5); |
| wim | 4:12446ee9f9c8 | 1154 | * serial_i2c.ioSetState(0xFF); |
| wim | 4:12446ee9f9c8 | 1155 | * wait(0.5); |
| wim | 4:12446ee9f9c8 | 1156 | * serial_i2c.putc('*'); |
| wim | 4:12446ee9f9c8 | 1157 | * pc.putc('*'); |
| wim | 4:12446ee9f9c8 | 1158 | * } |
| wim | 4:12446ee9f9c8 | 1159 | * } |
| wim | 4:12446ee9f9c8 | 1160 | * |
| wim | 4:12446ee9f9c8 | 1161 | * @endcode |
| wim | 4:12446ee9f9c8 | 1162 | */ |
| RLRiedinger | 6:b57b71c0879a | 1163 | |
| wim | 4:12446ee9f9c8 | 1164 | class SC16IS752_I2C : public SC16IS750 { |
| RLRiedinger | 6:b57b71c0879a | 1165 | |
| wim | 4:12446ee9f9c8 | 1166 | public: |
| wim | 4:12446ee9f9c8 | 1167 | |
| RLRiedinger | 6:b57b71c0879a | 1168 | /* |
| RLRiedinger | 6:b57b71c0879a | 1169 | * Create an SC16IS752_I2C object using a specified I2C bus, slaveaddress and Channel |
| RLRiedinger | 6:b57b71c0879a | 1170 | * Note: The SC16IS752 does not have separate GPIOs for Channel_A and Channel_B. |
| RLRiedinger | 6:b57b71c0879a | 1171 | * Note: The SC16IS752 does not have separate Reset for Channel_A and Channel_B. |
| RLRiedinger | 6:b57b71c0879a | 1172 | * |
| RLRiedinger | 6:b57b71c0879a | 1173 | * @param I2C &i2c the I2C port to connect to |
| RLRiedinger | 6:b57b71c0879a | 1174 | * @param char deviceAddress the address of the SC16IS750 |
| RLRiedinger | 6:b57b71c0879a | 1175 | * @param rst Pinname for Reset pin (active low) Optional, Default = NC |
| RLRiedinger | 6:b57b71c0879a | 1176 | * @param channel UART ChannelName, Default = Channel_A |
| RLRiedinger | 6:b57b71c0879a | 1177 | */ |
| RLRiedinger | 6:b57b71c0879a | 1178 | |
| wim | 4:12446ee9f9c8 | 1179 | SC16IS752_I2C(I2C *i2c, uint8_t deviceAddress = SC16IS750_DEFAULT_ADDR, PinName rst = NC, ChannelName channel = SC16IS750::Channel_A); |
| wim | 4:12446ee9f9c8 | 1180 | |
| RLRiedinger | 6:b57b71c0879a | 1181 | /* |
| RLRiedinger | 6:b57b71c0879a | 1182 | * Destruct SC16IS752_I2C bridge object |
| RLRiedinger | 6:b57b71c0879a | 1183 | * |
| RLRiedinger | 6:b57b71c0879a | 1184 | * @param none |
| RLRiedinger | 6:b57b71c0879a | 1185 | * @return none |
| RLRiedinger | 6:b57b71c0879a | 1186 | */ |
| wim | 4:12446ee9f9c8 | 1187 | |
| wim | 4:12446ee9f9c8 | 1188 | virtual ~SC16IS752_I2C(); |
| wim | 4:12446ee9f9c8 | 1189 | |
| RLRiedinger | 6:b57b71c0879a | 1190 | /* |
| RLRiedinger | 6:b57b71c0879a | 1191 | * Write value to internal register. |
| RLRiedinger | 6:b57b71c0879a | 1192 | * @param registerAddress The address of the Register (enum RegisterName) |
| RLRiedinger | 6:b57b71c0879a | 1193 | * @param data The 8bit value to write |
| RLRiedinger | 6:b57b71c0879a | 1194 | * @return none |
| RLRiedinger | 6:b57b71c0879a | 1195 | */ |
| wim | 4:12446ee9f9c8 | 1196 | |
| wim | 4:12446ee9f9c8 | 1197 | virtual void writeRegister(SC16IS750::RegisterName register_address, char data ); |
| wim | 4:12446ee9f9c8 | 1198 | |
| RLRiedinger | 6:b57b71c0879a | 1199 | /* |
| RLRiedinger | 6:b57b71c0879a | 1200 | * Read value from internal register. |
| RLRiedinger | 6:b57b71c0879a | 1201 | * @param registerAddress The address of the Register (enum RegisterName) |
| RLRiedinger | 6:b57b71c0879a | 1202 | * @return char The 8bit value read from the register |
| RLRiedinger | 6:b57b71c0879a | 1203 | */ |
| RLRiedinger | 6:b57b71c0879a | 1204 | |
| wim | 4:12446ee9f9c8 | 1205 | virtual char readRegister(SC16IS750::RegisterName register_address ); |
| wim | 4:12446ee9f9c8 | 1206 | |
| RLRiedinger | 6:b57b71c0879a | 1207 | /* |
| RLRiedinger | 6:b57b71c0879a | 1208 | * Write multiple datavalues to Transmitregister. |
| RLRiedinger | 6:b57b71c0879a | 1209 | * More Efficient implementation than writing individual bytes |
| RLRiedinger | 6:b57b71c0879a | 1210 | * Assume that previous check confirmed that the FIFO has sufficient free space to store the data |
| RLRiedinger | 6:b57b71c0879a | 1211 | * Pure virtual, must be declared in derived class. |
| RLRiedinger | 6:b57b71c0879a | 1212 | * @param char* databytes The pointer to the block of data |
| RLRiedinger | 6:b57b71c0879a | 1213 | * @param len The number of bytes to write |
| RLRiedinger | 6:b57b71c0879a | 1214 | * @return none |
| RLRiedinger | 6:b57b71c0879a | 1215 | */ |
| wim | 4:12446ee9f9c8 | 1216 | |
| wim | 4:12446ee9f9c8 | 1217 | virtual void writeDataBlock (const char *data, int len ); |
| wim | 4:12446ee9f9c8 | 1218 | |
| RLRiedinger | 6:b57b71c0879a | 1219 | /* |
| RLRiedinger | 6:b57b71c0879a | 1220 | * Hardware Reset SC16IS752 device. |
| RLRiedinger | 6:b57b71c0879a | 1221 | * This method is only functional when the Reset pin has been declared and is also connected |
| RLRiedinger | 6:b57b71c0879a | 1222 | * @param none |
| RLRiedinger | 6:b57b71c0879a | 1223 | * @return none |
| RLRiedinger | 6:b57b71c0879a | 1224 | */ |
| wim | 4:12446ee9f9c8 | 1225 | |
| wim | 4:12446ee9f9c8 | 1226 | virtual void hwReset(); |
| wim | 4:12446ee9f9c8 | 1227 | |
| wim | 4:12446ee9f9c8 | 1228 | protected: |
| RLRiedinger | 6:b57b71c0879a | 1229 | |
| RLRiedinger | 6:b57b71c0879a | 1230 | // protected is accessible to derived classes, but not to external users |
| wim | 4:12446ee9f9c8 | 1231 | |
| wim | 4:12446ee9f9c8 | 1232 | private: |
| RLRiedinger | 6:b57b71c0879a | 1233 | |
| RLRiedinger | 6:b57b71c0879a | 1234 | I2C *_i2c; // I2C bus reference |
| RLRiedinger | 6:b57b71c0879a | 1235 | uint8_t _slaveAddress; // I2C Slave address of device |
| wim | 4:12446ee9f9c8 | 1236 | |
| RLRiedinger | 6:b57b71c0879a | 1237 | /* |
| RLRiedinger | 6:b57b71c0879a | 1238 | * Optional Hardware Reset pin for the bridge device (active low) |
| RLRiedinger | 6:b57b71c0879a | 1239 | * Default PinName value is NC |
| RLRiedinger | 6:b57b71c0879a | 1240 | */ |
| RLRiedinger | 6:b57b71c0879a | 1241 | |
| RLRiedinger | 6:b57b71c0879a | 1242 | DigitalOut* _reset; // Reset the Bridge device (active low) |
| wim | 4:12446ee9f9c8 | 1243 | |
| wim | 4:12446ee9f9c8 | 1244 | // Save Channel setting |
| RLRiedinger | 6:b57b71c0879a | 1245 | |
| wim | 4:12446ee9f9c8 | 1246 | ChannelName _channel; |
| wim | 4:12446ee9f9c8 | 1247 | |
| wim | 0:d64854a60f95 | 1248 | }; |
| wim | 0:d64854a60f95 | 1249 | |
| wim | 0:d64854a60f95 | 1250 | #endif // _SC16IS750_H |