Randal Riedinger / SC16IS750

RETRO ROBOT E

Dependents:   RETRO_ROBOT_SC16IS750E

Fork of SC16IS750 by Wim Huiskamp

SC16IS750.h@2:76cb93b511f2, 2014-02-13 (annotated)

Committer:
wim
Date:
Thu Feb 13 17:12:02 2014 +0000
Revision:
2:76cb93b511f2
Parent:
1:0440152c5387
Child:
3:9783b6bde958
Testversion 2

Who changed what in which revision?

UserRevisionLine numberNew contents of line
wim 0:d64854a60f95 1 /* SC16IS750 interface
wim 2:76cb93b511f2 2 * v0.1 WH, Nov 2013, Sparkfun Libs used as example. Added I2C I/F and many more methods
wim 0:d64854a60f95 3 *
wim 0:d64854a60f95 4 * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
wim 0:d64854a60f95 5 * and associated documentation files (the "Software"), to deal in the Software without restriction,
wim 0:d64854a60f95 6 * including without limitation the rights to use, copy, modify, merge, publish, distribute,
wim 0:d64854a60f95 7 * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is
wim 0:d64854a60f95 8 * furnished to do so, subject to the following conditions:
wim 0:d64854a60f95 9 *
wim 0:d64854a60f95 10 * The above copyright notice and this permission notice shall be included in all copies or
wim 0:d64854a60f95 11 * substantial portions of the Software.
wim 0:d64854a60f95 12 *
wim 0:d64854a60f95 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
wim 0:d64854a60f95 14 * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
wim 0:d64854a60f95 15 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
wim 0:d64854a60f95 16 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
wim 0:d64854a60f95 17 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
wim 0:d64854a60f95 18 */
wim 0:d64854a60f95 19 #ifndef _SC16IS750_H
wim 0:d64854a60f95 20 #define _SC16IS750_H
wim 0:d64854a60f95 21
wim 1:0440152c5387 22 //I2C Slaveaddresses A1 A0
wim 2:76cb93b511f2 23 #define SC16IS750_SA0 0x90 /* VDD VDD */
wim 2:76cb93b511f2 24 #define SC16IS750_SA1 0x92 /* VDD VSS */
wim 2:76cb93b511f2 25 #define SC16IS750_SA2 0x94 /* VDD SCL */
wim 2:76cb93b511f2 26 #define SC16IS750_SA3 0x95 /* VDD SDA */
wim 2:76cb93b511f2 27 #define SC16IS750_SA4 0x98 /* VSS VDD */
wim 2:76cb93b511f2 28 #define SC16IS750_SA5 0x9A /* VSS VSS */
wim 2:76cb93b511f2 29 #define SC16IS750_SA6 0x9C /* VSS SCL */
wim 2:76cb93b511f2 30 #define SC16IS750_SA7 0x9E /* VSS SDA */
wim 2:76cb93b511f2 31 #define SC16IS750_SA8 0xA0 /* SCL VDD */
wim 2:76cb93b511f2 32 #define SC16IS750_SA9 0xA2 /* SCL VSS */
wim 2:76cb93b511f2 33 #define SC16IS750_SA10 0xA4 /* SCL SCL */
wim 2:76cb93b511f2 34 #define SC16IS750_SA11 0xA6 /* SCL SDA */
wim 2:76cb93b511f2 35 #define SC16IS750_SA12 0xA8 /* SDA VDD */
wim 2:76cb93b511f2 36 #define SC16IS750_SA13 0xAA /* SDA VSS */
wim 2:76cb93b511f2 37 #define SC16IS750_SA14 0xAC /* SDA SCL */
wim 2:76cb93b511f2 38 #define SC16IS750_SA15 0xAE /* SDA SDA */
wim 1:0440152c5387 39
wim 0:d64854a60f95 40 //Default I2C Slaveaddress
wim 2:76cb93b511f2 41 #define SC16IS750_DEFAULT_ADDR SC16IS750_SA0
wim 2:76cb93b511f2 42
wim 2:76cb93b511f2 43
wim 2:76cb93b511f2 44 /** See datasheet section 7.8 for configuring the
wim 2:76cb93b511f2 45 * "Programmable baud rate generator"
wim 2:76cb93b511f2 46 */
wim 2:76cb93b511f2 47 #define SC16IS750_XTAL_FREQ 14745600UL /* On-board crystal (New mid-2010 Version) */
wim 2:76cb93b511f2 48 #define SC16IS750_PRESCALER_1 1 /* Default prescaler after reset */
wim 2:76cb93b511f2 49 #define SC16IS750_PRESCALER_4 4 /* Selectable by setting MCR[7] */
wim 2:76cb93b511f2 50 #define SC16IS750_PRESCALER SC16IS750_PRESCALER_1
wim 2:76cb93b511f2 51 #define SC16IS750_BAUDRATE_DIVISOR(baud) ((SC16IS750_XTAL_FREQ/SC16IS750_PRESCALER)/(baud*16UL))
wim 0:d64854a60f95 52
wim 0:d64854a60f95 53 //Default baudrate
wim 2:76cb93b511f2 54 #define SC16IS750_DEFAULT_BAUDRATE 9600
wim 0:d64854a60f95 55
wim 1:0440152c5387 56
wim 2:76cb93b511f2 57 /** See section 8.3 of the datasheet for definitions
wim 2:76cb93b511f2 58 * of bits in the FIFO Control Register (FCR)
wim 2:76cb93b511f2 59 */
wim 2:76cb93b511f2 60 #define FCR_RX_IRQ_60 (3 << 6)
wim 2:76cb93b511f2 61 #define FCR_RX_IRQ_56 (2 << 6)
wim 2:76cb93b511f2 62 #define FCR_RX_IRQ_16 (1 << 6)
wim 2:76cb93b511f2 63 #define FCR_RX_IRQ_8 (0 << 6)
wim 2:76cb93b511f2 64 //TX Level only accessible when EFR[4] is set
wim 2:76cb93b511f2 65 #define FCR_TX_IRQ_56 (3 << 4)
wim 2:76cb93b511f2 66 #define FCR_TX_IRQ_32 (2 << 4)
wim 2:76cb93b511f2 67 #define FCR_TX_IRQ_16 (1 << 4)
wim 2:76cb93b511f2 68 #define FCR_TX_IRQ_8 (0 << 4)
wim 2:76cb93b511f2 69 //#define FCR_RESERVED (1 << 3)
wim 1:0440152c5387 70 #define FCR_TXFIFO_RST (1 << 2)
wim 1:0440152c5387 71 #define FCR_RXFIFO_RST (1 << 1)
wim 1:0440152c5387 72 #define FCR_ENABLE_FIFO (1 << 0)
wim 1:0440152c5387 73
wim 2:76cb93b511f2 74 //FIFO size
wim 2:76cb93b511f2 75 #define SC16IS750_FIFO_RX 64
wim 2:76cb93b511f2 76 #define SC16IS750_FIFO_TX 64
wim 1:0440152c5387 77
wim 1:0440152c5387 78
wim 2:76cb93b511f2 79 /** See section 8.4 of the datasheet for definitions
wim 2:76cb93b511f2 80 * of bits in the Line Control Register (LCR)
wim 2:76cb93b511f2 81 */
wim 2:76cb93b511f2 82 #define LCR_BITS5 0x00
wim 2:76cb93b511f2 83 #define LCR_BITS6 0x01
wim 2:76cb93b511f2 84 #define LCR_BITS7 0x02
wim 2:76cb93b511f2 85 #define LCR_BITS8 0x03
wim 1:0440152c5387 86
wim 2:76cb93b511f2 87 #define LCR_BITS1 0x00
wim 2:76cb93b511f2 88 #define LCR_BITS2 0x04
wim 1:0440152c5387 89
wim 2:76cb93b511f2 90 #define LCR_NONE 0x00
wim 2:76cb93b511f2 91 #define LCR_ODD 0x08
wim 2:76cb93b511f2 92 #define LCR_EVEN 0x18
wim 2:76cb93b511f2 93 #define LCR_FORCED1 0x28
wim 2:76cb93b511f2 94 #define LCR_FORCED0 0x38
wim 2:76cb93b511f2 95
wim 2:76cb93b511f2 96 #define LCR_BRK_ENA 0x40
wim 2:76cb93b511f2 97 #define LCR_BRK_DIS 0x00
wim 1:0440152c5387 98
wim 2:76cb93b511f2 99 #define LCR_ENABLE_DIV 0x80
wim 2:76cb93b511f2 100 #define LCR_DISABLE_DIV 0x00
wim 2:76cb93b511f2 101
wim 2:76cb93b511f2 102 #define LCR_ENABLE_ENHANCED_FUNCTIONS (0xBF)
wim 1:0440152c5387 103
wim 1:0440152c5387 104
wim 2:76cb93b511f2 105 /** See section 8.5 of the datasheet for definitions
wim 2:76cb93b511f2 106 * of bits in the Line status register (LSR)
wim 2:76cb93b511f2 107 */
wim 1:0440152c5387 108 #define LSR_DR (0x01) /* Data ready */
wim 1:0440152c5387 109 #define LSR_OE (0x02) /* Overrun error */
wim 1:0440152c5387 110 #define LSR_PE (0x04) /* Parity error */
wim 1:0440152c5387 111 #define LSR_FE (0x08) /* Framing error */
wim 1:0440152c5387 112 #define LSR_BI (0x10) /* Break interrupt */
wim 1:0440152c5387 113 #define LSR_THRE (0x20) /* Transmitter holding register (FIFO empty) */
wim 1:0440152c5387 114 #define LSR_TEMT (0x40) /* Transmitter empty (FIFO and TSR both empty) */
wim 2:76cb93b511f2 115 #define LSR_FFE (0x80) /* At least one PE, FE or BI in FIFO */
wim 1:0440152c5387 116
wim 2:76cb93b511f2 117
wim 2:76cb93b511f2 118 /** See section 8.6 of the datasheet for definitions
wim 2:76cb93b511f2 119 * of bits in the Modem control register (MCR)
wim 2:76cb93b511f2 120 */
wim 2:76cb93b511f2 121 #define MCR_MDTR (1 << 0) /* Data Terminal Ready pin control. */
wim 2:76cb93b511f2 122 #define MCR_MRTS (1 << 1) /* Request to Send pin control when not in Auto RTS mode.*/
wim 2:76cb93b511f2 123 #define MCR_ENABLE_TCR_TLR (1 << 2)
wim 2:76cb93b511f2 124 #define MCR_ENABLE_LOOPBACK (1 << 4)
wim 2:76cb93b511f2 125 #define MCR_ENABLE_XON_ANY_CHAR (1 << 5)
wim 2:76cb93b511f2 126 #define MCR_ENABLE_IRDA (1 << 6)
wim 2:76cb93b511f2 127 #define MCR_PRESCALE_1 (0 << 7)
wim 2:76cb93b511f2 128 #define MCR_PRESCALE_4 (1 << 7)
wim 2:76cb93b511f2 129
wim 1:0440152c5387 130
wim 2:76cb93b511f2 131 /** See section 8.7 of the datasheet for definitions
wim 2:76cb93b511f2 132 * of bits in the Modem status register (MSR)
wim 2:76cb93b511f2 133 */
wim 2:76cb93b511f2 134
wim 2:76cb93b511f2 135
wim 2:76cb93b511f2 136 /** See section 8.8 of the datasheet for definitions
wim 2:76cb93b511f2 137 * of bits in the Interrupt enable register (IER)
wim 2:76cb93b511f2 138 */
wim 2:76cb93b511f2 139 #define IER_ERBI (0x01) /* Enable received data available interrupt */
wim 2:76cb93b511f2 140 #define IER_ETBEI (0x02) /* Enable transmitter holding register empty interrupt */
wim 2:76cb93b511f2 141 #define IER_ELSI (0x04) /* Enable receiver line status interrupt */
wim 2:76cb93b511f2 142 #define IER_EDSSI (0x08) /* Enable modem status interrupt */
wim 2:76cb93b511f2 143 #define IER_SLEEP (0x10) /* Enable sleep mode */
wim 1:0440152c5387 144
wim 1:0440152c5387 145
wim 2:76cb93b511f2 146 /** See section 8.9 of the datasheet for definitions
wim 2:76cb93b511f2 147 * of bits in the Interrupt identification register (IIR)
wim 2:76cb93b511f2 148 * Bit 0 is set to 0 if an IT is pending.
wim 2:76cb93b511f2 149 * Bits 1 and 2 are used to identify the IT.
wim 2:76cb93b511f2 150 */
wim 2:76cb93b511f2 151 #define IIR_BITS_USED (0x07)
wim 2:76cb93b511f2 152 #define IIR_IT_NOT_PENDING (0x01)
wim 2:76cb93b511f2 153 #define IIR_RX_DATA (0x04)
wim 2:76cb93b511f2 154 #define IIR_TX_EMPTY (0x02)
wim 2:76cb93b511f2 155 #define IIR_MODEM_STATUS (0x00)
wim 2:76cb93b511f2 156
wim 2:76cb93b511f2 157
wim 2:76cb93b511f2 158 /** See section 8.10 of the datasheet for definitions
wim 2:76cb93b511f2 159 * of bits in the Enhanced Features Register (EFR)
wim 2:76cb93b511f2 160 */
wim 2:76cb93b511f2 161 #define EFR_ENABLE_CTS (1 << 7)
wim 2:76cb93b511f2 162 #define EFR_ENABLE_RTS (1 << 6)
wim 2:76cb93b511f2 163 #define EFR_ENABLE_XOFF2_CHAR_DETECT (1 << 5)
wim 2:76cb93b511f2 164 #define EFR_ENABLE_ENHANCED_FUNCTIONS (1 << 4)
wim 2:76cb93b511f2 165 // EFR[3:0] are used to define Software Flow Control mode
wim 2:76cb93b511f2 166 // See section 7.3
wim 2:76cb93b511f2 167 #define EFR_DISABLE_TX_FLOW_CTRL (0x0 << 2)
wim 2:76cb93b511f2 168 #define EFR_TX_XON2_XOFF2 (0x1 << 2)
wim 2:76cb93b511f2 169 #define EFR_TX_XON1_XOFF1 (0x2 << 2)
wim 2:76cb93b511f2 170 #define EFR_TX_XON2_1_XOFF2_1 (0x3 << 2)
wim 2:76cb93b511f2 171
wim 2:76cb93b511f2 172 #define EFR_DISABLE_RX_FLOW_CTRL (0x0 << 0)
wim 2:76cb93b511f2 173 #define EFR_RX_XON2_XOFF2 (0x1 << 0)
wim 2:76cb93b511f2 174 #define EFR_RX_XON1_XOFF1 (0x2 << 0)
wim 2:76cb93b511f2 175 #define EFR_RX_XON2_1_XOFF2_1 (0x3 << 0)
wim 2:76cb93b511f2 176
wim 2:76cb93b511f2 177 #define EFR_TX_XON2_XOFF2_RX_FLOW (0x1 << 2) | (0x3 << 0)
wim 2:76cb93b511f2 178 #define EFR_TX_XON1_XOFF1_RX_FLOW (0x2 << 2) | (0x3 << 0)
wim 2:76cb93b511f2 179 #define EFR_TX_XON2_1_XOFF2_1_RX_FLOW (0x3 << 2) | (0x3 << 0)
wim 1:0440152c5387 180
wim 1:0440152c5387 181
wim 1:0440152c5387 182
wim 2:76cb93b511f2 183 /** See section 8.12 of the datasheet for definitions
wim 2:76cb93b511f2 184 * of bits in the Transmission Control Register (TCR)
wim 2:76cb93b511f2 185 * Trigger level to halt transmission: 0..15 (meaning 0-60 with a granularity of 4)
wim 2:76cb93b511f2 186 * Trigger level to resume transmission: 0..15 (meaning 0-60 with a granularity of 4)
wim 2:76cb93b511f2 187 */
wim 2:76cb93b511f2 188 #define TCR_HALT_DEFAULT (0x0E)
wim 2:76cb93b511f2 189 #define TCR_RESUME_DEFAULT (0x04)
wim 2:76cb93b511f2 190
wim 2:76cb93b511f2 191
wim 2:76cb93b511f2 192 /** See section 8.13 of the datasheet for definitions
wim 2:76cb93b511f2 193 * of bits in the Trigger Level Register (TLR)
wim 2:76cb93b511f2 194 * Trigger level for TX interrupt: 0..15 (meaning 0-60 with a granularity of 4)
wim 2:76cb93b511f2 195 * Trigger level for RX interrupt: 0..15 (meaning 0-60 with a granularity of 4)
wim 2:76cb93b511f2 196 */
wim 2:76cb93b511f2 197 #define TLR_TX_DEFAULT (0x0E)
wim 2:76cb93b511f2 198 #define TLR_RX_DEFAULT (0x04)
wim 2:76cb93b511f2 199
wim 2:76cb93b511f2 200
wim 2:76cb93b511f2 201 /**
wim 2:76cb93b511f2 202 * See section 8.19 of the datasheet for definitions
wim 2:76cb93b511f2 203 * of bits in the IO Control register (IOC)
wim 2:76cb93b511f2 204 *
wim 2:76cb93b511f2 205 * Bit 0 is set to 0 to enable latch of IO inputs.
wim 2:76cb93b511f2 206 * Bit 1 is set to enable GPIO[7-4] as /RI, /CD, /DTR, /DST.
wim 2:76cb93b511f2 207 * Bit 2 is set to enable software reset.
wim 2:76cb93b511f2 208 */
wim 2:76cb93b511f2 209 #define IOC_ENA_LATCH (0x01)
wim 2:76cb93b511f2 210 #define IOC_ENA_MODEM (0x02)
wim 2:76cb93b511f2 211 #define IOC_SW_RST (0x04)
wim 2:76cb93b511f2 212
wim 2:76cb93b511f2 213
wim 0:d64854a60f95 214 // See Chapter 11 of datasheet
wim 2:76cb93b511f2 215 #define SPI_READ_MODE_FLAG (0x80)
wim 0:d64854a60f95 216
wim 0:d64854a60f95 217
wim 0:d64854a60f95 218 /** Abstract class SC16IS750 for a converter between either SPI or I2C and a Serial port
wim 0:d64854a60f95 219 *
wim 0:d64854a60f95 220 * Supports both SPI and I2C interfaces through derived classes
wim 0:d64854a60f95 221 *
wim 0:d64854a60f95 222 * @code
wim 0:d64854a60f95 223 *
wim 0:d64854a60f95 224 * @endcode
wim 0:d64854a60f95 225 */
wim 0:d64854a60f95 226 //class SC16IS750 : public Serial { //Fout, geen Serial constr met Serial(NC, NC) toegestaan...
wim 0:d64854a60f95 227 class SC16IS750 {
wim 0:d64854a60f95 228
wim 0:d64854a60f95 229 public:
wim 0:d64854a60f95 230
wim 0:d64854a60f95 231 // SC16IS750 Register definitions (shifted to align)
wim 0:d64854a60f95 232 enum RegisterName {
wim 1:0440152c5387 233 /*
wim 1:0440152c5387 234 * 16750 addresses. Registers accessed when LCR[7] = 0.
wim 1:0440152c5387 235 */
wim 1:0440152c5387 236 RHR = 0x00 << 3, /* Rx buffer register - Read access */
wim 1:0440152c5387 237 THR = 0x00 << 3, /* Tx holding register - Write access */
wim 1:0440152c5387 238 IER = 0x01 << 3, /* Interrupt enable reg - RD/WR access */
wim 1:0440152c5387 239
wim 1:0440152c5387 240 /*
wim 1:0440152c5387 241 * 16750 addresses. Registers accessed when LCR[7] = 1.
wim 1:0440152c5387 242 */
wim 1:0440152c5387 243 DLL = 0x00 << 3, /* Divisor latch (LSB) - RD/WR access */
wim 1:0440152c5387 244 DLH = 0x01 << 3, /* Divisor latch (MSB) - RD/WR access */
wim 1:0440152c5387 245
wim 1:0440152c5387 246 /*
wim 1:0440152c5387 247 * 16750 addresses. IIR/FCR is accessed when LCR[7:0] <> 0xBF.
wim 1:0440152c5387 248 * Bit 5 of the FCR register is accessed when LCR[7] = 1.
wim 1:0440152c5387 249 */
wim 1:0440152c5387 250 IIR = 0x02 << 3, /* Interrupt id. register - Read only */
wim 1:0440152c5387 251 FCR = 0x02 << 3, /* FIFO control register - Write only */
wim 1:0440152c5387 252 /*
wim 1:0440152c5387 253 * 16750 addresses. EFR is accessed when LCR[7:0] = 0xBF.
wim 1:0440152c5387 254 */
wim 1:0440152c5387 255 EFR = 0x02 << 3, /* Enhanced features reg - RD/WR access */
wim 1:0440152c5387 256
wim 1:0440152c5387 257 /*
wim 1:0440152c5387 258 * 16750 addresses.
wim 1:0440152c5387 259 */
wim 1:0440152c5387 260 LCR = 0x03 << 3, /* Line control register - RD/WR access */
wim 1:0440152c5387 261 /*
wim 1:0440152c5387 262 * 16750 addresses. MCR/LSR is accessed when LCR[7:0] <> 0xBF.
wim 1:0440152c5387 263 * Bit 7 of the MCR register is accessed when EFR[4] = 1.
wim 1:0440152c5387 264 */
wim 1:0440152c5387 265 MCR = 0x04 << 3, /* Modem control register - RD/WR access */
wim 1:0440152c5387 266 LSR = 0x05 << 3, /* Line status register - Read only */
wim 1:0440152c5387 267
wim 1:0440152c5387 268 /*
wim 1:0440152c5387 269 * 16750 addresses. MSR/SPR is accessed when LCR[7:0] <> 0xBF.
wim 1:0440152c5387 270 * MSR, SPR register is accessed when EFR[1]=0 and MCR[2]=0.
wim 1:0440152c5387 271 */
wim 1:0440152c5387 272 MSR = 0x06 << 3, /* Modem status register - Read only */
wim 1:0440152c5387 273 SPR = 0x07 << 3, /* Scratchpad register - RD/WR access */
wim 1:0440152c5387 274 /*
wim 1:0440152c5387 275 * 16750 addresses. TCR/TLR is accessed when LCR[7:0] <> 0xBF.
wim 1:0440152c5387 276 * TCR, TLR register is accessed when EFR[1]=1 and MCR[2]=1.
wim 1:0440152c5387 277 */
wim 1:0440152c5387 278 TCR = 0x06 << 3, /* Transmission control register - RD/WR access */
wim 1:0440152c5387 279 TLR = 0x07 << 3, /* Trigger level register - RD/WR access */
wim 1:0440152c5387 280
wim 1:0440152c5387 281 /*
wim 1:0440152c5387 282 * 16750 addresses. XON, XOFF is accessed when LCR[7:0] = 0xBF.
wim 1:0440152c5387 283 */
wim 1:0440152c5387 284 XON1 = 0x04 << 3, /* XON1 register - RD/WR access */
wim 1:0440152c5387 285 XON2 = 0x05 << 3, /* XON2 register - RD/WR access */
wim 1:0440152c5387 286 XOFF1 = 0x06 << 3, /* XOFF1 register - RD/WR access */
wim 1:0440152c5387 287 XOFF2 = 0x07 << 3, /* XOFF2 register - RD/WR access */
wim 1:0440152c5387 288
wim 1:0440152c5387 289 /*
wim 1:0440152c5387 290 * 16750 addresses.
wim 1:0440152c5387 291 */
wim 1:0440152c5387 292 TXLVL = 0x08 << 3, /* TX FIFO Level register - Read only */
wim 1:0440152c5387 293 RXLVL = 0x09 << 3, /* RX FIFO Level register - Read only */
wim 1:0440152c5387 294 IODIR = 0x0A << 3, /* IO Pin Direction reg - RD/WR access */
wim 1:0440152c5387 295 IOSTATE = 0x0B << 3, /* IO Pin State reg - Read only */
wim 1:0440152c5387 296 IOINTENA = 0x0C << 3, /* IO Interrupt Enable - RD/WR access */
wim 1:0440152c5387 297 // reserved = 0x0D << 3,
wim 1:0440152c5387 298 IOCTRL = 0x0E << 3, /* IO Control register - RD/WR access */
wim 1:0440152c5387 299 EFCR = 0x0F << 3, /* Extra features reg - RD/WR access */
wim 1:0440152c5387 300
wim 0:d64854a60f95 301 } ;
wim 0:d64854a60f95 302
wim 0:d64854a60f95 303
wim 1:0440152c5387 304 // This enum used to be part of SerialBase class (access via SerialBase.h).
wim 1:0440152c5387 305 // It seems not be supported anymore. The enums for Parity have moved to Serial now..
wim 1:0440152c5387 306 enum Flow {
wim 1:0440152c5387 307 Disabled = 0,
wim 1:0440152c5387 308 RTS,
wim 1:0440152c5387 309 CTS,
wim 1:0440152c5387 310 RTSCTS
wim 1:0440152c5387 311 };
wim 1:0440152c5387 312
wim 1:0440152c5387 313
wim 0:d64854a60f95 314 // SC16IS750 configuration register values
wim 1:0440152c5387 315 // Several configuration registers are write-only. Need to save values to allow restoring.
wim 0:d64854a60f95 316 struct SC16IS750_cfg {
wim 0:d64854a60f95 317 char baudrate;
wim 0:d64854a60f95 318 char dataformat;
wim 0:d64854a60f95 319 char flowctrl;
wim 1:0440152c5387 320 char fifoformat;
wim 1:0440152c5387 321 bool fifoenable;
wim 0:d64854a60f95 322 };
wim 0:d64854a60f95 323
wim 0:d64854a60f95 324
wim 0:d64854a60f95 325 /** Determine if there is a character available to read.
wim 2:76cb93b511f2 326 * This is data that's already arrived and stored in the receive
wim 2:76cb93b511f2 327 * buffer (which holds 64 chars).
wim 2:76cb93b511f2 328 *
wim 0:d64854a60f95 329 * @return 1 if there is a character available to read, 0 otherwise
wim 0:d64854a60f95 330 */
wim 1:0440152c5387 331 int readable();
wim 0:d64854a60f95 332
wim 2:76cb93b511f2 333 /** Determine how many characters are available to read.
wim 2:76cb93b511f2 334 * This is data that's already arrived and stored in the receive
wim 2:76cb93b511f2 335 * buffer (which holds 64 chars).
wim 2:76cb93b511f2 336 *
wim 0:d64854a60f95 337 * @return int Characters available to read
wim 2:76cb93b511f2 338 */
wim 1:0440152c5387 339 int readableCount();
wim 0:d64854a60f95 340
wim 0:d64854a60f95 341 /** Determine if there is space available to write a character.
wim 0:d64854a60f95 342 * @return 1 if there is a space for a character to write, 0 otherwise
wim 0:d64854a60f95 343 */
wim 1:0440152c5387 344 int writable();
wim 0:d64854a60f95 345
wim 2:76cb93b511f2 346
wim 1:0440152c5387 347 /** Determine how much space available for writing characters.
wim 2:76cb93b511f2 348 * This considers data that's already stored in the transmit
wim 2:76cb93b511f2 349 * buffer (which holds 64 chars).
wim 2:76cb93b511f2 350 *
wim 1:0440152c5387 351 * @return int character space available to write
wim 2:76cb93b511f2 352 */
wim 1:0440152c5387 353 int writableCount();
wim 1:0440152c5387 354
wim 0:d64854a60f95 355
wim 1:0440152c5387 356 /**
wim 1:0440152c5387 357 * Read char from UART Bridge.
wim 1:0440152c5387 358 * Acts in the same manner as 'Serial.read()'.
wim 1:0440152c5387 359 * @param none
wim 1:0440152c5387 360 * @return char read or -1 if no data available.
wim 1:0440152c5387 361 */
wim 1:0440152c5387 362 int getc();
wim 1:0440152c5387 363
wim 1:0440152c5387 364 /**
wim 1:0440152c5387 365 * Write char to UART Bridge. Blocking when no free space in FIFO
wim 1:0440152c5387 366 * @param value char to be written
wim 1:0440152c5387 367 * @return value written
wim 1:0440152c5387 368 */
wim 1:0440152c5387 369 int putc(int value);
wim 1:0440152c5387 370
wim 2:76cb93b511f2 371
wim 2:76cb93b511f2 372 /**
wim 2:76cb93b511f2 373 * Write char string to UART Bridge. Blocking when no free space in FIFO
wim 2:76cb93b511f2 374 * @param *str char string to be written
wim 2:76cb93b511f2 375 * @return none
wim 2:76cb93b511f2 376 */
wim 1:0440152c5387 377 void write(const char *str);
wim 0:d64854a60f95 378
wim 0:d64854a60f95 379 /** Set baudrate of the serial port.
wim 0:d64854a60f95 380 * @param baud integer baudrate (4800, 9600 etc)
wim 0:d64854a60f95 381 * @return none
wim 0:d64854a60f95 382 */
wim 2:76cb93b511f2 383 void baud(int baudrate = SC16IS750_DEFAULT_BAUDRATE);
wim 0:d64854a60f95 384
wim 0:d64854a60f95 385 /** Set the transmission format used by the serial port.
wim 0:d64854a60f95 386 * @param bits The number of bits in a word (5-8; default = 8)
wim 0:d64854a60f95 387 * @param parity The parity used (Serial::None, Serial::Odd, Serial::Even, Serial::Forced1, Serial::Forced0; default = Serial::None)
wim 0:d64854a60f95 388 * @param stop_bits The number of stop bits (1 or 2; default = 1)
wim 2:76cb93b511f2 389 * @return none
wim 0:d64854a60f95 390 */
wim 1:0440152c5387 391 void format(int bits=8, Serial::Parity parity=Serial::None, int stop_bits=1);
wim 2:76cb93b511f2 392
wim 1:0440152c5387 393 #if(0)
wim 1:0440152c5387 394 /** Attach a function to call whenever a serial interrupt is generated
wim 1:0440152c5387 395 *
wim 1:0440152c5387 396 * @param fptr A pointer to a void function, or 0 to set as none
wim 1:0440152c5387 397 * @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty)
wim 1:0440152c5387 398 */
wim 1:0440152c5387 399 void attach(void (*fptr)(void), IrqType type=RxIrq);
wim 1:0440152c5387 400
wim 1:0440152c5387 401 /** Attach a member function to call whenever a serial interrupt is generated
wim 1:0440152c5387 402 *
wim 1:0440152c5387 403 * @param tptr pointer to the object to call the member function on
wim 1:0440152c5387 404 * @param mptr pointer to the member function to be called
wim 1:0440152c5387 405 * @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty)
wim 2:76cb93b511f2 406 * @return none
wim 1:0440152c5387 407 */
wim 1:0440152c5387 408 template<typename T>
wim 1:0440152c5387 409 void attach(T* tptr, void (T::*mptr)(void), IrqType type=RxIrq) {
wim 1:0440152c5387 410 if((mptr != NULL) && (tptr != NULL)) {
wim 1:0440152c5387 411 _irq[type].attach(tptr, mptr);
wim 1:0440152c5387 412 serial_irq_set(&_serial, (SerialIrq)type, 1);
wim 1:0440152c5387 413 }
wim 1:0440152c5387 414 }
wim 1:0440152c5387 415 #endif
wim 1:0440152c5387 416
wim 1:0440152c5387 417 /** Generate a break condition on the serial line
wim 2:76cb93b511f2 418 * @param none
wim 2:76cb93b511f2 419 * @return none
wim 1:0440152c5387 420 */
wim 1:0440152c5387 421 void send_break();
wim 0:d64854a60f95 422
wim 1:0440152c5387 423
wim 1:0440152c5387 424 /** Set a break condition on the serial line
wim 1:0440152c5387 425 * @param enable break condition
wim 2:76cb93b511f2 426 * @return none
wim 1:0440152c5387 427 */
wim 1:0440152c5387 428 void set_break(bool enable=false);
wim 1:0440152c5387 429
wim 1:0440152c5387 430
wim 1:0440152c5387 431 /** Set the flow control type on the serial port
wim 1:0440152c5387 432 * Added for compatibility with Serial Class.
wim 2:76cb93b511f2 433 * SC16IS750 supports only Flow, Pins can not be selected.
wim 2:76cb93b511f2 434 * This method sets only hardware flow control. SC16IS750 supports XON/XOFF, but this is not implemented.
wim 1:0440152c5387 435 *
wim 1:0440152c5387 436 * @param type the flow control type (Disabled, RTS, CTS, RTSCTS)
wim 1:0440152c5387 437 * @param flow1 the first flow control pin (RTS for RTS or RTSCTS, CTS for CTS)
wim 1:0440152c5387 438 * @param flow2 the second flow control pin (CTS for RTSCTS)
wim 2:76cb93b511f2 439 * @return none
wim 1:0440152c5387 440 */
wim 1:0440152c5387 441 void set_flow_control(Flow type=Disabled, PinName flow1=NC, PinName flow2=NC);
wim 2:76cb93b511f2 442
wim 2:76cb93b511f2 443
wim 2:76cb93b511f2 444 /** Set the RX FIFO flow control levels
wim 2:76cb93b511f2 445 * This method sets only hardware flow control levels. SC16IS750 supports XON/XOFF, but this is not implemented.
wim 2:76cb93b511f2 446 * Should be called BEFORE Auto RTS is enabled.
wim 2:76cb93b511f2 447 *
wim 2:76cb93b511f2 448 * @param resume trigger level to resume transmission (0..15, meaning 0-60 with a granularity of 4)
wim 2:76cb93b511f2 449 * @param halt trigger level to resume transmission (0..15, meaning 0-60 with granularity of 4)
wim 2:76cb93b511f2 450 * @return none
wim 2:76cb93b511f2 451 */
wim 2:76cb93b511f2 452 void set_flow_triggers(int resume = TCR_RESUME_DEFAULT, int halt = TCR_HALT_DEFAULT);
wim 2:76cb93b511f2 453
wim 2:76cb93b511f2 454
wim 2:76cb93b511f2 455 /** Set the Modem Control register
wim 2:76cb93b511f2 456 * This method sets prescaler, enables TCR and TLR
wim 2:76cb93b511f2 457 *
wim 2:76cb93b511f2 458 * @param none
wim 2:76cb93b511f2 459 * @return none
wim 2:76cb93b511f2 460 */
wim 2:76cb93b511f2 461 void set_modem_control();
wim 2:76cb93b511f2 462
wim 1:0440152c5387 463
wim 0:d64854a60f95 464 /**
wim 0:d64854a60f95 465 * Check that UART is connected and operational.
wim 0:d64854a60f95 466 * @param none
wim 0:d64854a60f95 467 * @return bool true when connected, false otherwise
wim 0:d64854a60f95 468 */
wim 0:d64854a60f95 469 bool connected();
wim 0:d64854a60f95 470
wim 0:d64854a60f95 471
wim 2:76cb93b511f2 472
wim 2:76cb93b511f2 473 /** FIFO control, sets TX and RX trigger levels and enables FIFO and save in _config
wim 2:76cb93b511f2 474 * Note FCR[5:4] (=TX_IRQ_LVL) only accessible when EFR[4] is set (enhanced functions enable)
wim 2:76cb93b511f2 475 * Note TLR only accessible when EFR[4] is set (enhanced functions enable) and MCR[2] is set
wim 2:76cb93b511f2 476 * @param none
wim 2:76cb93b511f2 477 * @return none
wim 2:76cb93b511f2 478 */
wim 2:76cb93b511f2 479 void set_fifo_control();
wim 2:76cb93b511f2 480
wim 1:0440152c5387 481
wim 1:0440152c5387 482 /** Flush the UART FIFOs while maintaining current FIFO mode.
wim 1:0440152c5387 483 * @param none
wim 1:0440152c5387 484 * @return none
wim 1:0440152c5387 485 */
wim 1:0440152c5387 486 void flush();
wim 0:d64854a60f95 487
wim 0:d64854a60f95 488 //required for Stream
wim 1:0440152c5387 489 int peek() {return 0;};
wim 1:0440152c5387 490
wim 1:0440152c5387 491
wim 1:0440152c5387 492 /** Set direction of I/O port pins.
wim 1:0440152c5387 493 * This method is specific to the SPI-I2C UART and not found on the 16750
wim 1:0440152c5387 494 * @param bits Bitpattern for I/O (1=output, 0=input)
wim 1:0440152c5387 495 * @return none
wim 1:0440152c5387 496 */
wim 1:0440152c5387 497 void ioSetDirection(unsigned char bits);
wim 0:d64854a60f95 498
wim 1:0440152c5387 499 /** Set bits of I/O port pins.
wim 1:0440152c5387 500 * This method is specific to the SPI-I2C UART and not found on the 16750
wim 1:0440152c5387 501 * @param bits Bitpattern for I/O (1= set output bit, 0 = clear output bit)
wim 1:0440152c5387 502 * @return none
wim 1:0440152c5387 503 */
wim 1:0440152c5387 504 void ioSetState(unsigned char bits);
wim 1:0440152c5387 505
wim 1:0440152c5387 506 /** Get bits of I/O port pins.
wim 1:0440152c5387 507 * This method is specific to the SPI-I2C UART and not found on the 16750
wim 1:0440152c5387 508 * @param none
wim 1:0440152c5387 509 * @return bits Bitpattern for I/O (1= bit set, 0 = bit cleared)
wim 1:0440152c5387 510 */
wim 1:0440152c5387 511 unsigned char ioGetState();
wim 1:0440152c5387 512
wim 1:0440152c5387 513
wim 1:0440152c5387 514 /** Software Reset SC16IS750 device.
wim 1:0440152c5387 515 * This method is specific to the SPI-I2C UART and not found on the 16750
wim 1:0440152c5387 516 * @param none
wim 1:0440152c5387 517 * @return none
wim 1:0440152c5387 518 */
wim 1:0440152c5387 519 void swReset();
wim 1:0440152c5387 520
wim 0:d64854a60f95 521
wim 0:d64854a60f95 522 /** Write value to internal register.
wim 0:d64854a60f95 523 * Pure virtual, must be declared in derived class.
wim 1:0440152c5387 524 * @param registerAddress The address of the Register (enum RegisterName)
wim 0:d64854a60f95 525 * @param data The 8bit value to write
wim 0:d64854a60f95 526 * @return none
wim 0:d64854a60f95 527 */
wim 1:0440152c5387 528 virtual void writeRegister (RegisterName register_address, char data ) =0;
wim 0:d64854a60f95 529
wim 0:d64854a60f95 530 /** Read value from internal register.
wim 0:d64854a60f95 531 * Pure virtual, must be declared in derived class.
wim 1:0440152c5387 532 * @param registerAddress The address of the Register (enum RegisterName)
wim 0:d64854a60f95 533 * @return char The 8bit value read from the register
wim 0:d64854a60f95 534 */
wim 1:0440152c5387 535 virtual char readRegister (RegisterName register_address ) =0;
wim 1:0440152c5387 536
wim 0:d64854a60f95 537
wim 1:0440152c5387 538 /** Initialise internal registers
wim 1:0440152c5387 539 * Should be in protection section. Public for testing purposes
wim 1:0440152c5387 540 * If initialisation fails this method does not return.
wim 1:0440152c5387 541 * @param none
wim 1:0440152c5387 542 * @return none
wim 1:0440152c5387 543 */
wim 1:0440152c5387 544 void _init();
wim 1:0440152c5387 545
wim 0:d64854a60f95 546 protected:
wim 0:d64854a60f95 547 //protected is accessible to derived classes, but not to external users
wim 0:d64854a60f95 548
wim 2:76cb93b511f2 549
wim 2:76cb93b511f2 550 /** Constructor is protected for this abstract Class
wim 1:0440152c5387 551 *
wim 1:0440152c5387 552 */
wim 1:0440152c5387 553 SC16IS750();
wim 1:0440152c5387 554
wim 2:76cb93b511f2 555 // Save config settings
wim 0:d64854a60f95 556 SC16IS750_cfg _config;
wim 0:d64854a60f95 557
wim 0:d64854a60f95 558 private:
wim 0:d64854a60f95 559 //private is not accessible to derived classes, nor external users
wim 1:0440152c5387 560
wim 0:d64854a60f95 561 };
wim 0:d64854a60f95 562
wim 0:d64854a60f95 563
wim 0:d64854a60f95 564
wim 0:d64854a60f95 565 /** Class SC16IS750_SPI for a converter between SPI and a Serial port
wim 0:d64854a60f95 566 *
wim 0:d64854a60f95 567 * @code
wim 0:d64854a60f95 568 * #include "mbed.h"
wim 0:d64854a60f95 569 * #include "SC16IS750.h"
wim 0:d64854a60f95 570 *
wim 0:d64854a60f95 571 * SPI spi(PTD2, PTD3, PTD1); //MOSI, MISO, SCK
wim 0:d64854a60f95 572 * SC16IS750_SPI serial_spi(&spi, PTD0);
wim 0:d64854a60f95 573 *
wim 0:d64854a60f95 574 * Serial pc(USBTX,USBRX);
wim 0:d64854a60f95 575 *
wim 0:d64854a60f95 576 * int main() {
wim 0:d64854a60f95 577 * pc.printf("\nHello World!\n");
wim 0:d64854a60f95 578 *
wim 0:d64854a60f95 579 * while(1) {
wim 0:d64854a60f95 580 * serial_spi.ioSetState(0x00);
wim 0:d64854a60f95 581 * wait(0.5);
wim 2:76cb93b511f2 582 * serial_spi.ioSetState(0xFF);
wim 2:76cb93b511f2 583 * wait(0.5);
wim 2:76cb93b511f2 584 * serial_spi.putc('*');
wim 0:d64854a60f95 585 * pc.putc('*');
wim 0:d64854a60f95 586 * }
wim 0:d64854a60f95 587 * }
wim 0:d64854a60f95 588 *
wim 0:d64854a60f95 589 * @endcode
wim 0:d64854a60f95 590 */
wim 0:d64854a60f95 591 class SC16IS750_SPI : public SC16IS750 {
wim 0:d64854a60f95 592 public:
wim 0:d64854a60f95 593
wim 0:d64854a60f95 594 /** Create a SC16IS750_SPI object using a specified SPI bus and CS
wim 0:d64854a60f95 595 *
wim 0:d64854a60f95 596 * @param SPI &spi the SPI port to connect to
wim 0:d64854a60f95 597 * @param cs the Pin of the CS
wim 0:d64854a60f95 598 */
wim 0:d64854a60f95 599 SC16IS750_SPI(SPI *spi, PinName cs);
wim 0:d64854a60f95 600
wim 0:d64854a60f95 601 /** Write value to internal register.
wim 1:0440152c5387 602 * @param registerAddress The address of the Register (enum RegisterName)
wim 0:d64854a60f95 603 * @param data The 8bit value to write
wim 0:d64854a60f95 604 * @return none
wim 0:d64854a60f95 605 */
wim 0:d64854a60f95 606 virtual void writeRegister(SC16IS750::RegisterName registerAddress, char data);
wim 0:d64854a60f95 607
wim 0:d64854a60f95 608 /** Read value from internal register.
wim 1:0440152c5387 609 * @param registerAddress The address of the Register (enum RegisterName)
wim 0:d64854a60f95 610 * @return char The 8bit value read from the register
wim 0:d64854a60f95 611 */
wim 0:d64854a60f95 612 virtual char readRegister(SC16IS750::RegisterName registerAddress);
wim 0:d64854a60f95 613
wim 0:d64854a60f95 614 protected:
wim 0:d64854a60f95 615 //protected is accessible to derived classes, but not to external users
wim 0:d64854a60f95 616
wim 0:d64854a60f95 617
wim 0:d64854a60f95 618 private:
wim 0:d64854a60f95 619 SPI *_spi; //SPI bus reference
wim 0:d64854a60f95 620 DigitalOut _cs; //CS of SPI device
wim 0:d64854a60f95 621
wim 0:d64854a60f95 622 };
wim 0:d64854a60f95 623
wim 0:d64854a60f95 624
wim 0:d64854a60f95 625
wim 0:d64854a60f95 626 /** Class SC16IS750_I2C for a converter between I2C and a Serial port
wim 0:d64854a60f95 627 *
wim 0:d64854a60f95 628 * @code
wim 0:d64854a60f95 629 * #include "mbed.h"
wim 0:d64854a60f95 630 * #include "SC16IS750.h"
wim 0:d64854a60f95 631 *
wim 0:d64854a60f95 632 * I2C i2c(PTE0, PTE1); //SDA, SCL
wim 0:d64854a60f95 633 * SC16IS750_I2C serial_i2c(&i2c, DEFAULT_SC16IS750_ADDR);
wim 0:d64854a60f95 634 *
wim 0:d64854a60f95 635 * Serial pc(USBTX,USBRX);
wim 0:d64854a60f95 636 *
wim 0:d64854a60f95 637 * int main() {
wim 0:d64854a60f95 638 * pc.printf("\nHello World!\n");
wim 0:d64854a60f95 639 *
wim 0:d64854a60f95 640 * while(1) {
wim 0:d64854a60f95 641 * serial_i2c.ioSetState(0x00);
wim 0:d64854a60f95 642 * wait(0.5);
wim 2:76cb93b511f2 643 * serial_i2c.ioSetState(0xFF);
wim 2:76cb93b511f2 644 * wait(0.5);
wim 2:76cb93b511f2 645 * serial_i2c.putc('*');
wim 0:d64854a60f95 646 * pc.putc('*');
wim 0:d64854a60f95 647 * }
wim 0:d64854a60f95 648 * }
wim 0:d64854a60f95 649 *
wim 0:d64854a60f95 650 * @endcode
wim 0:d64854a60f95 651 */
wim 0:d64854a60f95 652 class SC16IS750_I2C : public SC16IS750 {
wim 0:d64854a60f95 653 public:
wim 0:d64854a60f95 654
wim 0:d64854a60f95 655 /** Create a SC16IS750_I2C object using a specified I2C bus and slaveaddress
wim 0:d64854a60f95 656 *
wim 0:d64854a60f95 657 * @param I2C &i2c the I2C port to connect to
wim 0:d64854a60f95 658 * @param char deviceAddress the address of the SC16IS750
wim 0:d64854a60f95 659 */
wim 2:76cb93b511f2 660 SC16IS750_I2C(I2C *i2c, uint8_t deviceAddress = SC16IS750_DEFAULT_ADDR);
wim 0:d64854a60f95 661
wim 0:d64854a60f95 662 /** Write value to internal register.
wim 1:0440152c5387 663 * @param registerAddress The address of the Register (enum RegisterName)
wim 0:d64854a60f95 664 * @param data The 8bit value to write
wim 0:d64854a60f95 665 * @return none
wim 0:d64854a60f95 666 */
wim 0:d64854a60f95 667 virtual void writeRegister(SC16IS750::RegisterName register_address, char data );
wim 0:d64854a60f95 668
wim 0:d64854a60f95 669 /** Read value from internal register.
wim 1:0440152c5387 670 * @param registerAddress The address of the Register (enum RegisterName)
wim 0:d64854a60f95 671 * @return char The 8bit value read from the register
wim 0:d64854a60f95 672 */
wim 0:d64854a60f95 673 virtual char readRegister(SC16IS750::RegisterName register_address );
wim 0:d64854a60f95 674
wim 0:d64854a60f95 675 protected:
wim 0:d64854a60f95 676 //protected is accessible to derived classes, but not to external users
wim 0:d64854a60f95 677
wim 0:d64854a60f95 678
wim 0:d64854a60f95 679 private:
wim 0:d64854a60f95 680 I2C *_i2c; //I2C bus reference
wim 0:d64854a60f95 681 uint8_t _slaveAddress; //I2C Slave address of device
wim 0:d64854a60f95 682
wim 0:d64854a60f95 683 };
wim 0:d64854a60f95 684
wim 0:d64854a60f95 685
wim 0:d64854a60f95 686 #endif // _SC16IS750_H