Randal Riedinger
RETRO ROBOT E
Dependents: RETRO_ROBOT_SC16IS750E
Fork of
SC16IS750
by 
Wim Huiskamp
SC16IS750.h@3:9783b6bde958, 2014-02-20 (annotated)
- Committer:
- wim
- Date:
- Thu Feb 20 19:37:55 2014 +0000
- Revision:
- 3:9783b6bde958
- Parent:
- 2:76cb93b511f2
- Child:
- 4:12446ee9f9c8
SC16IS750 SPI or I2C to UART Bridge (First Release)
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| wim | 3:9783b6bde958 | 1 | /* SC16IS750 I2C or SPI to UART bridge |
| wim | 3:9783b6bde958 | 2 | * v0.1 WH, Nov 2013, Sparkfun WiFly Shield code library alpha 0 used as example, Added I2C I/F and many more methods. |
| wim | 3:9783b6bde958 | 3 | * https://forum.sparkfun.com/viewtopic.php?f=13&t=21846 |
| wim | 0:d64854a60f95 | 4 | * |
| wim | 0:d64854a60f95 | 5 | * Permission is hereby granted, free of charge, to any person obtaining a copy of this software |
| wim | 0:d64854a60f95 | 6 | * and associated documentation files (the "Software"), to deal in the Software without restriction, |
| wim | 0:d64854a60f95 | 7 | * including without limitation the rights to use, copy, modify, merge, publish, distribute, |
| wim | 0:d64854a60f95 | 8 | * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is |
| wim | 0:d64854a60f95 | 9 | * furnished to do so, subject to the following conditions: |
| wim | 0:d64854a60f95 | 10 | * |
| wim | 0:d64854a60f95 | 11 | * The above copyright notice and this permission notice shall be included in all copies or |
| wim | 0:d64854a60f95 | 12 | * substantial portions of the Software. |
| wim | 0:d64854a60f95 | 13 | * |
| wim | 0:d64854a60f95 | 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING |
| wim | 0:d64854a60f95 | 15 | * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| wim | 0:d64854a60f95 | 16 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, |
| wim | 0:d64854a60f95 | 17 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| wim | 0:d64854a60f95 | 18 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| wim | 0:d64854a60f95 | 19 | */ |
| wim | 0:d64854a60f95 | 20 | #ifndef _SC16IS750_H |
| wim | 0:d64854a60f95 | 21 | #define _SC16IS750_H |
| wim | 0:d64854a60f95 | 22 | |
| wim | 3:9783b6bde958 | 23 | |
| wim | 3:9783b6bde958 | 24 | #include "Stream.h" |
| wim | 3:9783b6bde958 | 25 | //#include <SerialBase.h> |
| wim | 3:9783b6bde958 | 26 | |
| wim | 1:0440152c5387 | 27 | //I2C Slaveaddresses A1 A0 |
| wim | 2:76cb93b511f2 | 28 | #define SC16IS750_SA0 0x90 /* VDD VDD */ |
| wim | 2:76cb93b511f2 | 29 | #define SC16IS750_SA1 0x92 /* VDD VSS */ |
| wim | 2:76cb93b511f2 | 30 | #define SC16IS750_SA2 0x94 /* VDD SCL */ |
| wim | 2:76cb93b511f2 | 31 | #define SC16IS750_SA3 0x95 /* VDD SDA */ |
| wim | 2:76cb93b511f2 | 32 | #define SC16IS750_SA4 0x98 /* VSS VDD */ |
| wim | 2:76cb93b511f2 | 33 | #define SC16IS750_SA5 0x9A /* VSS VSS */ |
| wim | 2:76cb93b511f2 | 34 | #define SC16IS750_SA6 0x9C /* VSS SCL */ |
| wim | 2:76cb93b511f2 | 35 | #define SC16IS750_SA7 0x9E /* VSS SDA */ |
| wim | 2:76cb93b511f2 | 36 | #define SC16IS750_SA8 0xA0 /* SCL VDD */ |
| wim | 2:76cb93b511f2 | 37 | #define SC16IS750_SA9 0xA2 /* SCL VSS */ |
| wim | 2:76cb93b511f2 | 38 | #define SC16IS750_SA10 0xA4 /* SCL SCL */ |
| wim | 2:76cb93b511f2 | 39 | #define SC16IS750_SA11 0xA6 /* SCL SDA */ |
| wim | 2:76cb93b511f2 | 40 | #define SC16IS750_SA12 0xA8 /* SDA VDD */ |
| wim | 2:76cb93b511f2 | 41 | #define SC16IS750_SA13 0xAA /* SDA VSS */ |
| wim | 2:76cb93b511f2 | 42 | #define SC16IS750_SA14 0xAC /* SDA SCL */ |
| wim | 2:76cb93b511f2 | 43 | #define SC16IS750_SA15 0xAE /* SDA SDA */ |
| wim | 1:0440152c5387 | 44 | |
| wim | 0:d64854a60f95 | 45 | //Default I2C Slaveaddress |
| wim | 2:76cb93b511f2 | 46 | #define SC16IS750_DEFAULT_ADDR SC16IS750_SA0 |
| wim | 2:76cb93b511f2 | 47 | |
| wim | 2:76cb93b511f2 | 48 | |
| wim | 2:76cb93b511f2 | 49 | /** See datasheet section 7.8 for configuring the |
| wim | 2:76cb93b511f2 | 50 | * "Programmable baud rate generator" |
| wim | 2:76cb93b511f2 | 51 | */ |
| wim | 2:76cb93b511f2 | 52 | #define SC16IS750_XTAL_FREQ 14745600UL /* On-board crystal (New mid-2010 Version) */ |
| wim | 2:76cb93b511f2 | 53 | #define SC16IS750_PRESCALER_1 1 /* Default prescaler after reset */ |
| wim | 2:76cb93b511f2 | 54 | #define SC16IS750_PRESCALER_4 4 /* Selectable by setting MCR[7] */ |
| wim | 2:76cb93b511f2 | 55 | #define SC16IS750_PRESCALER SC16IS750_PRESCALER_1 |
| wim | 2:76cb93b511f2 | 56 | #define SC16IS750_BAUDRATE_DIVISOR(baud) ((SC16IS750_XTAL_FREQ/SC16IS750_PRESCALER)/(baud*16UL)) |
| wim | 0:d64854a60f95 | 57 | |
| wim | 0:d64854a60f95 | 58 | //Default baudrate |
| wim | 3:9783b6bde958 | 59 | #define SC16IS750_DEFAULT_BAUDRATE 9600 |
| wim | 0:d64854a60f95 | 60 | |
| wim | 1:0440152c5387 | 61 | |
| wim | 2:76cb93b511f2 | 62 | /** See section 8.3 of the datasheet for definitions |
| wim | 2:76cb93b511f2 | 63 | * of bits in the FIFO Control Register (FCR) |
| wim | 2:76cb93b511f2 | 64 | */ |
| wim | 2:76cb93b511f2 | 65 | #define FCR_RX_IRQ_60 (3 << 6) |
| wim | 2:76cb93b511f2 | 66 | #define FCR_RX_IRQ_56 (2 << 6) |
| wim | 2:76cb93b511f2 | 67 | #define FCR_RX_IRQ_16 (1 << 6) |
| wim | 2:76cb93b511f2 | 68 | #define FCR_RX_IRQ_8 (0 << 6) |
| wim | 2:76cb93b511f2 | 69 | //TX Level only accessible when EFR[4] is set |
| wim | 2:76cb93b511f2 | 70 | #define FCR_TX_IRQ_56 (3 << 4) |
| wim | 2:76cb93b511f2 | 71 | #define FCR_TX_IRQ_32 (2 << 4) |
| wim | 2:76cb93b511f2 | 72 | #define FCR_TX_IRQ_16 (1 << 4) |
| wim | 2:76cb93b511f2 | 73 | #define FCR_TX_IRQ_8 (0 << 4) |
| wim | 2:76cb93b511f2 | 74 | //#define FCR_RESERVED (1 << 3) |
| wim | 3:9783b6bde958 | 75 | #define FCR_TX_FIFO_RST (1 << 2) |
| wim | 3:9783b6bde958 | 76 | #define FCR_RX_FIFO_RST (1 << 1) |
| wim | 1:0440152c5387 | 77 | #define FCR_ENABLE_FIFO (1 << 0) |
| wim | 1:0440152c5387 | 78 | |
| wim | 2:76cb93b511f2 | 79 | //FIFO size |
| wim | 2:76cb93b511f2 | 80 | #define SC16IS750_FIFO_RX 64 |
| wim | 2:76cb93b511f2 | 81 | #define SC16IS750_FIFO_TX 64 |
| wim | 1:0440152c5387 | 82 | |
| wim | 1:0440152c5387 | 83 | |
| wim | 2:76cb93b511f2 | 84 | /** See section 8.4 of the datasheet for definitions |
| wim | 2:76cb93b511f2 | 85 | * of bits in the Line Control Register (LCR) |
| wim | 2:76cb93b511f2 | 86 | */ |
| wim | 2:76cb93b511f2 | 87 | #define LCR_BITS5 0x00 |
| wim | 2:76cb93b511f2 | 88 | #define LCR_BITS6 0x01 |
| wim | 2:76cb93b511f2 | 89 | #define LCR_BITS7 0x02 |
| wim | 2:76cb93b511f2 | 90 | #define LCR_BITS8 0x03 |
| wim | 1:0440152c5387 | 91 | |
| wim | 2:76cb93b511f2 | 92 | #define LCR_BITS1 0x00 |
| wim | 2:76cb93b511f2 | 93 | #define LCR_BITS2 0x04 |
| wim | 1:0440152c5387 | 94 | |
| wim | 2:76cb93b511f2 | 95 | #define LCR_NONE 0x00 |
| wim | 2:76cb93b511f2 | 96 | #define LCR_ODD 0x08 |
| wim | 2:76cb93b511f2 | 97 | #define LCR_EVEN 0x18 |
| wim | 2:76cb93b511f2 | 98 | #define LCR_FORCED1 0x28 |
| wim | 2:76cb93b511f2 | 99 | #define LCR_FORCED0 0x38 |
| wim | 2:76cb93b511f2 | 100 | |
| wim | 2:76cb93b511f2 | 101 | #define LCR_BRK_ENA 0x40 |
| wim | 2:76cb93b511f2 | 102 | #define LCR_BRK_DIS 0x00 |
| wim | 1:0440152c5387 | 103 | |
| wim | 2:76cb93b511f2 | 104 | #define LCR_ENABLE_DIV 0x80 |
| wim | 2:76cb93b511f2 | 105 | #define LCR_DISABLE_DIV 0x00 |
| wim | 2:76cb93b511f2 | 106 | |
| wim | 2:76cb93b511f2 | 107 | #define LCR_ENABLE_ENHANCED_FUNCTIONS (0xBF) |
| wim | 1:0440152c5387 | 108 | |
| wim | 1:0440152c5387 | 109 | |
| wim | 2:76cb93b511f2 | 110 | /** See section 8.5 of the datasheet for definitions |
| wim | 2:76cb93b511f2 | 111 | * of bits in the Line status register (LSR) |
| wim | 2:76cb93b511f2 | 112 | */ |
| wim | 3:9783b6bde958 | 113 | #define LSR_DR (0x01) /* Data ready in RX FIFO */ |
| wim | 1:0440152c5387 | 114 | #define LSR_OE (0x02) /* Overrun error */ |
| wim | 1:0440152c5387 | 115 | #define LSR_PE (0x04) /* Parity error */ |
| wim | 1:0440152c5387 | 116 | #define LSR_FE (0x08) /* Framing error */ |
| wim | 1:0440152c5387 | 117 | #define LSR_BI (0x10) /* Break interrupt */ |
| wim | 1:0440152c5387 | 118 | #define LSR_THRE (0x20) /* Transmitter holding register (FIFO empty) */ |
| wim | 1:0440152c5387 | 119 | #define LSR_TEMT (0x40) /* Transmitter empty (FIFO and TSR both empty) */ |
| wim | 2:76cb93b511f2 | 120 | #define LSR_FFE (0x80) /* At least one PE, FE or BI in FIFO */ |
| wim | 1:0440152c5387 | 121 | |
| wim | 2:76cb93b511f2 | 122 | |
| wim | 2:76cb93b511f2 | 123 | /** See section 8.6 of the datasheet for definitions |
| wim | 2:76cb93b511f2 | 124 | * of bits in the Modem control register (MCR) |
| wim | 2:76cb93b511f2 | 125 | */ |
| wim | 2:76cb93b511f2 | 126 | #define MCR_MDTR (1 << 0) /* Data Terminal Ready pin control. */ |
| wim | 2:76cb93b511f2 | 127 | #define MCR_MRTS (1 << 1) /* Request to Send pin control when not in Auto RTS mode.*/ |
| wim | 3:9783b6bde958 | 128 | //MCR[2] only accessible when EFR[4] is set |
| wim | 2:76cb93b511f2 | 129 | #define MCR_ENABLE_TCR_TLR (1 << 2) |
| wim | 2:76cb93b511f2 | 130 | #define MCR_ENABLE_LOOPBACK (1 << 4) |
| wim | 3:9783b6bde958 | 131 | //MCR[7:5] only accessible when EFR[4] is set |
| wim | 2:76cb93b511f2 | 132 | #define MCR_ENABLE_XON_ANY_CHAR (1 << 5) |
| wim | 2:76cb93b511f2 | 133 | #define MCR_ENABLE_IRDA (1 << 6) |
| wim | 2:76cb93b511f2 | 134 | #define MCR_PRESCALE_1 (0 << 7) |
| wim | 2:76cb93b511f2 | 135 | #define MCR_PRESCALE_4 (1 << 7) |
| wim | 2:76cb93b511f2 | 136 | |
| wim | 1:0440152c5387 | 137 | |
| wim | 2:76cb93b511f2 | 138 | /** See section 8.7 of the datasheet for definitions |
| wim | 2:76cb93b511f2 | 139 | * of bits in the Modem status register (MSR) |
| wim | 2:76cb93b511f2 | 140 | */ |
| wim | 3:9783b6bde958 | 141 | #define MSR_DCTS (1 << 0) /* Delta CTS - CTS Changed State */ |
| wim | 3:9783b6bde958 | 142 | #define MSR_DDSR (1 << 1) /* Delta DSR - DSR Changed State */ |
| wim | 3:9783b6bde958 | 143 | #define MSR_DDI (1 << 2) /* Delta DI - DI Changed State */ |
| wim | 3:9783b6bde958 | 144 | #define MSR_DCD (1 << 3) /* Delta CD - CD Changed State */ |
| wim | 3:9783b6bde958 | 145 | #define MSR_CTS (1 << 4) /* CTS State - Complement of NCTS pin */ |
| wim | 3:9783b6bde958 | 146 | //MSR[7:5] only accessible when GPIO[7:4] are set as modem pin |
| wim | 3:9783b6bde958 | 147 | #define MSR_DSR (1 << 5) /* DSR State - Complement of NDSR pin */ |
| wim | 3:9783b6bde958 | 148 | #define MSR_RI (1 << 6) /* RI State - Complement of NRI pin */ |
| wim | 3:9783b6bde958 | 149 | #define MSR_CD (1 << 7) /* CD State - Complement of NCD pin */ |
| wim | 2:76cb93b511f2 | 150 | |
| wim | 2:76cb93b511f2 | 151 | |
| wim | 2:76cb93b511f2 | 152 | /** See section 8.8 of the datasheet for definitions |
| wim | 2:76cb93b511f2 | 153 | * of bits in the Interrupt enable register (IER) |
| wim | 2:76cb93b511f2 | 154 | */ |
| wim | 3:9783b6bde958 | 155 | #define IER_ERHRI (0x01) /* Enable received data available interrupt */ |
| wim | 3:9783b6bde958 | 156 | #define IER_ETHRI (0x02) /* Enable transmitter holding register empty interrupt */ |
| wim | 2:76cb93b511f2 | 157 | #define IER_ELSI (0x04) /* Enable receiver line status interrupt */ |
| wim | 3:9783b6bde958 | 158 | #define IER_EMSI (0x08) /* Enable modem status interrupt */ |
| wim | 3:9783b6bde958 | 159 | //IER[7:5] only accessible when EFR[4] is set |
| wim | 2:76cb93b511f2 | 160 | #define IER_SLEEP (0x10) /* Enable sleep mode */ |
| wim | 3:9783b6bde958 | 161 | #define IER_XOFFI (0x20) /* Enable XOFF interrupt */ |
| wim | 3:9783b6bde958 | 162 | #define IER_RTSI (0x40) /* Enable RTS interrupt */ |
| wim | 3:9783b6bde958 | 163 | #define IER_CTSI (0x80) /* Enable CTS interrupt */ |
| wim | 1:0440152c5387 | 164 | |
| wim | 1:0440152c5387 | 165 | |
| wim | 2:76cb93b511f2 | 166 | /** See section 8.9 of the datasheet for definitions |
| wim | 2:76cb93b511f2 | 167 | * of bits in the Interrupt identification register (IIR) |
| wim | 3:9783b6bde958 | 168 | * Bit 0 is set to 0 if an IRQ is pending. |
| wim | 3:9783b6bde958 | 169 | * Bits 1..5 are used to identify the IRQ source. |
| wim | 2:76cb93b511f2 | 170 | */ |
| wim | 3:9783b6bde958 | 171 | #define IIR_IRQ_NOT_PENDING (0x01) /* IRQ Not Pending */ |
| wim | 3:9783b6bde958 | 172 | #define IIR_TX_EMPTY (0x02) /* THR Interrupt */ |
| wim | 3:9783b6bde958 | 173 | #define IIR_RX_DATA (0x04) /* RHR Interrupt */ |
| wim | 3:9783b6bde958 | 174 | #define IIR_RX_ERROR (0x06) /* Line Status Error Interrupt */ |
| wim | 3:9783b6bde958 | 175 | #define IIR_RX_TIMEOUT (0x0B) /* RX Timeout Interrupt */ |
| wim | 3:9783b6bde958 | 176 | #define IIR_RX_XOFF (0x10) /* RX XOff Interrupt */ |
| wim | 3:9783b6bde958 | 177 | #define IIR_DCTS_DRTS (0x20) /* Delta CTS or RTS Interrupt */ |
| wim | 3:9783b6bde958 | 178 | #define IIR_DIO (0x30) /* Delta GPIO pin Interrupt */ |
| wim | 3:9783b6bde958 | 179 | |
| wim | 2:76cb93b511f2 | 180 | #define IIR_BITS_USED (0x07) |
| wim | 2:76cb93b511f2 | 181 | |
| wim | 2:76cb93b511f2 | 182 | |
| wim | 2:76cb93b511f2 | 183 | /** See section 8.10 of the datasheet for definitions |
| wim | 2:76cb93b511f2 | 184 | * of bits in the Enhanced Features Register (EFR) |
| wim | 2:76cb93b511f2 | 185 | */ |
| wim | 2:76cb93b511f2 | 186 | #define EFR_ENABLE_CTS (1 << 7) |
| wim | 2:76cb93b511f2 | 187 | #define EFR_ENABLE_RTS (1 << 6) |
| wim | 2:76cb93b511f2 | 188 | #define EFR_ENABLE_XOFF2_CHAR_DETECT (1 << 5) |
| wim | 2:76cb93b511f2 | 189 | #define EFR_ENABLE_ENHANCED_FUNCTIONS (1 << 4) |
| wim | 2:76cb93b511f2 | 190 | // EFR[3:0] are used to define Software Flow Control mode |
| wim | 2:76cb93b511f2 | 191 | // See section 7.3 |
| wim | 2:76cb93b511f2 | 192 | #define EFR_DISABLE_TX_FLOW_CTRL (0x0 << 2) |
| wim | 2:76cb93b511f2 | 193 | #define EFR_TX_XON2_XOFF2 (0x1 << 2) |
| wim | 2:76cb93b511f2 | 194 | #define EFR_TX_XON1_XOFF1 (0x2 << 2) |
| wim | 2:76cb93b511f2 | 195 | #define EFR_TX_XON2_1_XOFF2_1 (0x3 << 2) |
| wim | 2:76cb93b511f2 | 196 | |
| wim | 2:76cb93b511f2 | 197 | #define EFR_DISABLE_RX_FLOW_CTRL (0x0 << 0) |
| wim | 2:76cb93b511f2 | 198 | #define EFR_RX_XON2_XOFF2 (0x1 << 0) |
| wim | 2:76cb93b511f2 | 199 | #define EFR_RX_XON1_XOFF1 (0x2 << 0) |
| wim | 2:76cb93b511f2 | 200 | #define EFR_RX_XON2_1_XOFF2_1 (0x3 << 0) |
| wim | 2:76cb93b511f2 | 201 | |
| wim | 2:76cb93b511f2 | 202 | #define EFR_TX_XON2_XOFF2_RX_FLOW (0x1 << 2) | (0x3 << 0) |
| wim | 2:76cb93b511f2 | 203 | #define EFR_TX_XON1_XOFF1_RX_FLOW (0x2 << 2) | (0x3 << 0) |
| wim | 2:76cb93b511f2 | 204 | #define EFR_TX_XON2_1_XOFF2_1_RX_FLOW (0x3 << 2) | (0x3 << 0) |
| wim | 1:0440152c5387 | 205 | |
| wim | 1:0440152c5387 | 206 | |
| wim | 1:0440152c5387 | 207 | |
| wim | 2:76cb93b511f2 | 208 | /** See section 8.12 of the datasheet for definitions |
| wim | 2:76cb93b511f2 | 209 | * of bits in the Transmission Control Register (TCR) |
| wim | 3:9783b6bde958 | 210 | * These levels control when RTS is asserted or de-asserted and auto RTS is enabled. Note that XON/XOFF is not supported in this lib. |
| wim | 3:9783b6bde958 | 211 | * Trigger level to halt transmission to the device : 0..15 (meaning 0-60 with a granularity of 4) |
| wim | 3:9783b6bde958 | 212 | * RTS is de-asserted when RX FIFO is above the set trigger level (i.e. buffer is getting full) |
| wim | 3:9783b6bde958 | 213 | * Trigger level to resume transmission to the device : 0..15 (meaning 0-60 with a granularity of 4) |
| wim | 3:9783b6bde958 | 214 | * RTS is asserted again when RX FIFO drops below the set trigger level (i.e. buffer has room again) |
| wim | 2:76cb93b511f2 | 215 | */ |
| wim | 2:76cb93b511f2 | 216 | #define TCR_HALT_DEFAULT (0x0E) |
| wim | 3:9783b6bde958 | 217 | #define TCR_RESUME_DEFAULT (0x08) |
| wim | 2:76cb93b511f2 | 218 | |
| wim | 3:9783b6bde958 | 219 | /** See section 8.12 of the datasheet for definitions |
| wim | 3:9783b6bde958 | 220 | * Note: The device will stop transmissions from the TX FIFO when CTS is de-asserted by external receiver and |
| wim | 3:9783b6bde958 | 221 | * auto CTS is enabled. Note that XON/XOFF is not supported in this lib. |
| wim | 3:9783b6bde958 | 222 | */ |
| wim | 2:76cb93b511f2 | 223 | |
| wim | 3:9783b6bde958 | 224 | |
| wim | 3:9783b6bde958 | 225 | /** See section 7.5 and 8.13 of the datasheet for definitions |
| wim | 3:9783b6bde958 | 226 | * of bits in the Trigger Level Register (TLR) control when an IRQ is generated. |
| wim | 2:76cb93b511f2 | 227 | * Trigger level for TX interrupt: 0..15 (meaning 0-60 with a granularity of 4) |
| wim | 3:9783b6bde958 | 228 | * IRQ when TX FIFO is above the set trigger level (i.e. buffer is getting full) |
| wim | 2:76cb93b511f2 | 229 | * Trigger level for RX interrupt: 0..15 (meaning 0-60 with a granularity of 4) |
| wim | 3:9783b6bde958 | 230 | * IRQ when RX FIFO is above the set trigger level (i.e. data is waiting to be read) |
| wim | 2:76cb93b511f2 | 231 | */ |
| wim | 2:76cb93b511f2 | 232 | #define TLR_TX_DEFAULT (0x0E) |
| wim | 2:76cb93b511f2 | 233 | #define TLR_RX_DEFAULT (0x04) |
| wim | 2:76cb93b511f2 | 234 | |
| wim | 2:76cb93b511f2 | 235 | |
| wim | 2:76cb93b511f2 | 236 | /** |
| wim | 3:9783b6bde958 | 237 | * See section 8.16, 8.17, 8.18 of the datasheet for definitions |
| wim | 3:9783b6bde958 | 238 | * of bits in the IO Direction (IODIR), IO State (IOSTATE) and IO Interrupt Enable register (IOINTENA) |
| wim | 3:9783b6bde958 | 239 | * |
| wim | 3:9783b6bde958 | 240 | * Basically a direct mapping of register bits to GPIO pin. |
| wim | 3:9783b6bde958 | 241 | */ |
| wim | 3:9783b6bde958 | 242 | |
| wim | 3:9783b6bde958 | 243 | |
| wim | 3:9783b6bde958 | 244 | /** |
| wim | 2:76cb93b511f2 | 245 | * See section 8.19 of the datasheet for definitions |
| wim | 2:76cb93b511f2 | 246 | * of bits in the IO Control register (IOC) |
| wim | 2:76cb93b511f2 | 247 | * |
| wim | 2:76cb93b511f2 | 248 | * Bit 0 is set to 0 to enable latch of IO inputs. |
| wim | 2:76cb93b511f2 | 249 | * Bit 1 is set to enable GPIO[7-4] as /RI, /CD, /DTR, /DST. |
| wim | 2:76cb93b511f2 | 250 | * Bit 2 is set to enable software reset. |
| wim | 2:76cb93b511f2 | 251 | */ |
| wim | 2:76cb93b511f2 | 252 | #define IOC_ENA_LATCH (0x01) |
| wim | 3:9783b6bde958 | 253 | #define IOC_ENA_MODEM (0x02) /* Set GPIO[7:4] pins to modem functions */ |
| wim | 3:9783b6bde958 | 254 | #define IOC_SW_RST (0x04) |
| wim | 3:9783b6bde958 | 255 | |
| wim | 2:76cb93b511f2 | 256 | |
| wim | 3:9783b6bde958 | 257 | /** |
| wim | 3:9783b6bde958 | 258 | * See section 8.20 of the datasheet for definitions |
| wim | 3:9783b6bde958 | 259 | * of bits in the Extra Features Control register (EFCR) |
| wim | 3:9783b6bde958 | 260 | * |
| wim | 3:9783b6bde958 | 261 | */ |
| wim | 3:9783b6bde958 | 262 | #define EFCR_ENA_RS485 (0x01) |
| wim | 3:9783b6bde958 | 263 | #define EFCR_DIS_RX (0x02) |
| wim | 3:9783b6bde958 | 264 | #define EFCR_DIS_TX (0x04) |
| wim | 3:9783b6bde958 | 265 | #define EFCR_ENA_TX_RTS (0x10) |
| wim | 3:9783b6bde958 | 266 | #define EFCR_INV_RTS_RS485 (0x20) |
| wim | 3:9783b6bde958 | 267 | #define EFCR_ENA_IRDA (0x80) |
| wim | 2:76cb93b511f2 | 268 | |
| wim | 0:d64854a60f95 | 269 | // See Chapter 11 of datasheet |
| wim | 2:76cb93b511f2 | 270 | #define SPI_READ_MODE_FLAG (0x80) |
| wim | 0:d64854a60f95 | 271 | |
| wim | 0:d64854a60f95 | 272 | |
| wim | 0:d64854a60f95 | 273 | /** Abstract class SC16IS750 for a converter between either SPI or I2C and a Serial port |
| wim | 0:d64854a60f95 | 274 | * |
| wim | 0:d64854a60f95 | 275 | * Supports both SPI and I2C interfaces through derived classes |
| wim | 0:d64854a60f95 | 276 | * |
| wim | 0:d64854a60f95 | 277 | * @code |
| wim | 0:d64854a60f95 | 278 | * |
| wim | 0:d64854a60f95 | 279 | * @endcode |
| wim | 0:d64854a60f95 | 280 | */ |
| wim | 3:9783b6bde958 | 281 | //class SC16IS750 { |
| wim | 3:9783b6bde958 | 282 | //class SC16IS750 : public SerialBase, public Stream { // Wrong, Serialbase can not be constructed for NC,NC |
| wim | 3:9783b6bde958 | 283 | class SC16IS750 : public Stream { |
| wim | 0:d64854a60f95 | 284 | public: |
| wim | 0:d64854a60f95 | 285 | |
| wim | 0:d64854a60f95 | 286 | // SC16IS750 Register definitions (shifted to align) |
| wim | 0:d64854a60f95 | 287 | enum RegisterName { |
| wim | 1:0440152c5387 | 288 | /* |
| wim | 1:0440152c5387 | 289 | * 16750 addresses. Registers accessed when LCR[7] = 0. |
| wim | 1:0440152c5387 | 290 | */ |
| wim | 1:0440152c5387 | 291 | RHR = 0x00 << 3, /* Rx buffer register - Read access */ |
| wim | 1:0440152c5387 | 292 | THR = 0x00 << 3, /* Tx holding register - Write access */ |
| wim | 1:0440152c5387 | 293 | IER = 0x01 << 3, /* Interrupt enable reg - RD/WR access */ |
| wim | 1:0440152c5387 | 294 | |
| wim | 1:0440152c5387 | 295 | /* |
| wim | 1:0440152c5387 | 296 | * 16750 addresses. Registers accessed when LCR[7] = 1. |
| wim | 1:0440152c5387 | 297 | */ |
| wim | 1:0440152c5387 | 298 | DLL = 0x00 << 3, /* Divisor latch (LSB) - RD/WR access */ |
| wim | 1:0440152c5387 | 299 | DLH = 0x01 << 3, /* Divisor latch (MSB) - RD/WR access */ |
| wim | 1:0440152c5387 | 300 | |
| wim | 1:0440152c5387 | 301 | /* |
| wim | 1:0440152c5387 | 302 | * 16750 addresses. IIR/FCR is accessed when LCR[7:0] <> 0xBF. |
| wim | 1:0440152c5387 | 303 | * Bit 5 of the FCR register is accessed when LCR[7] = 1. |
| wim | 1:0440152c5387 | 304 | */ |
| wim | 1:0440152c5387 | 305 | IIR = 0x02 << 3, /* Interrupt id. register - Read only */ |
| wim | 1:0440152c5387 | 306 | FCR = 0x02 << 3, /* FIFO control register - Write only */ |
| wim | 1:0440152c5387 | 307 | /* |
| wim | 1:0440152c5387 | 308 | * 16750 addresses. EFR is accessed when LCR[7:0] = 0xBF. |
| wim | 1:0440152c5387 | 309 | */ |
| wim | 1:0440152c5387 | 310 | EFR = 0x02 << 3, /* Enhanced features reg - RD/WR access */ |
| wim | 1:0440152c5387 | 311 | |
| wim | 1:0440152c5387 | 312 | /* |
| wim | 1:0440152c5387 | 313 | * 16750 addresses. |
| wim | 1:0440152c5387 | 314 | */ |
| wim | 1:0440152c5387 | 315 | LCR = 0x03 << 3, /* Line control register - RD/WR access */ |
| wim | 1:0440152c5387 | 316 | /* |
| wim | 1:0440152c5387 | 317 | * 16750 addresses. MCR/LSR is accessed when LCR[7:0] <> 0xBF. |
| wim | 1:0440152c5387 | 318 | * Bit 7 of the MCR register is accessed when EFR[4] = 1. |
| wim | 1:0440152c5387 | 319 | */ |
| wim | 1:0440152c5387 | 320 | MCR = 0x04 << 3, /* Modem control register - RD/WR access */ |
| wim | 1:0440152c5387 | 321 | LSR = 0x05 << 3, /* Line status register - Read only */ |
| wim | 1:0440152c5387 | 322 | |
| wim | 1:0440152c5387 | 323 | /* |
| wim | 1:0440152c5387 | 324 | * 16750 addresses. MSR/SPR is accessed when LCR[7:0] <> 0xBF. |
| wim | 1:0440152c5387 | 325 | * MSR, SPR register is accessed when EFR[1]=0 and MCR[2]=0. |
| wim | 1:0440152c5387 | 326 | */ |
| wim | 1:0440152c5387 | 327 | MSR = 0x06 << 3, /* Modem status register - Read only */ |
| wim | 1:0440152c5387 | 328 | SPR = 0x07 << 3, /* Scratchpad register - RD/WR access */ |
| wim | 1:0440152c5387 | 329 | /* |
| wim | 1:0440152c5387 | 330 | * 16750 addresses. TCR/TLR is accessed when LCR[7:0] <> 0xBF. |
| wim | 1:0440152c5387 | 331 | * TCR, TLR register is accessed when EFR[1]=1 and MCR[2]=1. |
| wim | 1:0440152c5387 | 332 | */ |
| wim | 1:0440152c5387 | 333 | TCR = 0x06 << 3, /* Transmission control register - RD/WR access */ |
| wim | 1:0440152c5387 | 334 | TLR = 0x07 << 3, /* Trigger level register - RD/WR access */ |
| wim | 1:0440152c5387 | 335 | |
| wim | 1:0440152c5387 | 336 | /* |
| wim | 1:0440152c5387 | 337 | * 16750 addresses. XON, XOFF is accessed when LCR[7:0] = 0xBF. |
| wim | 1:0440152c5387 | 338 | */ |
| wim | 1:0440152c5387 | 339 | XON1 = 0x04 << 3, /* XON1 register - RD/WR access */ |
| wim | 1:0440152c5387 | 340 | XON2 = 0x05 << 3, /* XON2 register - RD/WR access */ |
| wim | 1:0440152c5387 | 341 | XOFF1 = 0x06 << 3, /* XOFF1 register - RD/WR access */ |
| wim | 1:0440152c5387 | 342 | XOFF2 = 0x07 << 3, /* XOFF2 register - RD/WR access */ |
| wim | 1:0440152c5387 | 343 | |
| wim | 1:0440152c5387 | 344 | /* |
| wim | 1:0440152c5387 | 345 | * 16750 addresses. |
| wim | 1:0440152c5387 | 346 | */ |
| wim | 1:0440152c5387 | 347 | TXLVL = 0x08 << 3, /* TX FIFO Level register - Read only */ |
| wim | 1:0440152c5387 | 348 | RXLVL = 0x09 << 3, /* RX FIFO Level register - Read only */ |
| wim | 1:0440152c5387 | 349 | IODIR = 0x0A << 3, /* IO Pin Direction reg - RD/WR access */ |
| wim | 1:0440152c5387 | 350 | IOSTATE = 0x0B << 3, /* IO Pin State reg - Read only */ |
| wim | 1:0440152c5387 | 351 | IOINTENA = 0x0C << 3, /* IO Interrupt Enable - RD/WR access */ |
| wim | 1:0440152c5387 | 352 | // reserved = 0x0D << 3, |
| wim | 1:0440152c5387 | 353 | IOCTRL = 0x0E << 3, /* IO Control register - RD/WR access */ |
| wim | 1:0440152c5387 | 354 | EFCR = 0x0F << 3, /* Extra features reg - RD/WR access */ |
| wim | 1:0440152c5387 | 355 | |
| wim | 0:d64854a60f95 | 356 | } ; |
| wim | 0:d64854a60f95 | 357 | |
| wim | 0:d64854a60f95 | 358 | |
| wim | 1:0440152c5387 | 359 | // This enum used to be part of SerialBase class (access via SerialBase.h). |
| wim | 1:0440152c5387 | 360 | // It seems not be supported anymore. The enums for Parity have moved to Serial now.. |
| wim | 1:0440152c5387 | 361 | enum Flow { |
| wim | 1:0440152c5387 | 362 | Disabled = 0, |
| wim | 1:0440152c5387 | 363 | RTS, |
| wim | 1:0440152c5387 | 364 | CTS, |
| wim | 1:0440152c5387 | 365 | RTSCTS |
| wim | 1:0440152c5387 | 366 | }; |
| wim | 1:0440152c5387 | 367 | |
| wim | 1:0440152c5387 | 368 | |
| wim | 0:d64854a60f95 | 369 | // SC16IS750 configuration register values |
| wim | 1:0440152c5387 | 370 | // Several configuration registers are write-only. Need to save values to allow restoring. |
| wim | 0:d64854a60f95 | 371 | struct SC16IS750_cfg { |
| wim | 0:d64854a60f95 | 372 | char baudrate; |
| wim | 0:d64854a60f95 | 373 | char dataformat; |
| wim | 0:d64854a60f95 | 374 | char flowctrl; |
| wim | 1:0440152c5387 | 375 | char fifoformat; |
| wim | 1:0440152c5387 | 376 | bool fifoenable; |
| wim | 0:d64854a60f95 | 377 | }; |
| wim | 0:d64854a60f95 | 378 | |
| wim | 0:d64854a60f95 | 379 | |
| wim | 0:d64854a60f95 | 380 | /** Determine if there is a character available to read. |
| wim | 2:76cb93b511f2 | 381 | * This is data that's already arrived and stored in the receive |
| wim | 2:76cb93b511f2 | 382 | * buffer (which holds 64 chars). |
| wim | 2:76cb93b511f2 | 383 | * |
| wim | 0:d64854a60f95 | 384 | * @return 1 if there is a character available to read, 0 otherwise |
| wim | 0:d64854a60f95 | 385 | */ |
| wim | 1:0440152c5387 | 386 | int readable(); |
| wim | 0:d64854a60f95 | 387 | |
| wim | 2:76cb93b511f2 | 388 | /** Determine how many characters are available to read. |
| wim | 2:76cb93b511f2 | 389 | * This is data that's already arrived and stored in the receive |
| wim | 2:76cb93b511f2 | 390 | * buffer (which holds 64 chars). |
| wim | 2:76cb93b511f2 | 391 | * |
| wim | 0:d64854a60f95 | 392 | * @return int Characters available to read |
| wim | 2:76cb93b511f2 | 393 | */ |
| wim | 1:0440152c5387 | 394 | int readableCount(); |
| wim | 0:d64854a60f95 | 395 | |
| wim | 0:d64854a60f95 | 396 | /** Determine if there is space available to write a character. |
| wim | 0:d64854a60f95 | 397 | * @return 1 if there is a space for a character to write, 0 otherwise |
| wim | 0:d64854a60f95 | 398 | */ |
| wim | 1:0440152c5387 | 399 | int writable(); |
| wim | 0:d64854a60f95 | 400 | |
| wim | 2:76cb93b511f2 | 401 | |
| wim | 1:0440152c5387 | 402 | /** Determine how much space available for writing characters. |
| wim | 2:76cb93b511f2 | 403 | * This considers data that's already stored in the transmit |
| wim | 2:76cb93b511f2 | 404 | * buffer (which holds 64 chars). |
| wim | 2:76cb93b511f2 | 405 | * |
| wim | 1:0440152c5387 | 406 | * @return int character space available to write |
| wim | 2:76cb93b511f2 | 407 | */ |
| wim | 1:0440152c5387 | 408 | int writableCount(); |
| wim | 1:0440152c5387 | 409 | |
| wim | 0:d64854a60f95 | 410 | |
| wim | 1:0440152c5387 | 411 | /** |
| wim | 1:0440152c5387 | 412 | * Read char from UART Bridge. |
| wim | 1:0440152c5387 | 413 | * Acts in the same manner as 'Serial.read()'. |
| wim | 1:0440152c5387 | 414 | * @param none |
| wim | 1:0440152c5387 | 415 | * @return char read or -1 if no data available. |
| wim | 1:0440152c5387 | 416 | */ |
| wim | 1:0440152c5387 | 417 | int getc(); |
| wim | 1:0440152c5387 | 418 | |
| wim | 1:0440152c5387 | 419 | /** |
| wim | 1:0440152c5387 | 420 | * Write char to UART Bridge. Blocking when no free space in FIFO |
| wim | 1:0440152c5387 | 421 | * @param value char to be written |
| wim | 1:0440152c5387 | 422 | * @return value written |
| wim | 1:0440152c5387 | 423 | */ |
| wim | 1:0440152c5387 | 424 | int putc(int value); |
| wim | 1:0440152c5387 | 425 | |
| wim | 2:76cb93b511f2 | 426 | |
| wim | 2:76cb93b511f2 | 427 | /** |
| wim | 2:76cb93b511f2 | 428 | * Write char string to UART Bridge. Blocking when no free space in FIFO |
| wim | 2:76cb93b511f2 | 429 | * @param *str char string to be written |
| wim | 2:76cb93b511f2 | 430 | * @return none |
| wim | 2:76cb93b511f2 | 431 | */ |
| wim | 3:9783b6bde958 | 432 | void writeString(const char *str); |
| wim | 3:9783b6bde958 | 433 | |
| wim | 3:9783b6bde958 | 434 | |
| wim | 3:9783b6bde958 | 435 | /** |
| wim | 3:9783b6bde958 | 436 | * Write byte array to UART Bridge. Blocking when no free space in FIFO |
| wim | 3:9783b6bde958 | 437 | * @param *data byte array to be written |
| wim | 3:9783b6bde958 | 438 | * @param len number of bytes to write |
| wim | 3:9783b6bde958 | 439 | * @return none |
| wim | 3:9783b6bde958 | 440 | */ |
| wim | 3:9783b6bde958 | 441 | void writeBytes(const char *data, int len); |
| wim | 0:d64854a60f95 | 442 | |
| wim | 0:d64854a60f95 | 443 | /** Set baudrate of the serial port. |
| wim | 0:d64854a60f95 | 444 | * @param baud integer baudrate (4800, 9600 etc) |
| wim | 0:d64854a60f95 | 445 | * @return none |
| wim | 0:d64854a60f95 | 446 | */ |
| wim | 2:76cb93b511f2 | 447 | void baud(int baudrate = SC16IS750_DEFAULT_BAUDRATE); |
| wim | 0:d64854a60f95 | 448 | |
| wim | 0:d64854a60f95 | 449 | /** Set the transmission format used by the serial port. |
| wim | 0:d64854a60f95 | 450 | * @param bits The number of bits in a word (5-8; default = 8) |
| wim | 0:d64854a60f95 | 451 | * @param parity The parity used (Serial::None, Serial::Odd, Serial::Even, Serial::Forced1, Serial::Forced0; default = Serial::None) |
| wim | 0:d64854a60f95 | 452 | * @param stop_bits The number of stop bits (1 or 2; default = 1) |
| wim | 2:76cb93b511f2 | 453 | * @return none |
| wim | 0:d64854a60f95 | 454 | */ |
| wim | 1:0440152c5387 | 455 | void format(int bits=8, Serial::Parity parity=Serial::None, int stop_bits=1); |
| wim | 2:76cb93b511f2 | 456 | |
| wim | 1:0440152c5387 | 457 | #if(0) |
| wim | 1:0440152c5387 | 458 | /** Attach a function to call whenever a serial interrupt is generated |
| wim | 1:0440152c5387 | 459 | * |
| wim | 1:0440152c5387 | 460 | * @param fptr A pointer to a void function, or 0 to set as none |
| wim | 1:0440152c5387 | 461 | * @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty) |
| wim | 1:0440152c5387 | 462 | */ |
| wim | 1:0440152c5387 | 463 | void attach(void (*fptr)(void), IrqType type=RxIrq); |
| wim | 1:0440152c5387 | 464 | |
| wim | 1:0440152c5387 | 465 | /** Attach a member function to call whenever a serial interrupt is generated |
| wim | 1:0440152c5387 | 466 | * |
| wim | 1:0440152c5387 | 467 | * @param tptr pointer to the object to call the member function on |
| wim | 1:0440152c5387 | 468 | * @param mptr pointer to the member function to be called |
| wim | 1:0440152c5387 | 469 | * @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty) |
| wim | 2:76cb93b511f2 | 470 | * @return none |
| wim | 1:0440152c5387 | 471 | */ |
| wim | 1:0440152c5387 | 472 | template<typename T> |
| wim | 1:0440152c5387 | 473 | void attach(T* tptr, void (T::*mptr)(void), IrqType type=RxIrq) { |
| wim | 1:0440152c5387 | 474 | if((mptr != NULL) && (tptr != NULL)) { |
| wim | 1:0440152c5387 | 475 | _irq[type].attach(tptr, mptr); |
| wim | 1:0440152c5387 | 476 | serial_irq_set(&_serial, (SerialIrq)type, 1); |
| wim | 1:0440152c5387 | 477 | } |
| wim | 1:0440152c5387 | 478 | } |
| wim | 1:0440152c5387 | 479 | #endif |
| wim | 1:0440152c5387 | 480 | |
| wim | 1:0440152c5387 | 481 | /** Generate a break condition on the serial line |
| wim | 2:76cb93b511f2 | 482 | * @param none |
| wim | 2:76cb93b511f2 | 483 | * @return none |
| wim | 1:0440152c5387 | 484 | */ |
| wim | 1:0440152c5387 | 485 | void send_break(); |
| wim | 0:d64854a60f95 | 486 | |
| wim | 1:0440152c5387 | 487 | |
| wim | 1:0440152c5387 | 488 | /** Set a break condition on the serial line |
| wim | 1:0440152c5387 | 489 | * @param enable break condition |
| wim | 2:76cb93b511f2 | 490 | * @return none |
| wim | 1:0440152c5387 | 491 | */ |
| wim | 1:0440152c5387 | 492 | void set_break(bool enable=false); |
| wim | 1:0440152c5387 | 493 | |
| wim | 1:0440152c5387 | 494 | |
| wim | 1:0440152c5387 | 495 | /** Set the flow control type on the serial port |
| wim | 1:0440152c5387 | 496 | * Added for compatibility with Serial Class. |
| wim | 2:76cb93b511f2 | 497 | * SC16IS750 supports only Flow, Pins can not be selected. |
| wim | 3:9783b6bde958 | 498 | * This method sets hardware flow control levels. SC16IS750 supports XON/XOFF, but this is not implemented. |
| wim | 1:0440152c5387 | 499 | * |
| wim | 1:0440152c5387 | 500 | * @param type the flow control type (Disabled, RTS, CTS, RTSCTS) |
| wim | 1:0440152c5387 | 501 | * @param flow1 the first flow control pin (RTS for RTS or RTSCTS, CTS for CTS) |
| wim | 1:0440152c5387 | 502 | * @param flow2 the second flow control pin (CTS for RTSCTS) |
| wim | 2:76cb93b511f2 | 503 | * @return none |
| wim | 1:0440152c5387 | 504 | */ |
| wim | 1:0440152c5387 | 505 | void set_flow_control(Flow type=Disabled, PinName flow1=NC, PinName flow2=NC); |
| wim | 2:76cb93b511f2 | 506 | |
| wim | 2:76cb93b511f2 | 507 | |
| wim | 2:76cb93b511f2 | 508 | /** Set the RX FIFO flow control levels |
| wim | 3:9783b6bde958 | 509 | * This method sets hardware flow control levels. SC16IS750 supports XON/XOFF, but this is not implemented. |
| wim | 2:76cb93b511f2 | 510 | * Should be called BEFORE Auto RTS is enabled. |
| wim | 2:76cb93b511f2 | 511 | * |
| wim | 2:76cb93b511f2 | 512 | * @param resume trigger level to resume transmission (0..15, meaning 0-60 with a granularity of 4) |
| wim | 2:76cb93b511f2 | 513 | * @param halt trigger level to resume transmission (0..15, meaning 0-60 with granularity of 4) |
| wim | 2:76cb93b511f2 | 514 | * @return none |
| wim | 2:76cb93b511f2 | 515 | */ |
| wim | 2:76cb93b511f2 | 516 | void set_flow_triggers(int resume = TCR_RESUME_DEFAULT, int halt = TCR_HALT_DEFAULT); |
| wim | 2:76cb93b511f2 | 517 | |
| wim | 2:76cb93b511f2 | 518 | |
| wim | 2:76cb93b511f2 | 519 | /** Set the Modem Control register |
| wim | 2:76cb93b511f2 | 520 | * This method sets prescaler, enables TCR and TLR |
| wim | 2:76cb93b511f2 | 521 | * |
| wim | 2:76cb93b511f2 | 522 | * @param none |
| wim | 2:76cb93b511f2 | 523 | * @return none |
| wim | 2:76cb93b511f2 | 524 | */ |
| wim | 2:76cb93b511f2 | 525 | void set_modem_control(); |
| wim | 2:76cb93b511f2 | 526 | |
| wim | 1:0440152c5387 | 527 | |
| wim | 0:d64854a60f95 | 528 | /** |
| wim | 0:d64854a60f95 | 529 | * Check that UART is connected and operational. |
| wim | 0:d64854a60f95 | 530 | * @param none |
| wim | 0:d64854a60f95 | 531 | * @return bool true when connected, false otherwise |
| wim | 0:d64854a60f95 | 532 | */ |
| wim | 0:d64854a60f95 | 533 | bool connected(); |
| wim | 0:d64854a60f95 | 534 | |
| wim | 0:d64854a60f95 | 535 | |
| wim | 2:76cb93b511f2 | 536 | |
| wim | 3:9783b6bde958 | 537 | /** FIFO control, sets TX and RX IRQ trigger levels and enables FIFO and save in _config |
| wim | 2:76cb93b511f2 | 538 | * Note FCR[5:4] (=TX_IRQ_LVL) only accessible when EFR[4] is set (enhanced functions enable) |
| wim | 2:76cb93b511f2 | 539 | * Note TLR only accessible when EFR[4] is set (enhanced functions enable) and MCR[2] is set |
| wim | 2:76cb93b511f2 | 540 | * @param none |
| wim | 2:76cb93b511f2 | 541 | * @return none |
| wim | 2:76cb93b511f2 | 542 | */ |
| wim | 2:76cb93b511f2 | 543 | void set_fifo_control(); |
| wim | 2:76cb93b511f2 | 544 | |
| wim | 1:0440152c5387 | 545 | |
| wim | 1:0440152c5387 | 546 | /** Flush the UART FIFOs while maintaining current FIFO mode. |
| wim | 1:0440152c5387 | 547 | * @param none |
| wim | 1:0440152c5387 | 548 | * @return none |
| wim | 1:0440152c5387 | 549 | */ |
| wim | 1:0440152c5387 | 550 | void flush(); |
| wim | 0:d64854a60f95 | 551 | |
| wim | 1:0440152c5387 | 552 | |
| wim | 1:0440152c5387 | 553 | /** Set direction of I/O port pins. |
| wim | 1:0440152c5387 | 554 | * This method is specific to the SPI-I2C UART and not found on the 16750 |
| wim | 1:0440152c5387 | 555 | * @param bits Bitpattern for I/O (1=output, 0=input) |
| wim | 1:0440152c5387 | 556 | * @return none |
| wim | 1:0440152c5387 | 557 | */ |
| wim | 1:0440152c5387 | 558 | void ioSetDirection(unsigned char bits); |
| wim | 0:d64854a60f95 | 559 | |
| wim | 1:0440152c5387 | 560 | /** Set bits of I/O port pins. |
| wim | 1:0440152c5387 | 561 | * This method is specific to the SPI-I2C UART and not found on the 16750 |
| wim | 1:0440152c5387 | 562 | * @param bits Bitpattern for I/O (1= set output bit, 0 = clear output bit) |
| wim | 1:0440152c5387 | 563 | * @return none |
| wim | 1:0440152c5387 | 564 | */ |
| wim | 1:0440152c5387 | 565 | void ioSetState(unsigned char bits); |
| wim | 1:0440152c5387 | 566 | |
| wim | 1:0440152c5387 | 567 | /** Get bits of I/O port pins. |
| wim | 1:0440152c5387 | 568 | * This method is specific to the SPI-I2C UART and not found on the 16750 |
| wim | 1:0440152c5387 | 569 | * @param none |
| wim | 1:0440152c5387 | 570 | * @return bits Bitpattern for I/O (1= bit set, 0 = bit cleared) |
| wim | 1:0440152c5387 | 571 | */ |
| wim | 1:0440152c5387 | 572 | unsigned char ioGetState(); |
| wim | 1:0440152c5387 | 573 | |
| wim | 1:0440152c5387 | 574 | |
| wim | 1:0440152c5387 | 575 | /** Software Reset SC16IS750 device. |
| wim | 1:0440152c5387 | 576 | * This method is specific to the SPI-I2C UART and not found on the 16750 |
| wim | 1:0440152c5387 | 577 | * @param none |
| wim | 1:0440152c5387 | 578 | * @return none |
| wim | 1:0440152c5387 | 579 | */ |
| wim | 1:0440152c5387 | 580 | void swReset(); |
| wim | 1:0440152c5387 | 581 | |
| wim | 0:d64854a60f95 | 582 | |
| wim | 0:d64854a60f95 | 583 | /** Write value to internal register. |
| wim | 0:d64854a60f95 | 584 | * Pure virtual, must be declared in derived class. |
| wim | 1:0440152c5387 | 585 | * @param registerAddress The address of the Register (enum RegisterName) |
| wim | 0:d64854a60f95 | 586 | * @param data The 8bit value to write |
| wim | 0:d64854a60f95 | 587 | * @return none |
| wim | 0:d64854a60f95 | 588 | */ |
| wim | 1:0440152c5387 | 589 | virtual void writeRegister (RegisterName register_address, char data ) =0; |
| wim | 0:d64854a60f95 | 590 | |
| wim | 0:d64854a60f95 | 591 | /** Read value from internal register. |
| wim | 0:d64854a60f95 | 592 | * Pure virtual, must be declared in derived class. |
| wim | 1:0440152c5387 | 593 | * @param registerAddress The address of the Register (enum RegisterName) |
| wim | 0:d64854a60f95 | 594 | * @return char The 8bit value read from the register |
| wim | 0:d64854a60f95 | 595 | */ |
| wim | 1:0440152c5387 | 596 | virtual char readRegister (RegisterName register_address ) =0; |
| wim | 1:0440152c5387 | 597 | |
| wim | 3:9783b6bde958 | 598 | /** Write multiple datavalues to Transmitregister. |
| wim | 3:9783b6bde958 | 599 | * More Efficient implementation than writing individual bytes |
| wim | 3:9783b6bde958 | 600 | * Pure virtual, must be declared in derived class. |
| wim | 3:9783b6bde958 | 601 | * @param char* databytes The pointer to the block of data |
| wim | 3:9783b6bde958 | 602 | * @param len The number of bytes to write |
| wim | 3:9783b6bde958 | 603 | * @return none |
| wim | 3:9783b6bde958 | 604 | */ |
| wim | 3:9783b6bde958 | 605 | virtual void writeDataBlock (const char *data, int len ) =0; |
| wim | 3:9783b6bde958 | 606 | |
| wim | 0:d64854a60f95 | 607 | |
| wim | 1:0440152c5387 | 608 | /** Initialise internal registers |
| wim | 1:0440152c5387 | 609 | * Should be in protection section. Public for testing purposes |
| wim | 1:0440152c5387 | 610 | * If initialisation fails this method does not return. |
| wim | 1:0440152c5387 | 611 | * @param none |
| wim | 1:0440152c5387 | 612 | * @return none |
| wim | 1:0440152c5387 | 613 | */ |
| wim | 1:0440152c5387 | 614 | void _init(); |
| wim | 1:0440152c5387 | 615 | |
| wim | 0:d64854a60f95 | 616 | protected: |
| wim | 0:d64854a60f95 | 617 | //protected is accessible to derived classes, but not to external users |
| wim | 0:d64854a60f95 | 618 | |
| wim | 2:76cb93b511f2 | 619 | |
| wim | 2:76cb93b511f2 | 620 | /** Constructor is protected for this abstract Class |
| wim | 1:0440152c5387 | 621 | * |
| wim | 1:0440152c5387 | 622 | */ |
| wim | 1:0440152c5387 | 623 | SC16IS750(); |
| wim | 1:0440152c5387 | 624 | |
| wim | 3:9783b6bde958 | 625 | /** Needed to implement Stream |
| wim | 3:9783b6bde958 | 626 | * |
| wim | 3:9783b6bde958 | 627 | * Read char from UART Bridge. |
| wim | 3:9783b6bde958 | 628 | * Acts in the same manner as 'Serial.read()'. |
| wim | 3:9783b6bde958 | 629 | * @param none |
| wim | 3:9783b6bde958 | 630 | * @return char read or -1 if no data available. |
| wim | 3:9783b6bde958 | 631 | */ |
| wim | 3:9783b6bde958 | 632 | virtual int _getc() { |
| wim | 3:9783b6bde958 | 633 | return getc(); |
| wim | 3:9783b6bde958 | 634 | } |
| wim | 3:9783b6bde958 | 635 | |
| wim | 3:9783b6bde958 | 636 | |
| wim | 3:9783b6bde958 | 637 | /** Needed to implement Stream |
| wim | 3:9783b6bde958 | 638 | * |
| wim | 3:9783b6bde958 | 639 | * Write char to UART Bridge. Blocking when no free space in FIFO |
| wim | 3:9783b6bde958 | 640 | * @param value char to be written |
| wim | 3:9783b6bde958 | 641 | * @return value written |
| wim | 3:9783b6bde958 | 642 | */ |
| wim | 3:9783b6bde958 | 643 | virtual int _putc(int c) { |
| wim | 3:9783b6bde958 | 644 | return putc(c); |
| wim | 3:9783b6bde958 | 645 | } |
| wim | 3:9783b6bde958 | 646 | |
| wim | 3:9783b6bde958 | 647 | /** Needed to implement Stream |
| wim | 3:9783b6bde958 | 648 | * |
| wim | 3:9783b6bde958 | 649 | */ |
| wim | 3:9783b6bde958 | 650 | virtual int peek() {return 0;}; |
| wim | 3:9783b6bde958 | 651 | |
| wim | 2:76cb93b511f2 | 652 | // Save config settings |
| wim | 0:d64854a60f95 | 653 | SC16IS750_cfg _config; |
| wim | 0:d64854a60f95 | 654 | |
| wim | 0:d64854a60f95 | 655 | private: |
| wim | 0:d64854a60f95 | 656 | //private is not accessible to derived classes, nor external users |
| wim | 1:0440152c5387 | 657 | |
| wim | 0:d64854a60f95 | 658 | }; |
| wim | 0:d64854a60f95 | 659 | |
| wim | 0:d64854a60f95 | 660 | |
| wim | 0:d64854a60f95 | 661 | |
| wim | 0:d64854a60f95 | 662 | /** Class SC16IS750_SPI for a converter between SPI and a Serial port |
| wim | 0:d64854a60f95 | 663 | * |
| wim | 0:d64854a60f95 | 664 | * @code |
| wim | 0:d64854a60f95 | 665 | * #include "mbed.h" |
| wim | 0:d64854a60f95 | 666 | * #include "SC16IS750.h" |
| wim | 0:d64854a60f95 | 667 | * |
| wim | 0:d64854a60f95 | 668 | * SPI spi(PTD2, PTD3, PTD1); //MOSI, MISO, SCK |
| wim | 0:d64854a60f95 | 669 | * SC16IS750_SPI serial_spi(&spi, PTD0); |
| wim | 0:d64854a60f95 | 670 | * |
| wim | 0:d64854a60f95 | 671 | * Serial pc(USBTX,USBRX); |
| wim | 0:d64854a60f95 | 672 | * |
| wim | 0:d64854a60f95 | 673 | * int main() { |
| wim | 0:d64854a60f95 | 674 | * pc.printf("\nHello World!\n"); |
| wim | 0:d64854a60f95 | 675 | * |
| wim | 0:d64854a60f95 | 676 | * while(1) { |
| wim | 0:d64854a60f95 | 677 | * serial_spi.ioSetState(0x00); |
| wim | 0:d64854a60f95 | 678 | * wait(0.5); |
| wim | 2:76cb93b511f2 | 679 | * serial_spi.ioSetState(0xFF); |
| wim | 2:76cb93b511f2 | 680 | * wait(0.5); |
| wim | 2:76cb93b511f2 | 681 | * serial_spi.putc('*'); |
| wim | 0:d64854a60f95 | 682 | * pc.putc('*'); |
| wim | 0:d64854a60f95 | 683 | * } |
| wim | 0:d64854a60f95 | 684 | * } |
| wim | 0:d64854a60f95 | 685 | * |
| wim | 0:d64854a60f95 | 686 | * @endcode |
| wim | 0:d64854a60f95 | 687 | */ |
| wim | 0:d64854a60f95 | 688 | class SC16IS750_SPI : public SC16IS750 { |
| wim | 0:d64854a60f95 | 689 | public: |
| wim | 0:d64854a60f95 | 690 | |
| wim | 0:d64854a60f95 | 691 | /** Create a SC16IS750_SPI object using a specified SPI bus and CS |
| wim | 0:d64854a60f95 | 692 | * |
| wim | 0:d64854a60f95 | 693 | * @param SPI &spi the SPI port to connect to |
| wim | 0:d64854a60f95 | 694 | * @param cs the Pin of the CS |
| wim | 0:d64854a60f95 | 695 | */ |
| wim | 0:d64854a60f95 | 696 | SC16IS750_SPI(SPI *spi, PinName cs); |
| wim | 0:d64854a60f95 | 697 | |
| wim | 0:d64854a60f95 | 698 | /** Write value to internal register. |
| wim | 1:0440152c5387 | 699 | * @param registerAddress The address of the Register (enum RegisterName) |
| wim | 0:d64854a60f95 | 700 | * @param data The 8bit value to write |
| wim | 0:d64854a60f95 | 701 | * @return none |
| wim | 0:d64854a60f95 | 702 | */ |
| wim | 0:d64854a60f95 | 703 | virtual void writeRegister(SC16IS750::RegisterName registerAddress, char data); |
| wim | 0:d64854a60f95 | 704 | |
| wim | 0:d64854a60f95 | 705 | /** Read value from internal register. |
| wim | 1:0440152c5387 | 706 | * @param registerAddress The address of the Register (enum RegisterName) |
| wim | 0:d64854a60f95 | 707 | * @return char The 8bit value read from the register |
| wim | 0:d64854a60f95 | 708 | */ |
| wim | 0:d64854a60f95 | 709 | virtual char readRegister(SC16IS750::RegisterName registerAddress); |
| wim | 0:d64854a60f95 | 710 | |
| wim | 3:9783b6bde958 | 711 | /** Write multiple datavalues to Transmitregister. |
| wim | 3:9783b6bde958 | 712 | * More Efficient implementation than writing individual bytes |
| wim | 3:9783b6bde958 | 713 | * Assume that previous check confirmed that the FIFO has sufficient free space to store the data |
| wim | 3:9783b6bde958 | 714 | * Pure virtual, must be declared in derived class. |
| wim | 3:9783b6bde958 | 715 | * @param char* databytes The pointer to the block of data |
| wim | 3:9783b6bde958 | 716 | * @param len The number of bytes to write |
| wim | 3:9783b6bde958 | 717 | * @return none |
| wim | 3:9783b6bde958 | 718 | */ |
| wim | 3:9783b6bde958 | 719 | virtual void writeDataBlock (const char *data, int len ); |
| wim | 3:9783b6bde958 | 720 | |
| wim | 3:9783b6bde958 | 721 | |
| wim | 0:d64854a60f95 | 722 | protected: |
| wim | 0:d64854a60f95 | 723 | //protected is accessible to derived classes, but not to external users |
| wim | 0:d64854a60f95 | 724 | |
| wim | 0:d64854a60f95 | 725 | |
| wim | 0:d64854a60f95 | 726 | private: |
| wim | 0:d64854a60f95 | 727 | SPI *_spi; //SPI bus reference |
| wim | 0:d64854a60f95 | 728 | DigitalOut _cs; //CS of SPI device |
| wim | 0:d64854a60f95 | 729 | |
| wim | 0:d64854a60f95 | 730 | }; |
| wim | 0:d64854a60f95 | 731 | |
| wim | 0:d64854a60f95 | 732 | |
| wim | 0:d64854a60f95 | 733 | |
| wim | 0:d64854a60f95 | 734 | /** Class SC16IS750_I2C for a converter between I2C and a Serial port |
| wim | 0:d64854a60f95 | 735 | * |
| wim | 0:d64854a60f95 | 736 | * @code |
| wim | 0:d64854a60f95 | 737 | * #include "mbed.h" |
| wim | 0:d64854a60f95 | 738 | * #include "SC16IS750.h" |
| wim | 0:d64854a60f95 | 739 | * |
| wim | 0:d64854a60f95 | 740 | * I2C i2c(PTE0, PTE1); //SDA, SCL |
| wim | 0:d64854a60f95 | 741 | * SC16IS750_I2C serial_i2c(&i2c, DEFAULT_SC16IS750_ADDR); |
| wim | 0:d64854a60f95 | 742 | * |
| wim | 0:d64854a60f95 | 743 | * Serial pc(USBTX,USBRX); |
| wim | 0:d64854a60f95 | 744 | * |
| wim | 0:d64854a60f95 | 745 | * int main() { |
| wim | 0:d64854a60f95 | 746 | * pc.printf("\nHello World!\n"); |
| wim | 0:d64854a60f95 | 747 | * |
| wim | 0:d64854a60f95 | 748 | * while(1) { |
| wim | 0:d64854a60f95 | 749 | * serial_i2c.ioSetState(0x00); |
| wim | 0:d64854a60f95 | 750 | * wait(0.5); |
| wim | 2:76cb93b511f2 | 751 | * serial_i2c.ioSetState(0xFF); |
| wim | 2:76cb93b511f2 | 752 | * wait(0.5); |
| wim | 2:76cb93b511f2 | 753 | * serial_i2c.putc('*'); |
| wim | 0:d64854a60f95 | 754 | * pc.putc('*'); |
| wim | 0:d64854a60f95 | 755 | * } |
| wim | 0:d64854a60f95 | 756 | * } |
| wim | 0:d64854a60f95 | 757 | * |
| wim | 0:d64854a60f95 | 758 | * @endcode |
| wim | 0:d64854a60f95 | 759 | */ |
| wim | 0:d64854a60f95 | 760 | class SC16IS750_I2C : public SC16IS750 { |
| wim | 0:d64854a60f95 | 761 | public: |
| wim | 0:d64854a60f95 | 762 | |
| wim | 0:d64854a60f95 | 763 | /** Create a SC16IS750_I2C object using a specified I2C bus and slaveaddress |
| wim | 0:d64854a60f95 | 764 | * |
| wim | 0:d64854a60f95 | 765 | * @param I2C &i2c the I2C port to connect to |
| wim | 0:d64854a60f95 | 766 | * @param char deviceAddress the address of the SC16IS750 |
| wim | 0:d64854a60f95 | 767 | */ |
| wim | 2:76cb93b511f2 | 768 | SC16IS750_I2C(I2C *i2c, uint8_t deviceAddress = SC16IS750_DEFAULT_ADDR); |
| wim | 0:d64854a60f95 | 769 | |
| wim | 0:d64854a60f95 | 770 | /** Write value to internal register. |
| wim | 1:0440152c5387 | 771 | * @param registerAddress The address of the Register (enum RegisterName) |
| wim | 0:d64854a60f95 | 772 | * @param data The 8bit value to write |
| wim | 0:d64854a60f95 | 773 | * @return none |
| wim | 0:d64854a60f95 | 774 | */ |
| wim | 0:d64854a60f95 | 775 | virtual void writeRegister(SC16IS750::RegisterName register_address, char data ); |
| wim | 0:d64854a60f95 | 776 | |
| wim | 0:d64854a60f95 | 777 | /** Read value from internal register. |
| wim | 1:0440152c5387 | 778 | * @param registerAddress The address of the Register (enum RegisterName) |
| wim | 0:d64854a60f95 | 779 | * @return char The 8bit value read from the register |
| wim | 0:d64854a60f95 | 780 | */ |
| wim | 0:d64854a60f95 | 781 | virtual char readRegister(SC16IS750::RegisterName register_address ); |
| wim | 0:d64854a60f95 | 782 | |
| wim | 3:9783b6bde958 | 783 | |
| wim | 3:9783b6bde958 | 784 | /** Write multiple datavalues to Transmitregister. |
| wim | 3:9783b6bde958 | 785 | * More Efficient implementation than writing individual bytes |
| wim | 3:9783b6bde958 | 786 | * Assume that previous check confirmed that the FIFO has sufficient free space to store the data |
| wim | 3:9783b6bde958 | 787 | * Pure virtual, must be declared in derived class. |
| wim | 3:9783b6bde958 | 788 | * @param char* databytes The pointer to the block of data |
| wim | 3:9783b6bde958 | 789 | * @param len The number of bytes to write |
| wim | 3:9783b6bde958 | 790 | * @return none |
| wim | 3:9783b6bde958 | 791 | */ |
| wim | 3:9783b6bde958 | 792 | virtual void writeDataBlock (const char *data, int len ); |
| wim | 3:9783b6bde958 | 793 | |
| wim | 0:d64854a60f95 | 794 | protected: |
| wim | 0:d64854a60f95 | 795 | //protected is accessible to derived classes, but not to external users |
| wim | 0:d64854a60f95 | 796 | |
| wim | 0:d64854a60f95 | 797 | |
| wim | 0:d64854a60f95 | 798 | private: |
| wim | 0:d64854a60f95 | 799 | I2C *_i2c; //I2C bus reference |
| wim | 0:d64854a60f95 | 800 | uint8_t _slaveAddress; //I2C Slave address of device |
| wim | 0:d64854a60f95 | 801 | |
| wim | 0:d64854a60f95 | 802 | }; |
| wim | 0:d64854a60f95 | 803 | |
| wim | 0:d64854a60f95 | 804 | |
| wim | 0:d64854a60f95 | 805 | #endif // _SC16IS750_H |