Randal Riedinger
RETRO ROBOT E
Dependents: RETRO_ROBOT_SC16IS750E
Fork of
SC16IS750
by 
Wim Huiskamp
SC16IS750.h@4:12446ee9f9c8, 2014-12-22 (annotated)
- Committer:
- wim
- Date:
- Mon Dec 22 19:04:38 2014 +0000
- Revision:
- 4:12446ee9f9c8
- Parent:
- 3:9783b6bde958
- Child:
- 5:ff3e57bebb6a
Added support for SC16IS752 Dual UART device.
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| wim | 3:9783b6bde958 | 1 | /* SC16IS750 I2C or SPI to UART bridge |
| wim | 3:9783b6bde958 | 2 | * v0.1 WH, Nov 2013, Sparkfun WiFly Shield code library alpha 0 used as example, Added I2C I/F and many more methods. |
| wim | 3:9783b6bde958 | 3 | * https://forum.sparkfun.com/viewtopic.php?f=13&t=21846 |
| wim | 4:12446ee9f9c8 | 4 | * v0.2 WH, Feb 2014, Added Doxygen Documentation, Added Hardware Reset pin methods. |
| wim | 4:12446ee9f9c8 | 5 | * v0.3 WH, Dec 2014, Added support for SC16IS752 dual UART. |
| wim | 0:d64854a60f95 | 6 | * |
| wim | 0:d64854a60f95 | 7 | * Permission is hereby granted, free of charge, to any person obtaining a copy of this software |
| wim | 0:d64854a60f95 | 8 | * and associated documentation files (the "Software"), to deal in the Software without restriction, |
| wim | 0:d64854a60f95 | 9 | * including without limitation the rights to use, copy, modify, merge, publish, distribute, |
| wim | 0:d64854a60f95 | 10 | * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is |
| wim | 0:d64854a60f95 | 11 | * furnished to do so, subject to the following conditions: |
| wim | 0:d64854a60f95 | 12 | * |
| wim | 0:d64854a60f95 | 13 | * The above copyright notice and this permission notice shall be included in all copies or |
| wim | 0:d64854a60f95 | 14 | * substantial portions of the Software. |
| wim | 0:d64854a60f95 | 15 | * |
| wim | 0:d64854a60f95 | 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING |
| wim | 0:d64854a60f95 | 17 | * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| wim | 0:d64854a60f95 | 18 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, |
| wim | 0:d64854a60f95 | 19 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| wim | 0:d64854a60f95 | 20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| wim | 0:d64854a60f95 | 21 | */ |
| wim | 0:d64854a60f95 | 22 | #ifndef _SC16IS750_H |
| wim | 0:d64854a60f95 | 23 | #define _SC16IS750_H |
| wim | 0:d64854a60f95 | 24 | |
| wim | 3:9783b6bde958 | 25 | |
| wim | 3:9783b6bde958 | 26 | #include "Stream.h" |
| wim | 3:9783b6bde958 | 27 | //#include <SerialBase.h> |
| wim | 3:9783b6bde958 | 28 | |
| wim | 1:0440152c5387 | 29 | //I2C Slaveaddresses A1 A0 |
| wim | 2:76cb93b511f2 | 30 | #define SC16IS750_SA0 0x90 /* VDD VDD */ |
| wim | 2:76cb93b511f2 | 31 | #define SC16IS750_SA1 0x92 /* VDD VSS */ |
| wim | 2:76cb93b511f2 | 32 | #define SC16IS750_SA2 0x94 /* VDD SCL */ |
| wim | 2:76cb93b511f2 | 33 | #define SC16IS750_SA3 0x95 /* VDD SDA */ |
| wim | 2:76cb93b511f2 | 34 | #define SC16IS750_SA4 0x98 /* VSS VDD */ |
| wim | 2:76cb93b511f2 | 35 | #define SC16IS750_SA5 0x9A /* VSS VSS */ |
| wim | 2:76cb93b511f2 | 36 | #define SC16IS750_SA6 0x9C /* VSS SCL */ |
| wim | 2:76cb93b511f2 | 37 | #define SC16IS750_SA7 0x9E /* VSS SDA */ |
| wim | 2:76cb93b511f2 | 38 | #define SC16IS750_SA8 0xA0 /* SCL VDD */ |
| wim | 2:76cb93b511f2 | 39 | #define SC16IS750_SA9 0xA2 /* SCL VSS */ |
| wim | 2:76cb93b511f2 | 40 | #define SC16IS750_SA10 0xA4 /* SCL SCL */ |
| wim | 2:76cb93b511f2 | 41 | #define SC16IS750_SA11 0xA6 /* SCL SDA */ |
| wim | 2:76cb93b511f2 | 42 | #define SC16IS750_SA12 0xA8 /* SDA VDD */ |
| wim | 2:76cb93b511f2 | 43 | #define SC16IS750_SA13 0xAA /* SDA VSS */ |
| wim | 2:76cb93b511f2 | 44 | #define SC16IS750_SA14 0xAC /* SDA SCL */ |
| wim | 2:76cb93b511f2 | 45 | #define SC16IS750_SA15 0xAE /* SDA SDA */ |
| wim | 1:0440152c5387 | 46 | |
| wim | 0:d64854a60f95 | 47 | //Default I2C Slaveaddress |
| wim | 2:76cb93b511f2 | 48 | #define SC16IS750_DEFAULT_ADDR SC16IS750_SA0 |
| wim | 2:76cb93b511f2 | 49 | |
| wim | 2:76cb93b511f2 | 50 | |
| wim | 2:76cb93b511f2 | 51 | /** See datasheet section 7.8 for configuring the |
| wim | 2:76cb93b511f2 | 52 | * "Programmable baud rate generator" |
| wim | 2:76cb93b511f2 | 53 | */ |
| wim | 2:76cb93b511f2 | 54 | #define SC16IS750_XTAL_FREQ 14745600UL /* On-board crystal (New mid-2010 Version) */ |
| wim | 2:76cb93b511f2 | 55 | #define SC16IS750_PRESCALER_1 1 /* Default prescaler after reset */ |
| wim | 2:76cb93b511f2 | 56 | #define SC16IS750_PRESCALER_4 4 /* Selectable by setting MCR[7] */ |
| wim | 2:76cb93b511f2 | 57 | #define SC16IS750_PRESCALER SC16IS750_PRESCALER_1 |
| wim | 2:76cb93b511f2 | 58 | #define SC16IS750_BAUDRATE_DIVISOR(baud) ((SC16IS750_XTAL_FREQ/SC16IS750_PRESCALER)/(baud*16UL)) |
| wim | 0:d64854a60f95 | 59 | |
| wim | 0:d64854a60f95 | 60 | //Default baudrate |
| wim | 3:9783b6bde958 | 61 | #define SC16IS750_DEFAULT_BAUDRATE 9600 |
| wim | 0:d64854a60f95 | 62 | |
| wim | 1:0440152c5387 | 63 | |
| wim | 2:76cb93b511f2 | 64 | /** See section 8.3 of the datasheet for definitions |
| wim | 2:76cb93b511f2 | 65 | * of bits in the FIFO Control Register (FCR) |
| wim | 2:76cb93b511f2 | 66 | */ |
| wim | 2:76cb93b511f2 | 67 | #define FCR_RX_IRQ_60 (3 << 6) |
| wim | 2:76cb93b511f2 | 68 | #define FCR_RX_IRQ_56 (2 << 6) |
| wim | 2:76cb93b511f2 | 69 | #define FCR_RX_IRQ_16 (1 << 6) |
| wim | 2:76cb93b511f2 | 70 | #define FCR_RX_IRQ_8 (0 << 6) |
| wim | 2:76cb93b511f2 | 71 | //TX Level only accessible when EFR[4] is set |
| wim | 2:76cb93b511f2 | 72 | #define FCR_TX_IRQ_56 (3 << 4) |
| wim | 2:76cb93b511f2 | 73 | #define FCR_TX_IRQ_32 (2 << 4) |
| wim | 2:76cb93b511f2 | 74 | #define FCR_TX_IRQ_16 (1 << 4) |
| wim | 2:76cb93b511f2 | 75 | #define FCR_TX_IRQ_8 (0 << 4) |
| wim | 2:76cb93b511f2 | 76 | //#define FCR_RESERVED (1 << 3) |
| wim | 3:9783b6bde958 | 77 | #define FCR_TX_FIFO_RST (1 << 2) |
| wim | 3:9783b6bde958 | 78 | #define FCR_RX_FIFO_RST (1 << 1) |
| wim | 1:0440152c5387 | 79 | #define FCR_ENABLE_FIFO (1 << 0) |
| wim | 1:0440152c5387 | 80 | |
| wim | 2:76cb93b511f2 | 81 | //FIFO size |
| wim | 2:76cb93b511f2 | 82 | #define SC16IS750_FIFO_RX 64 |
| wim | 2:76cb93b511f2 | 83 | #define SC16IS750_FIFO_TX 64 |
| wim | 1:0440152c5387 | 84 | |
| wim | 1:0440152c5387 | 85 | |
| wim | 2:76cb93b511f2 | 86 | /** See section 8.4 of the datasheet for definitions |
| wim | 2:76cb93b511f2 | 87 | * of bits in the Line Control Register (LCR) |
| wim | 2:76cb93b511f2 | 88 | */ |
| wim | 2:76cb93b511f2 | 89 | #define LCR_BITS5 0x00 |
| wim | 2:76cb93b511f2 | 90 | #define LCR_BITS6 0x01 |
| wim | 2:76cb93b511f2 | 91 | #define LCR_BITS7 0x02 |
| wim | 2:76cb93b511f2 | 92 | #define LCR_BITS8 0x03 |
| wim | 1:0440152c5387 | 93 | |
| wim | 2:76cb93b511f2 | 94 | #define LCR_BITS1 0x00 |
| wim | 2:76cb93b511f2 | 95 | #define LCR_BITS2 0x04 |
| wim | 1:0440152c5387 | 96 | |
| wim | 2:76cb93b511f2 | 97 | #define LCR_NONE 0x00 |
| wim | 2:76cb93b511f2 | 98 | #define LCR_ODD 0x08 |
| wim | 2:76cb93b511f2 | 99 | #define LCR_EVEN 0x18 |
| wim | 2:76cb93b511f2 | 100 | #define LCR_FORCED1 0x28 |
| wim | 2:76cb93b511f2 | 101 | #define LCR_FORCED0 0x38 |
| wim | 2:76cb93b511f2 | 102 | |
| wim | 2:76cb93b511f2 | 103 | #define LCR_BRK_ENA 0x40 |
| wim | 2:76cb93b511f2 | 104 | #define LCR_BRK_DIS 0x00 |
| wim | 1:0440152c5387 | 105 | |
| wim | 2:76cb93b511f2 | 106 | #define LCR_ENABLE_DIV 0x80 |
| wim | 2:76cb93b511f2 | 107 | #define LCR_DISABLE_DIV 0x00 |
| wim | 2:76cb93b511f2 | 108 | |
| wim | 2:76cb93b511f2 | 109 | #define LCR_ENABLE_ENHANCED_FUNCTIONS (0xBF) |
| wim | 1:0440152c5387 | 110 | |
| wim | 1:0440152c5387 | 111 | |
| wim | 2:76cb93b511f2 | 112 | /** See section 8.5 of the datasheet for definitions |
| wim | 2:76cb93b511f2 | 113 | * of bits in the Line status register (LSR) |
| wim | 2:76cb93b511f2 | 114 | */ |
| wim | 3:9783b6bde958 | 115 | #define LSR_DR (0x01) /* Data ready in RX FIFO */ |
| wim | 1:0440152c5387 | 116 | #define LSR_OE (0x02) /* Overrun error */ |
| wim | 1:0440152c5387 | 117 | #define LSR_PE (0x04) /* Parity error */ |
| wim | 1:0440152c5387 | 118 | #define LSR_FE (0x08) /* Framing error */ |
| wim | 1:0440152c5387 | 119 | #define LSR_BI (0x10) /* Break interrupt */ |
| wim | 1:0440152c5387 | 120 | #define LSR_THRE (0x20) /* Transmitter holding register (FIFO empty) */ |
| wim | 1:0440152c5387 | 121 | #define LSR_TEMT (0x40) /* Transmitter empty (FIFO and TSR both empty) */ |
| wim | 2:76cb93b511f2 | 122 | #define LSR_FFE (0x80) /* At least one PE, FE or BI in FIFO */ |
| wim | 1:0440152c5387 | 123 | |
| wim | 2:76cb93b511f2 | 124 | |
| wim | 2:76cb93b511f2 | 125 | /** See section 8.6 of the datasheet for definitions |
| wim | 2:76cb93b511f2 | 126 | * of bits in the Modem control register (MCR) |
| wim | 2:76cb93b511f2 | 127 | */ |
| wim | 2:76cb93b511f2 | 128 | #define MCR_MDTR (1 << 0) /* Data Terminal Ready pin control. */ |
| wim | 2:76cb93b511f2 | 129 | #define MCR_MRTS (1 << 1) /* Request to Send pin control when not in Auto RTS mode.*/ |
| wim | 3:9783b6bde958 | 130 | //MCR[2] only accessible when EFR[4] is set |
| wim | 2:76cb93b511f2 | 131 | #define MCR_ENABLE_TCR_TLR (1 << 2) |
| wim | 2:76cb93b511f2 | 132 | #define MCR_ENABLE_LOOPBACK (1 << 4) |
| wim | 3:9783b6bde958 | 133 | //MCR[7:5] only accessible when EFR[4] is set |
| wim | 2:76cb93b511f2 | 134 | #define MCR_ENABLE_XON_ANY_CHAR (1 << 5) |
| wim | 2:76cb93b511f2 | 135 | #define MCR_ENABLE_IRDA (1 << 6) |
| wim | 2:76cb93b511f2 | 136 | #define MCR_PRESCALE_1 (0 << 7) |
| wim | 2:76cb93b511f2 | 137 | #define MCR_PRESCALE_4 (1 << 7) |
| wim | 2:76cb93b511f2 | 138 | |
| wim | 1:0440152c5387 | 139 | |
| wim | 2:76cb93b511f2 | 140 | /** See section 8.7 of the datasheet for definitions |
| wim | 2:76cb93b511f2 | 141 | * of bits in the Modem status register (MSR) |
| wim | 2:76cb93b511f2 | 142 | */ |
| wim | 3:9783b6bde958 | 143 | #define MSR_DCTS (1 << 0) /* Delta CTS - CTS Changed State */ |
| wim | 3:9783b6bde958 | 144 | #define MSR_DDSR (1 << 1) /* Delta DSR - DSR Changed State */ |
| wim | 3:9783b6bde958 | 145 | #define MSR_DDI (1 << 2) /* Delta DI - DI Changed State */ |
| wim | 3:9783b6bde958 | 146 | #define MSR_DCD (1 << 3) /* Delta CD - CD Changed State */ |
| wim | 3:9783b6bde958 | 147 | #define MSR_CTS (1 << 4) /* CTS State - Complement of NCTS pin */ |
| wim | 3:9783b6bde958 | 148 | //MSR[7:5] only accessible when GPIO[7:4] are set as modem pin |
| wim | 3:9783b6bde958 | 149 | #define MSR_DSR (1 << 5) /* DSR State - Complement of NDSR pin */ |
| wim | 3:9783b6bde958 | 150 | #define MSR_RI (1 << 6) /* RI State - Complement of NRI pin */ |
| wim | 3:9783b6bde958 | 151 | #define MSR_CD (1 << 7) /* CD State - Complement of NCD pin */ |
| wim | 2:76cb93b511f2 | 152 | |
| wim | 2:76cb93b511f2 | 153 | |
| wim | 2:76cb93b511f2 | 154 | /** See section 8.8 of the datasheet for definitions |
| wim | 2:76cb93b511f2 | 155 | * of bits in the Interrupt enable register (IER) |
| wim | 2:76cb93b511f2 | 156 | */ |
| wim | 3:9783b6bde958 | 157 | #define IER_ERHRI (0x01) /* Enable received data available interrupt */ |
| wim | 3:9783b6bde958 | 158 | #define IER_ETHRI (0x02) /* Enable transmitter holding register empty interrupt */ |
| wim | 2:76cb93b511f2 | 159 | #define IER_ELSI (0x04) /* Enable receiver line status interrupt */ |
| wim | 3:9783b6bde958 | 160 | #define IER_EMSI (0x08) /* Enable modem status interrupt */ |
| wim | 3:9783b6bde958 | 161 | //IER[7:5] only accessible when EFR[4] is set |
| wim | 2:76cb93b511f2 | 162 | #define IER_SLEEP (0x10) /* Enable sleep mode */ |
| wim | 3:9783b6bde958 | 163 | #define IER_XOFFI (0x20) /* Enable XOFF interrupt */ |
| wim | 3:9783b6bde958 | 164 | #define IER_RTSI (0x40) /* Enable RTS interrupt */ |
| wim | 3:9783b6bde958 | 165 | #define IER_CTSI (0x80) /* Enable CTS interrupt */ |
| wim | 1:0440152c5387 | 166 | |
| wim | 1:0440152c5387 | 167 | |
| wim | 2:76cb93b511f2 | 168 | /** See section 8.9 of the datasheet for definitions |
| wim | 2:76cb93b511f2 | 169 | * of bits in the Interrupt identification register (IIR) |
| wim | 3:9783b6bde958 | 170 | * Bit 0 is set to 0 if an IRQ is pending. |
| wim | 3:9783b6bde958 | 171 | * Bits 1..5 are used to identify the IRQ source. |
| wim | 2:76cb93b511f2 | 172 | */ |
| wim | 3:9783b6bde958 | 173 | #define IIR_IRQ_NOT_PENDING (0x01) /* IRQ Not Pending */ |
| wim | 3:9783b6bde958 | 174 | #define IIR_TX_EMPTY (0x02) /* THR Interrupt */ |
| wim | 3:9783b6bde958 | 175 | #define IIR_RX_DATA (0x04) /* RHR Interrupt */ |
| wim | 3:9783b6bde958 | 176 | #define IIR_RX_ERROR (0x06) /* Line Status Error Interrupt */ |
| wim | 3:9783b6bde958 | 177 | #define IIR_RX_TIMEOUT (0x0B) /* RX Timeout Interrupt */ |
| wim | 3:9783b6bde958 | 178 | #define IIR_RX_XOFF (0x10) /* RX XOff Interrupt */ |
| wim | 3:9783b6bde958 | 179 | #define IIR_DCTS_DRTS (0x20) /* Delta CTS or RTS Interrupt */ |
| wim | 3:9783b6bde958 | 180 | #define IIR_DIO (0x30) /* Delta GPIO pin Interrupt */ |
| wim | 3:9783b6bde958 | 181 | |
| wim | 2:76cb93b511f2 | 182 | #define IIR_BITS_USED (0x07) |
| wim | 2:76cb93b511f2 | 183 | |
| wim | 2:76cb93b511f2 | 184 | |
| wim | 2:76cb93b511f2 | 185 | /** See section 8.10 of the datasheet for definitions |
| wim | 2:76cb93b511f2 | 186 | * of bits in the Enhanced Features Register (EFR) |
| wim | 2:76cb93b511f2 | 187 | */ |
| wim | 2:76cb93b511f2 | 188 | #define EFR_ENABLE_CTS (1 << 7) |
| wim | 2:76cb93b511f2 | 189 | #define EFR_ENABLE_RTS (1 << 6) |
| wim | 2:76cb93b511f2 | 190 | #define EFR_ENABLE_XOFF2_CHAR_DETECT (1 << 5) |
| wim | 2:76cb93b511f2 | 191 | #define EFR_ENABLE_ENHANCED_FUNCTIONS (1 << 4) |
| wim | 2:76cb93b511f2 | 192 | // EFR[3:0] are used to define Software Flow Control mode |
| wim | 2:76cb93b511f2 | 193 | // See section 7.3 |
| wim | 2:76cb93b511f2 | 194 | #define EFR_DISABLE_TX_FLOW_CTRL (0x0 << 2) |
| wim | 2:76cb93b511f2 | 195 | #define EFR_TX_XON2_XOFF2 (0x1 << 2) |
| wim | 2:76cb93b511f2 | 196 | #define EFR_TX_XON1_XOFF1 (0x2 << 2) |
| wim | 2:76cb93b511f2 | 197 | #define EFR_TX_XON2_1_XOFF2_1 (0x3 << 2) |
| wim | 2:76cb93b511f2 | 198 | |
| wim | 2:76cb93b511f2 | 199 | #define EFR_DISABLE_RX_FLOW_CTRL (0x0 << 0) |
| wim | 2:76cb93b511f2 | 200 | #define EFR_RX_XON2_XOFF2 (0x1 << 0) |
| wim | 2:76cb93b511f2 | 201 | #define EFR_RX_XON1_XOFF1 (0x2 << 0) |
| wim | 2:76cb93b511f2 | 202 | #define EFR_RX_XON2_1_XOFF2_1 (0x3 << 0) |
| wim | 2:76cb93b511f2 | 203 | |
| wim | 2:76cb93b511f2 | 204 | #define EFR_TX_XON2_XOFF2_RX_FLOW (0x1 << 2) | (0x3 << 0) |
| wim | 2:76cb93b511f2 | 205 | #define EFR_TX_XON1_XOFF1_RX_FLOW (0x2 << 2) | (0x3 << 0) |
| wim | 2:76cb93b511f2 | 206 | #define EFR_TX_XON2_1_XOFF2_1_RX_FLOW (0x3 << 2) | (0x3 << 0) |
| wim | 1:0440152c5387 | 207 | |
| wim | 1:0440152c5387 | 208 | |
| wim | 1:0440152c5387 | 209 | |
| wim | 2:76cb93b511f2 | 210 | /** See section 8.12 of the datasheet for definitions |
| wim | 2:76cb93b511f2 | 211 | * of bits in the Transmission Control Register (TCR) |
| wim | 3:9783b6bde958 | 212 | * These levels control when RTS is asserted or de-asserted and auto RTS is enabled. Note that XON/XOFF is not supported in this lib. |
| wim | 3:9783b6bde958 | 213 | * Trigger level to halt transmission to the device : 0..15 (meaning 0-60 with a granularity of 4) |
| wim | 3:9783b6bde958 | 214 | * RTS is de-asserted when RX FIFO is above the set trigger level (i.e. buffer is getting full) |
| wim | 3:9783b6bde958 | 215 | * Trigger level to resume transmission to the device : 0..15 (meaning 0-60 with a granularity of 4) |
| wim | 3:9783b6bde958 | 216 | * RTS is asserted again when RX FIFO drops below the set trigger level (i.e. buffer has room again) |
| wim | 2:76cb93b511f2 | 217 | */ |
| wim | 2:76cb93b511f2 | 218 | #define TCR_HALT_DEFAULT (0x0E) |
| wim | 3:9783b6bde958 | 219 | #define TCR_RESUME_DEFAULT (0x08) |
| wim | 2:76cb93b511f2 | 220 | |
| wim | 3:9783b6bde958 | 221 | /** See section 8.12 of the datasheet for definitions |
| wim | 3:9783b6bde958 | 222 | * Note: The device will stop transmissions from the TX FIFO when CTS is de-asserted by external receiver and |
| wim | 3:9783b6bde958 | 223 | * auto CTS is enabled. Note that XON/XOFF is not supported in this lib. |
| wim | 3:9783b6bde958 | 224 | */ |
| wim | 2:76cb93b511f2 | 225 | |
| wim | 3:9783b6bde958 | 226 | |
| wim | 3:9783b6bde958 | 227 | /** See section 7.5 and 8.13 of the datasheet for definitions |
| wim | 3:9783b6bde958 | 228 | * of bits in the Trigger Level Register (TLR) control when an IRQ is generated. |
| wim | 2:76cb93b511f2 | 229 | * Trigger level for TX interrupt: 0..15 (meaning 0-60 with a granularity of 4) |
| wim | 3:9783b6bde958 | 230 | * IRQ when TX FIFO is above the set trigger level (i.e. buffer is getting full) |
| wim | 2:76cb93b511f2 | 231 | * Trigger level for RX interrupt: 0..15 (meaning 0-60 with a granularity of 4) |
| wim | 3:9783b6bde958 | 232 | * IRQ when RX FIFO is above the set trigger level (i.e. data is waiting to be read) |
| wim | 2:76cb93b511f2 | 233 | */ |
| wim | 2:76cb93b511f2 | 234 | #define TLR_TX_DEFAULT (0x0E) |
| wim | 2:76cb93b511f2 | 235 | #define TLR_RX_DEFAULT (0x04) |
| wim | 2:76cb93b511f2 | 236 | |
| wim | 2:76cb93b511f2 | 237 | |
| wim | 2:76cb93b511f2 | 238 | /** |
| wim | 3:9783b6bde958 | 239 | * See section 8.16, 8.17, 8.18 of the datasheet for definitions |
| wim | 3:9783b6bde958 | 240 | * of bits in the IO Direction (IODIR), IO State (IOSTATE) and IO Interrupt Enable register (IOINTENA) |
| wim | 3:9783b6bde958 | 241 | * |
| wim | 3:9783b6bde958 | 242 | * Basically a direct mapping of register bits to GPIO pin. |
| wim | 3:9783b6bde958 | 243 | */ |
| wim | 3:9783b6bde958 | 244 | |
| wim | 3:9783b6bde958 | 245 | |
| wim | 3:9783b6bde958 | 246 | /** |
| wim | 2:76cb93b511f2 | 247 | * See section 8.19 of the datasheet for definitions |
| wim | 2:76cb93b511f2 | 248 | * of bits in the IO Control register (IOC) |
| wim | 2:76cb93b511f2 | 249 | * |
| wim | 2:76cb93b511f2 | 250 | * Bit 0 is set to 0 to enable latch of IO inputs. |
| wim | 2:76cb93b511f2 | 251 | * Bit 1 is set to enable GPIO[7-4] as /RI, /CD, /DTR, /DST. |
| wim | 2:76cb93b511f2 | 252 | * Bit 2 is set to enable software reset. |
| wim | 2:76cb93b511f2 | 253 | */ |
| wim | 2:76cb93b511f2 | 254 | #define IOC_ENA_LATCH (0x01) |
| wim | 3:9783b6bde958 | 255 | #define IOC_ENA_MODEM (0x02) /* Set GPIO[7:4] pins to modem functions */ |
| wim | 3:9783b6bde958 | 256 | #define IOC_SW_RST (0x04) |
| wim | 3:9783b6bde958 | 257 | |
| wim | 2:76cb93b511f2 | 258 | |
| wim | 3:9783b6bde958 | 259 | /** |
| wim | 3:9783b6bde958 | 260 | * See section 8.20 of the datasheet for definitions |
| wim | 3:9783b6bde958 | 261 | * of bits in the Extra Features Control register (EFCR) |
| wim | 3:9783b6bde958 | 262 | * |
| wim | 3:9783b6bde958 | 263 | */ |
| wim | 3:9783b6bde958 | 264 | #define EFCR_ENA_RS485 (0x01) |
| wim | 3:9783b6bde958 | 265 | #define EFCR_DIS_RX (0x02) |
| wim | 3:9783b6bde958 | 266 | #define EFCR_DIS_TX (0x04) |
| wim | 3:9783b6bde958 | 267 | #define EFCR_ENA_TX_RTS (0x10) |
| wim | 3:9783b6bde958 | 268 | #define EFCR_INV_RTS_RS485 (0x20) |
| wim | 3:9783b6bde958 | 269 | #define EFCR_ENA_IRDA (0x80) |
| wim | 2:76cb93b511f2 | 270 | |
| wim | 0:d64854a60f95 | 271 | // See Chapter 11 of datasheet |
| wim | 2:76cb93b511f2 | 272 | #define SPI_READ_MODE_FLAG (0x80) |
| wim | 0:d64854a60f95 | 273 | |
| wim | 0:d64854a60f95 | 274 | |
| wim | 4:12446ee9f9c8 | 275 | /** Abstract class SC16IS750 for a bridge between either SPI or I2C and a Serial port |
| wim | 0:d64854a60f95 | 276 | * |
| wim | 0:d64854a60f95 | 277 | * Supports both SPI and I2C interfaces through derived classes |
| wim | 0:d64854a60f95 | 278 | * |
| wim | 0:d64854a60f95 | 279 | * @code |
| wim | 0:d64854a60f95 | 280 | * |
| wim | 0:d64854a60f95 | 281 | * @endcode |
| wim | 0:d64854a60f95 | 282 | */ |
| wim | 3:9783b6bde958 | 283 | //class SC16IS750 { |
| wim | 3:9783b6bde958 | 284 | //class SC16IS750 : public SerialBase, public Stream { // Wrong, Serialbase can not be constructed for NC,NC |
| wim | 3:9783b6bde958 | 285 | class SC16IS750 : public Stream { |
| wim | 0:d64854a60f95 | 286 | public: |
| wim | 0:d64854a60f95 | 287 | |
| wim | 0:d64854a60f95 | 288 | // SC16IS750 Register definitions (shifted to align) |
| wim | 0:d64854a60f95 | 289 | enum RegisterName { |
| wim | 1:0440152c5387 | 290 | /* |
| wim | 1:0440152c5387 | 291 | * 16750 addresses. Registers accessed when LCR[7] = 0. |
| wim | 1:0440152c5387 | 292 | */ |
| wim | 1:0440152c5387 | 293 | RHR = 0x00 << 3, /* Rx buffer register - Read access */ |
| wim | 1:0440152c5387 | 294 | THR = 0x00 << 3, /* Tx holding register - Write access */ |
| wim | 1:0440152c5387 | 295 | IER = 0x01 << 3, /* Interrupt enable reg - RD/WR access */ |
| wim | 1:0440152c5387 | 296 | |
| wim | 1:0440152c5387 | 297 | /* |
| wim | 1:0440152c5387 | 298 | * 16750 addresses. Registers accessed when LCR[7] = 1. |
| wim | 1:0440152c5387 | 299 | */ |
| wim | 1:0440152c5387 | 300 | DLL = 0x00 << 3, /* Divisor latch (LSB) - RD/WR access */ |
| wim | 1:0440152c5387 | 301 | DLH = 0x01 << 3, /* Divisor latch (MSB) - RD/WR access */ |
| wim | 1:0440152c5387 | 302 | |
| wim | 1:0440152c5387 | 303 | /* |
| wim | 1:0440152c5387 | 304 | * 16750 addresses. IIR/FCR is accessed when LCR[7:0] <> 0xBF. |
| wim | 1:0440152c5387 | 305 | * Bit 5 of the FCR register is accessed when LCR[7] = 1. |
| wim | 1:0440152c5387 | 306 | */ |
| wim | 1:0440152c5387 | 307 | IIR = 0x02 << 3, /* Interrupt id. register - Read only */ |
| wim | 1:0440152c5387 | 308 | FCR = 0x02 << 3, /* FIFO control register - Write only */ |
| wim | 1:0440152c5387 | 309 | /* |
| wim | 1:0440152c5387 | 310 | * 16750 addresses. EFR is accessed when LCR[7:0] = 0xBF. |
| wim | 1:0440152c5387 | 311 | */ |
| wim | 1:0440152c5387 | 312 | EFR = 0x02 << 3, /* Enhanced features reg - RD/WR access */ |
| wim | 1:0440152c5387 | 313 | |
| wim | 1:0440152c5387 | 314 | /* |
| wim | 1:0440152c5387 | 315 | * 16750 addresses. |
| wim | 1:0440152c5387 | 316 | */ |
| wim | 1:0440152c5387 | 317 | LCR = 0x03 << 3, /* Line control register - RD/WR access */ |
| wim | 1:0440152c5387 | 318 | /* |
| wim | 1:0440152c5387 | 319 | * 16750 addresses. MCR/LSR is accessed when LCR[7:0] <> 0xBF. |
| wim | 1:0440152c5387 | 320 | * Bit 7 of the MCR register is accessed when EFR[4] = 1. |
| wim | 1:0440152c5387 | 321 | */ |
| wim | 1:0440152c5387 | 322 | MCR = 0x04 << 3, /* Modem control register - RD/WR access */ |
| wim | 1:0440152c5387 | 323 | LSR = 0x05 << 3, /* Line status register - Read only */ |
| wim | 1:0440152c5387 | 324 | |
| wim | 1:0440152c5387 | 325 | /* |
| wim | 1:0440152c5387 | 326 | * 16750 addresses. MSR/SPR is accessed when LCR[7:0] <> 0xBF. |
| wim | 1:0440152c5387 | 327 | * MSR, SPR register is accessed when EFR[1]=0 and MCR[2]=0. |
| wim | 1:0440152c5387 | 328 | */ |
| wim | 1:0440152c5387 | 329 | MSR = 0x06 << 3, /* Modem status register - Read only */ |
| wim | 1:0440152c5387 | 330 | SPR = 0x07 << 3, /* Scratchpad register - RD/WR access */ |
| wim | 1:0440152c5387 | 331 | /* |
| wim | 1:0440152c5387 | 332 | * 16750 addresses. TCR/TLR is accessed when LCR[7:0] <> 0xBF. |
| wim | 1:0440152c5387 | 333 | * TCR, TLR register is accessed when EFR[1]=1 and MCR[2]=1. |
| wim | 1:0440152c5387 | 334 | */ |
| wim | 1:0440152c5387 | 335 | TCR = 0x06 << 3, /* Transmission control register - RD/WR access */ |
| wim | 1:0440152c5387 | 336 | TLR = 0x07 << 3, /* Trigger level register - RD/WR access */ |
| wim | 1:0440152c5387 | 337 | |
| wim | 1:0440152c5387 | 338 | /* |
| wim | 1:0440152c5387 | 339 | * 16750 addresses. XON, XOFF is accessed when LCR[7:0] = 0xBF. |
| wim | 1:0440152c5387 | 340 | */ |
| wim | 1:0440152c5387 | 341 | XON1 = 0x04 << 3, /* XON1 register - RD/WR access */ |
| wim | 1:0440152c5387 | 342 | XON2 = 0x05 << 3, /* XON2 register - RD/WR access */ |
| wim | 1:0440152c5387 | 343 | XOFF1 = 0x06 << 3, /* XOFF1 register - RD/WR access */ |
| wim | 1:0440152c5387 | 344 | XOFF2 = 0x07 << 3, /* XOFF2 register - RD/WR access */ |
| wim | 1:0440152c5387 | 345 | |
| wim | 1:0440152c5387 | 346 | /* |
| wim | 1:0440152c5387 | 347 | * 16750 addresses. |
| wim | 1:0440152c5387 | 348 | */ |
| wim | 1:0440152c5387 | 349 | TXLVL = 0x08 << 3, /* TX FIFO Level register - Read only */ |
| wim | 1:0440152c5387 | 350 | RXLVL = 0x09 << 3, /* RX FIFO Level register - Read only */ |
| wim | 1:0440152c5387 | 351 | IODIR = 0x0A << 3, /* IO Pin Direction reg - RD/WR access */ |
| wim | 1:0440152c5387 | 352 | IOSTATE = 0x0B << 3, /* IO Pin State reg - Read only */ |
| wim | 1:0440152c5387 | 353 | IOINTENA = 0x0C << 3, /* IO Interrupt Enable - RD/WR access */ |
| wim | 1:0440152c5387 | 354 | // reserved = 0x0D << 3, |
| wim | 1:0440152c5387 | 355 | IOCTRL = 0x0E << 3, /* IO Control register - RD/WR access */ |
| wim | 1:0440152c5387 | 356 | EFCR = 0x0F << 3, /* Extra features reg - RD/WR access */ |
| wim | 1:0440152c5387 | 357 | |
| wim | 0:d64854a60f95 | 358 | } ; |
| wim | 0:d64854a60f95 | 359 | |
| wim | 0:d64854a60f95 | 360 | |
| wim | 1:0440152c5387 | 361 | // This enum used to be part of SerialBase class (access via SerialBase.h). |
| wim | 1:0440152c5387 | 362 | // It seems not be supported anymore. The enums for Parity have moved to Serial now.. |
| wim | 1:0440152c5387 | 363 | enum Flow { |
| wim | 1:0440152c5387 | 364 | Disabled = 0, |
| wim | 1:0440152c5387 | 365 | RTS, |
| wim | 1:0440152c5387 | 366 | CTS, |
| wim | 1:0440152c5387 | 367 | RTSCTS |
| wim | 1:0440152c5387 | 368 | }; |
| wim | 1:0440152c5387 | 369 | |
| wim | 4:12446ee9f9c8 | 370 | // SC16IS752 Channel definitions (shifted to align) |
| wim | 4:12446ee9f9c8 | 371 | enum ChannelName { |
| wim | 4:12446ee9f9c8 | 372 | Channel_A = 0x00 << 1, |
| wim | 4:12446ee9f9c8 | 373 | Channel_B = 0x01 << 1 |
| wim | 4:12446ee9f9c8 | 374 | }; |
| wim | 1:0440152c5387 | 375 | |
| wim | 0:d64854a60f95 | 376 | // SC16IS750 configuration register values |
| wim | 1:0440152c5387 | 377 | // Several configuration registers are write-only. Need to save values to allow restoring. |
| wim | 0:d64854a60f95 | 378 | struct SC16IS750_cfg { |
| wim | 0:d64854a60f95 | 379 | char baudrate; |
| wim | 0:d64854a60f95 | 380 | char dataformat; |
| wim | 0:d64854a60f95 | 381 | char flowctrl; |
| wim | 1:0440152c5387 | 382 | char fifoformat; |
| wim | 1:0440152c5387 | 383 | bool fifoenable; |
| wim | 0:d64854a60f95 | 384 | }; |
| wim | 0:d64854a60f95 | 385 | |
| wim | 0:d64854a60f95 | 386 | |
| wim | 0:d64854a60f95 | 387 | /** Determine if there is a character available to read. |
| wim | 2:76cb93b511f2 | 388 | * This is data that's already arrived and stored in the receive |
| wim | 2:76cb93b511f2 | 389 | * buffer (which holds 64 chars). |
| wim | 2:76cb93b511f2 | 390 | * |
| wim | 0:d64854a60f95 | 391 | * @return 1 if there is a character available to read, 0 otherwise |
| wim | 0:d64854a60f95 | 392 | */ |
| wim | 1:0440152c5387 | 393 | int readable(); |
| wim | 0:d64854a60f95 | 394 | |
| wim | 2:76cb93b511f2 | 395 | /** Determine how many characters are available to read. |
| wim | 2:76cb93b511f2 | 396 | * This is data that's already arrived and stored in the receive |
| wim | 2:76cb93b511f2 | 397 | * buffer (which holds 64 chars). |
| wim | 2:76cb93b511f2 | 398 | * |
| wim | 0:d64854a60f95 | 399 | * @return int Characters available to read |
| wim | 2:76cb93b511f2 | 400 | */ |
| wim | 1:0440152c5387 | 401 | int readableCount(); |
| wim | 0:d64854a60f95 | 402 | |
| wim | 0:d64854a60f95 | 403 | /** Determine if there is space available to write a character. |
| wim | 0:d64854a60f95 | 404 | * @return 1 if there is a space for a character to write, 0 otherwise |
| wim | 0:d64854a60f95 | 405 | */ |
| wim | 1:0440152c5387 | 406 | int writable(); |
| wim | 0:d64854a60f95 | 407 | |
| wim | 2:76cb93b511f2 | 408 | |
| wim | 1:0440152c5387 | 409 | /** Determine how much space available for writing characters. |
| wim | 2:76cb93b511f2 | 410 | * This considers data that's already stored in the transmit |
| wim | 2:76cb93b511f2 | 411 | * buffer (which holds 64 chars). |
| wim | 2:76cb93b511f2 | 412 | * |
| wim | 1:0440152c5387 | 413 | * @return int character space available to write |
| wim | 2:76cb93b511f2 | 414 | */ |
| wim | 1:0440152c5387 | 415 | int writableCount(); |
| wim | 1:0440152c5387 | 416 | |
| wim | 1:0440152c5387 | 417 | /** |
| wim | 1:0440152c5387 | 418 | * Read char from UART Bridge. |
| wim | 1:0440152c5387 | 419 | * Acts in the same manner as 'Serial.read()'. |
| wim | 1:0440152c5387 | 420 | * @param none |
| wim | 1:0440152c5387 | 421 | * @return char read or -1 if no data available. |
| wim | 1:0440152c5387 | 422 | */ |
| wim | 1:0440152c5387 | 423 | int getc(); |
| wim | 1:0440152c5387 | 424 | |
| wim | 1:0440152c5387 | 425 | /** |
| wim | 1:0440152c5387 | 426 | * Write char to UART Bridge. Blocking when no free space in FIFO |
| wim | 1:0440152c5387 | 427 | * @param value char to be written |
| wim | 1:0440152c5387 | 428 | * @return value written |
| wim | 1:0440152c5387 | 429 | */ |
| wim | 4:12446ee9f9c8 | 430 | int putc(int c); |
| wim | 4:12446ee9f9c8 | 431 | |
| wim | 4:12446ee9f9c8 | 432 | |
| wim | 4:12446ee9f9c8 | 433 | #if DOXYGEN_ONLY |
| wim | 4:12446ee9f9c8 | 434 | /** Write a formatted string to the UART Bridge. Blocking when no free space in FIFO |
| wim | 4:12446ee9f9c8 | 435 | * |
| wim | 4:12446ee9f9c8 | 436 | * @param format A printf-style format string, followed by the |
| wim | 4:12446ee9f9c8 | 437 | * variables to use in formatting the string. |
| wim | 4:12446ee9f9c8 | 438 | */ |
| wim | 4:12446ee9f9c8 | 439 | int printf(const char* format, ...); |
| wim | 4:12446ee9f9c8 | 440 | #endif |
| wim | 1:0440152c5387 | 441 | |
| wim | 2:76cb93b511f2 | 442 | |
| wim | 2:76cb93b511f2 | 443 | /** |
| wim | 2:76cb93b511f2 | 444 | * Write char string to UART Bridge. Blocking when no free space in FIFO |
| wim | 2:76cb93b511f2 | 445 | * @param *str char string to be written |
| wim | 2:76cb93b511f2 | 446 | * @return none |
| wim | 2:76cb93b511f2 | 447 | */ |
| wim | 3:9783b6bde958 | 448 | void writeString(const char *str); |
| wim | 3:9783b6bde958 | 449 | |
| wim | 3:9783b6bde958 | 450 | |
| wim | 3:9783b6bde958 | 451 | /** |
| wim | 3:9783b6bde958 | 452 | * Write byte array to UART Bridge. Blocking when no free space in FIFO |
| wim | 3:9783b6bde958 | 453 | * @param *data byte array to be written |
| wim | 3:9783b6bde958 | 454 | * @param len number of bytes to write |
| wim | 3:9783b6bde958 | 455 | * @return none |
| wim | 3:9783b6bde958 | 456 | */ |
| wim | 3:9783b6bde958 | 457 | void writeBytes(const char *data, int len); |
| wim | 0:d64854a60f95 | 458 | |
| wim | 0:d64854a60f95 | 459 | /** Set baudrate of the serial port. |
| wim | 0:d64854a60f95 | 460 | * @param baud integer baudrate (4800, 9600 etc) |
| wim | 0:d64854a60f95 | 461 | * @return none |
| wim | 0:d64854a60f95 | 462 | */ |
| wim | 2:76cb93b511f2 | 463 | void baud(int baudrate = SC16IS750_DEFAULT_BAUDRATE); |
| wim | 0:d64854a60f95 | 464 | |
| wim | 0:d64854a60f95 | 465 | /** Set the transmission format used by the serial port. |
| wim | 0:d64854a60f95 | 466 | * @param bits The number of bits in a word (5-8; default = 8) |
| wim | 0:d64854a60f95 | 467 | * @param parity The parity used (Serial::None, Serial::Odd, Serial::Even, Serial::Forced1, Serial::Forced0; default = Serial::None) |
| wim | 0:d64854a60f95 | 468 | * @param stop_bits The number of stop bits (1 or 2; default = 1) |
| wim | 2:76cb93b511f2 | 469 | * @return none |
| wim | 0:d64854a60f95 | 470 | */ |
| wim | 1:0440152c5387 | 471 | void format(int bits=8, Serial::Parity parity=Serial::None, int stop_bits=1); |
| wim | 2:76cb93b511f2 | 472 | |
| wim | 1:0440152c5387 | 473 | #if(0) |
| wim | 1:0440152c5387 | 474 | /** Attach a function to call whenever a serial interrupt is generated |
| wim | 1:0440152c5387 | 475 | * |
| wim | 1:0440152c5387 | 476 | * @param fptr A pointer to a void function, or 0 to set as none |
| wim | 1:0440152c5387 | 477 | * @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty) |
| wim | 1:0440152c5387 | 478 | */ |
| wim | 1:0440152c5387 | 479 | void attach(void (*fptr)(void), IrqType type=RxIrq); |
| wim | 1:0440152c5387 | 480 | |
| wim | 1:0440152c5387 | 481 | /** Attach a member function to call whenever a serial interrupt is generated |
| wim | 1:0440152c5387 | 482 | * |
| wim | 1:0440152c5387 | 483 | * @param tptr pointer to the object to call the member function on |
| wim | 1:0440152c5387 | 484 | * @param mptr pointer to the member function to be called |
| wim | 1:0440152c5387 | 485 | * @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty) |
| wim | 2:76cb93b511f2 | 486 | * @return none |
| wim | 1:0440152c5387 | 487 | */ |
| wim | 1:0440152c5387 | 488 | template<typename T> |
| wim | 1:0440152c5387 | 489 | void attach(T* tptr, void (T::*mptr)(void), IrqType type=RxIrq) { |
| wim | 1:0440152c5387 | 490 | if((mptr != NULL) && (tptr != NULL)) { |
| wim | 1:0440152c5387 | 491 | _irq[type].attach(tptr, mptr); |
| wim | 1:0440152c5387 | 492 | serial_irq_set(&_serial, (SerialIrq)type, 1); |
| wim | 1:0440152c5387 | 493 | } |
| wim | 1:0440152c5387 | 494 | } |
| wim | 1:0440152c5387 | 495 | #endif |
| wim | 1:0440152c5387 | 496 | |
| wim | 1:0440152c5387 | 497 | /** Generate a break condition on the serial line |
| wim | 2:76cb93b511f2 | 498 | * @param none |
| wim | 2:76cb93b511f2 | 499 | * @return none |
| wim | 1:0440152c5387 | 500 | */ |
| wim | 1:0440152c5387 | 501 | void send_break(); |
| wim | 0:d64854a60f95 | 502 | |
| wim | 1:0440152c5387 | 503 | |
| wim | 1:0440152c5387 | 504 | /** Set a break condition on the serial line |
| wim | 1:0440152c5387 | 505 | * @param enable break condition |
| wim | 2:76cb93b511f2 | 506 | * @return none |
| wim | 1:0440152c5387 | 507 | */ |
| wim | 1:0440152c5387 | 508 | void set_break(bool enable=false); |
| wim | 1:0440152c5387 | 509 | |
| wim | 1:0440152c5387 | 510 | |
| wim | 1:0440152c5387 | 511 | /** Set the flow control type on the serial port |
| wim | 1:0440152c5387 | 512 | * Added for compatibility with Serial Class. |
| wim | 2:76cb93b511f2 | 513 | * SC16IS750 supports only Flow, Pins can not be selected. |
| wim | 3:9783b6bde958 | 514 | * This method sets hardware flow control levels. SC16IS750 supports XON/XOFF, but this is not implemented. |
| wim | 1:0440152c5387 | 515 | * |
| wim | 1:0440152c5387 | 516 | * @param type the flow control type (Disabled, RTS, CTS, RTSCTS) |
| wim | 1:0440152c5387 | 517 | * @param flow1 the first flow control pin (RTS for RTS or RTSCTS, CTS for CTS) |
| wim | 1:0440152c5387 | 518 | * @param flow2 the second flow control pin (CTS for RTSCTS) |
| wim | 2:76cb93b511f2 | 519 | * @return none |
| wim | 1:0440152c5387 | 520 | */ |
| wim | 1:0440152c5387 | 521 | void set_flow_control(Flow type=Disabled, PinName flow1=NC, PinName flow2=NC); |
| wim | 2:76cb93b511f2 | 522 | |
| wim | 2:76cb93b511f2 | 523 | |
| wim | 2:76cb93b511f2 | 524 | /** Set the RX FIFO flow control levels |
| wim | 3:9783b6bde958 | 525 | * This method sets hardware flow control levels. SC16IS750 supports XON/XOFF, but this is not implemented. |
| wim | 2:76cb93b511f2 | 526 | * Should be called BEFORE Auto RTS is enabled. |
| wim | 2:76cb93b511f2 | 527 | * |
| wim | 2:76cb93b511f2 | 528 | * @param resume trigger level to resume transmission (0..15, meaning 0-60 with a granularity of 4) |
| wim | 2:76cb93b511f2 | 529 | * @param halt trigger level to resume transmission (0..15, meaning 0-60 with granularity of 4) |
| wim | 2:76cb93b511f2 | 530 | * @return none |
| wim | 2:76cb93b511f2 | 531 | */ |
| wim | 2:76cb93b511f2 | 532 | void set_flow_triggers(int resume = TCR_RESUME_DEFAULT, int halt = TCR_HALT_DEFAULT); |
| wim | 2:76cb93b511f2 | 533 | |
| wim | 2:76cb93b511f2 | 534 | |
| wim | 2:76cb93b511f2 | 535 | /** Set the Modem Control register |
| wim | 2:76cb93b511f2 | 536 | * This method sets prescaler, enables TCR and TLR |
| wim | 2:76cb93b511f2 | 537 | * |
| wim | 2:76cb93b511f2 | 538 | * @param none |
| wim | 2:76cb93b511f2 | 539 | * @return none |
| wim | 2:76cb93b511f2 | 540 | */ |
| wim | 2:76cb93b511f2 | 541 | void set_modem_control(); |
| wim | 2:76cb93b511f2 | 542 | |
| wim | 1:0440152c5387 | 543 | |
| wim | 0:d64854a60f95 | 544 | /** |
| wim | 0:d64854a60f95 | 545 | * Check that UART is connected and operational. |
| wim | 0:d64854a60f95 | 546 | * @param none |
| wim | 0:d64854a60f95 | 547 | * @return bool true when connected, false otherwise |
| wim | 0:d64854a60f95 | 548 | */ |
| wim | 0:d64854a60f95 | 549 | bool connected(); |
| wim | 0:d64854a60f95 | 550 | |
| wim | 0:d64854a60f95 | 551 | |
| wim | 2:76cb93b511f2 | 552 | |
| wim | 3:9783b6bde958 | 553 | /** FIFO control, sets TX and RX IRQ trigger levels and enables FIFO and save in _config |
| wim | 2:76cb93b511f2 | 554 | * Note FCR[5:4] (=TX_IRQ_LVL) only accessible when EFR[4] is set (enhanced functions enable) |
| wim | 2:76cb93b511f2 | 555 | * Note TLR only accessible when EFR[4] is set (enhanced functions enable) and MCR[2] is set |
| wim | 2:76cb93b511f2 | 556 | * @param none |
| wim | 2:76cb93b511f2 | 557 | * @return none |
| wim | 2:76cb93b511f2 | 558 | */ |
| wim | 2:76cb93b511f2 | 559 | void set_fifo_control(); |
| wim | 2:76cb93b511f2 | 560 | |
| wim | 1:0440152c5387 | 561 | |
| wim | 1:0440152c5387 | 562 | /** Flush the UART FIFOs while maintaining current FIFO mode. |
| wim | 1:0440152c5387 | 563 | * @param none |
| wim | 1:0440152c5387 | 564 | * @return none |
| wim | 1:0440152c5387 | 565 | */ |
| wim | 1:0440152c5387 | 566 | void flush(); |
| wim | 0:d64854a60f95 | 567 | |
| wim | 1:0440152c5387 | 568 | |
| wim | 1:0440152c5387 | 569 | /** Set direction of I/O port pins. |
| wim | 1:0440152c5387 | 570 | * This method is specific to the SPI-I2C UART and not found on the 16750 |
| wim | 1:0440152c5387 | 571 | * @param bits Bitpattern for I/O (1=output, 0=input) |
| wim | 1:0440152c5387 | 572 | * @return none |
| wim | 1:0440152c5387 | 573 | */ |
| wim | 1:0440152c5387 | 574 | void ioSetDirection(unsigned char bits); |
| wim | 0:d64854a60f95 | 575 | |
| wim | 1:0440152c5387 | 576 | /** Set bits of I/O port pins. |
| wim | 1:0440152c5387 | 577 | * This method is specific to the SPI-I2C UART and not found on the 16750 |
| wim | 1:0440152c5387 | 578 | * @param bits Bitpattern for I/O (1= set output bit, 0 = clear output bit) |
| wim | 1:0440152c5387 | 579 | * @return none |
| wim | 1:0440152c5387 | 580 | */ |
| wim | 1:0440152c5387 | 581 | void ioSetState(unsigned char bits); |
| wim | 1:0440152c5387 | 582 | |
| wim | 1:0440152c5387 | 583 | /** Get bits of I/O port pins. |
| wim | 1:0440152c5387 | 584 | * This method is specific to the SPI-I2C UART and not found on the 16750 |
| wim | 1:0440152c5387 | 585 | * @param none |
| wim | 1:0440152c5387 | 586 | * @return bits Bitpattern for I/O (1= bit set, 0 = bit cleared) |
| wim | 1:0440152c5387 | 587 | */ |
| wim | 1:0440152c5387 | 588 | unsigned char ioGetState(); |
| wim | 1:0440152c5387 | 589 | |
| wim | 1:0440152c5387 | 590 | |
| wim | 1:0440152c5387 | 591 | /** Software Reset SC16IS750 device. |
| wim | 1:0440152c5387 | 592 | * This method is specific to the SPI-I2C UART and not found on the 16750 |
| wim | 1:0440152c5387 | 593 | * @param none |
| wim | 1:0440152c5387 | 594 | * @return none |
| wim | 1:0440152c5387 | 595 | */ |
| wim | 1:0440152c5387 | 596 | void swReset(); |
| wim | 1:0440152c5387 | 597 | |
| wim | 0:d64854a60f95 | 598 | |
| wim | 4:12446ee9f9c8 | 599 | /** Hardware Reset SC16IS750 device. |
| wim | 4:12446ee9f9c8 | 600 | * Pure virtual, must be declared in derived class. |
| wim | 4:12446ee9f9c8 | 601 | * This method is only functional when the Reset pin has been declared and is also connected |
| wim | 4:12446ee9f9c8 | 602 | * @param none |
| wim | 4:12446ee9f9c8 | 603 | * @return none |
| wim | 4:12446ee9f9c8 | 604 | */ |
| wim | 4:12446ee9f9c8 | 605 | virtual void hwReset() =0; |
| wim | 4:12446ee9f9c8 | 606 | |
| wim | 0:d64854a60f95 | 607 | /** Write value to internal register. |
| wim | 0:d64854a60f95 | 608 | * Pure virtual, must be declared in derived class. |
| wim | 1:0440152c5387 | 609 | * @param registerAddress The address of the Register (enum RegisterName) |
| wim | 0:d64854a60f95 | 610 | * @param data The 8bit value to write |
| wim | 0:d64854a60f95 | 611 | * @return none |
| wim | 0:d64854a60f95 | 612 | */ |
| wim | 1:0440152c5387 | 613 | virtual void writeRegister (RegisterName register_address, char data ) =0; |
| wim | 0:d64854a60f95 | 614 | |
| wim | 0:d64854a60f95 | 615 | /** Read value from internal register. |
| wim | 0:d64854a60f95 | 616 | * Pure virtual, must be declared in derived class. |
| wim | 1:0440152c5387 | 617 | * @param registerAddress The address of the Register (enum RegisterName) |
| wim | 0:d64854a60f95 | 618 | * @return char The 8bit value read from the register |
| wim | 0:d64854a60f95 | 619 | */ |
| wim | 1:0440152c5387 | 620 | virtual char readRegister (RegisterName register_address ) =0; |
| wim | 1:0440152c5387 | 621 | |
| wim | 3:9783b6bde958 | 622 | /** Write multiple datavalues to Transmitregister. |
| wim | 3:9783b6bde958 | 623 | * More Efficient implementation than writing individual bytes |
| wim | 3:9783b6bde958 | 624 | * Pure virtual, must be declared in derived class. |
| wim | 3:9783b6bde958 | 625 | * @param char* databytes The pointer to the block of data |
| wim | 3:9783b6bde958 | 626 | * @param len The number of bytes to write |
| wim | 3:9783b6bde958 | 627 | * @return none |
| wim | 3:9783b6bde958 | 628 | */ |
| wim | 3:9783b6bde958 | 629 | virtual void writeDataBlock (const char *data, int len ) =0; |
| wim | 3:9783b6bde958 | 630 | |
| wim | 0:d64854a60f95 | 631 | |
| wim | 1:0440152c5387 | 632 | /** Initialise internal registers |
| wim | 1:0440152c5387 | 633 | * Should be in protection section. Public for testing purposes |
| wim | 1:0440152c5387 | 634 | * If initialisation fails this method does not return. |
| wim | 1:0440152c5387 | 635 | * @param none |
| wim | 1:0440152c5387 | 636 | * @return none |
| wim | 1:0440152c5387 | 637 | */ |
| wim | 1:0440152c5387 | 638 | void _init(); |
| wim | 1:0440152c5387 | 639 | |
| wim | 0:d64854a60f95 | 640 | protected: |
| wim | 0:d64854a60f95 | 641 | //protected is accessible to derived classes, but not to external users |
| wim | 0:d64854a60f95 | 642 | |
| wim | 2:76cb93b511f2 | 643 | |
| wim | 2:76cb93b511f2 | 644 | /** Constructor is protected for this abstract Class |
| wim | 1:0440152c5387 | 645 | * |
| wim | 1:0440152c5387 | 646 | */ |
| wim | 1:0440152c5387 | 647 | SC16IS750(); |
| wim | 1:0440152c5387 | 648 | |
| wim | 3:9783b6bde958 | 649 | /** Needed to implement Stream |
| wim | 3:9783b6bde958 | 650 | * |
| wim | 3:9783b6bde958 | 651 | * Read char from UART Bridge. |
| wim | 3:9783b6bde958 | 652 | * Acts in the same manner as 'Serial.read()'. |
| wim | 3:9783b6bde958 | 653 | * @param none |
| wim | 3:9783b6bde958 | 654 | * @return char read or -1 if no data available. |
| wim | 3:9783b6bde958 | 655 | */ |
| wim | 3:9783b6bde958 | 656 | virtual int _getc() { |
| wim | 3:9783b6bde958 | 657 | return getc(); |
| wim | 3:9783b6bde958 | 658 | } |
| wim | 3:9783b6bde958 | 659 | |
| wim | 3:9783b6bde958 | 660 | |
| wim | 3:9783b6bde958 | 661 | /** Needed to implement Stream |
| wim | 3:9783b6bde958 | 662 | * |
| wim | 3:9783b6bde958 | 663 | * Write char to UART Bridge. Blocking when no free space in FIFO |
| wim | 3:9783b6bde958 | 664 | * @param value char to be written |
| wim | 3:9783b6bde958 | 665 | * @return value written |
| wim | 3:9783b6bde958 | 666 | */ |
| wim | 3:9783b6bde958 | 667 | virtual int _putc(int c) { |
| wim | 3:9783b6bde958 | 668 | return putc(c); |
| wim | 3:9783b6bde958 | 669 | } |
| wim | 3:9783b6bde958 | 670 | |
| wim | 3:9783b6bde958 | 671 | /** Needed to implement Stream |
| wim | 3:9783b6bde958 | 672 | * |
| wim | 3:9783b6bde958 | 673 | */ |
| wim | 3:9783b6bde958 | 674 | virtual int peek() {return 0;}; |
| wim | 4:12446ee9f9c8 | 675 | |
| wim | 3:9783b6bde958 | 676 | |
| wim | 2:76cb93b511f2 | 677 | // Save config settings |
| wim | 0:d64854a60f95 | 678 | SC16IS750_cfg _config; |
| wim | 0:d64854a60f95 | 679 | |
| wim | 0:d64854a60f95 | 680 | private: |
| wim | 0:d64854a60f95 | 681 | //private is not accessible to derived classes, nor external users |
| wim | 1:0440152c5387 | 682 | |
| wim | 0:d64854a60f95 | 683 | }; |
| wim | 0:d64854a60f95 | 684 | |
| wim | 0:d64854a60f95 | 685 | |
| wim | 0:d64854a60f95 | 686 | |
| wim | 4:12446ee9f9c8 | 687 | /** Class SC16IS750_SPI for a bridge between SPI and a Serial port |
| wim | 0:d64854a60f95 | 688 | * |
| wim | 0:d64854a60f95 | 689 | * @code |
| wim | 0:d64854a60f95 | 690 | * #include "mbed.h" |
| wim | 0:d64854a60f95 | 691 | * #include "SC16IS750.h" |
| wim | 0:d64854a60f95 | 692 | * |
| wim | 0:d64854a60f95 | 693 | * SPI spi(PTD2, PTD3, PTD1); //MOSI, MISO, SCK |
| wim | 0:d64854a60f95 | 694 | * SC16IS750_SPI serial_spi(&spi, PTD0); |
| wim | 0:d64854a60f95 | 695 | * |
| wim | 0:d64854a60f95 | 696 | * Serial pc(USBTX,USBRX); |
| wim | 0:d64854a60f95 | 697 | * |
| wim | 0:d64854a60f95 | 698 | * int main() { |
| wim | 0:d64854a60f95 | 699 | * pc.printf("\nHello World!\n"); |
| wim | 0:d64854a60f95 | 700 | * |
| wim | 0:d64854a60f95 | 701 | * while(1) { |
| wim | 0:d64854a60f95 | 702 | * serial_spi.ioSetState(0x00); |
| wim | 0:d64854a60f95 | 703 | * wait(0.5); |
| wim | 2:76cb93b511f2 | 704 | * serial_spi.ioSetState(0xFF); |
| wim | 2:76cb93b511f2 | 705 | * wait(0.5); |
| wim | 2:76cb93b511f2 | 706 | * serial_spi.putc('*'); |
| wim | 0:d64854a60f95 | 707 | * pc.putc('*'); |
| wim | 0:d64854a60f95 | 708 | * } |
| wim | 0:d64854a60f95 | 709 | * } |
| wim | 0:d64854a60f95 | 710 | * |
| wim | 0:d64854a60f95 | 711 | * @endcode |
| wim | 0:d64854a60f95 | 712 | */ |
| wim | 0:d64854a60f95 | 713 | class SC16IS750_SPI : public SC16IS750 { |
| wim | 0:d64854a60f95 | 714 | public: |
| wim | 0:d64854a60f95 | 715 | |
| wim | 4:12446ee9f9c8 | 716 | /** Create an SC16IS750_SPI object using a specified SPI bus and CS |
| wim | 0:d64854a60f95 | 717 | * |
| wim | 0:d64854a60f95 | 718 | * @param SPI &spi the SPI port to connect to |
| wim | 4:12446ee9f9c8 | 719 | * @param cs Pinname of the CS pin (active low) |
| wim | 4:12446ee9f9c8 | 720 | * @param rst Pinname for Reset pin (active low) Optional, Default = NC |
| wim | 0:d64854a60f95 | 721 | */ |
| wim | 4:12446ee9f9c8 | 722 | SC16IS750_SPI(SPI *spi, PinName cs, PinName rst = NC); |
| wim | 4:12446ee9f9c8 | 723 | |
| wim | 4:12446ee9f9c8 | 724 | /** Destruct SC16IS750_SPI bridge object |
| wim | 4:12446ee9f9c8 | 725 | * |
| wim | 4:12446ee9f9c8 | 726 | * @param none |
| wim | 4:12446ee9f9c8 | 727 | * @return none |
| wim | 4:12446ee9f9c8 | 728 | */ |
| wim | 4:12446ee9f9c8 | 729 | virtual ~SC16IS750_SPI(); |
| wim | 4:12446ee9f9c8 | 730 | |
| wim | 0:d64854a60f95 | 731 | |
| wim | 0:d64854a60f95 | 732 | /** Write value to internal register. |
| wim | 1:0440152c5387 | 733 | * @param registerAddress The address of the Register (enum RegisterName) |
| wim | 0:d64854a60f95 | 734 | * @param data The 8bit value to write |
| wim | 0:d64854a60f95 | 735 | * @return none |
| wim | 0:d64854a60f95 | 736 | */ |
| wim | 0:d64854a60f95 | 737 | virtual void writeRegister(SC16IS750::RegisterName registerAddress, char data); |
| wim | 0:d64854a60f95 | 738 | |
| wim | 0:d64854a60f95 | 739 | /** Read value from internal register. |
| wim | 1:0440152c5387 | 740 | * @param registerAddress The address of the Register (enum RegisterName) |
| wim | 0:d64854a60f95 | 741 | * @return char The 8bit value read from the register |
| wim | 0:d64854a60f95 | 742 | */ |
| wim | 0:d64854a60f95 | 743 | virtual char readRegister(SC16IS750::RegisterName registerAddress); |
| wim | 0:d64854a60f95 | 744 | |
| wim | 3:9783b6bde958 | 745 | /** Write multiple datavalues to Transmitregister. |
| wim | 3:9783b6bde958 | 746 | * More Efficient implementation than writing individual bytes |
| wim | 3:9783b6bde958 | 747 | * Assume that previous check confirmed that the FIFO has sufficient free space to store the data |
| wim | 4:12446ee9f9c8 | 748 | * |
| wim | 3:9783b6bde958 | 749 | * @param char* databytes The pointer to the block of data |
| wim | 3:9783b6bde958 | 750 | * @param len The number of bytes to write |
| wim | 3:9783b6bde958 | 751 | * @return none |
| wim | 3:9783b6bde958 | 752 | */ |
| wim | 3:9783b6bde958 | 753 | virtual void writeDataBlock (const char *data, int len ); |
| wim | 3:9783b6bde958 | 754 | |
| wim | 4:12446ee9f9c8 | 755 | /** Hardware Reset SC16IS750 device. |
| wim | 4:12446ee9f9c8 | 756 | * This method is only functional when the Reset pin has been declared and is also connected |
| wim | 4:12446ee9f9c8 | 757 | * @param none |
| wim | 4:12446ee9f9c8 | 758 | * @return none |
| wim | 4:12446ee9f9c8 | 759 | */ |
| wim | 4:12446ee9f9c8 | 760 | virtual void hwReset(); |
| wim | 4:12446ee9f9c8 | 761 | |
| wim | 3:9783b6bde958 | 762 | |
| wim | 0:d64854a60f95 | 763 | protected: |
| wim | 0:d64854a60f95 | 764 | //protected is accessible to derived classes, but not to external users |
| wim | 0:d64854a60f95 | 765 | |
| wim | 0:d64854a60f95 | 766 | |
| wim | 0:d64854a60f95 | 767 | private: |
| wim | 0:d64854a60f95 | 768 | SPI *_spi; //SPI bus reference |
| wim | 4:12446ee9f9c8 | 769 | DigitalOut _cs; //CS of SPI device (active low) |
| wim | 4:12446ee9f9c8 | 770 | |
| wim | 4:12446ee9f9c8 | 771 | /** Optional Hardware Reset pin for the bridge device (active low) |
| wim | 4:12446ee9f9c8 | 772 | * Default PinName value is NC |
| wim | 4:12446ee9f9c8 | 773 | */ |
| wim | 4:12446ee9f9c8 | 774 | DigitalOut* _reset; //Reset the Bridge device (active low) |
| wim | 0:d64854a60f95 | 775 | |
| wim | 0:d64854a60f95 | 776 | }; |
| wim | 0:d64854a60f95 | 777 | |
| wim | 0:d64854a60f95 | 778 | |
| wim | 0:d64854a60f95 | 779 | |
| wim | 4:12446ee9f9c8 | 780 | /** Class SC16IS750_I2C for a bridge between I2C and a Serial port |
| wim | 0:d64854a60f95 | 781 | * |
| wim | 0:d64854a60f95 | 782 | * @code |
| wim | 0:d64854a60f95 | 783 | * #include "mbed.h" |
| wim | 0:d64854a60f95 | 784 | * #include "SC16IS750.h" |
| wim | 0:d64854a60f95 | 785 | * |
| wim | 0:d64854a60f95 | 786 | * I2C i2c(PTE0, PTE1); //SDA, SCL |
| wim | 0:d64854a60f95 | 787 | * SC16IS750_I2C serial_i2c(&i2c, DEFAULT_SC16IS750_ADDR); |
| wim | 0:d64854a60f95 | 788 | * |
| wim | 0:d64854a60f95 | 789 | * Serial pc(USBTX,USBRX); |
| wim | 0:d64854a60f95 | 790 | * |
| wim | 0:d64854a60f95 | 791 | * int main() { |
| wim | 0:d64854a60f95 | 792 | * pc.printf("\nHello World!\n"); |
| wim | 0:d64854a60f95 | 793 | * |
| wim | 0:d64854a60f95 | 794 | * while(1) { |
| wim | 0:d64854a60f95 | 795 | * serial_i2c.ioSetState(0x00); |
| wim | 0:d64854a60f95 | 796 | * wait(0.5); |
| wim | 2:76cb93b511f2 | 797 | * serial_i2c.ioSetState(0xFF); |
| wim | 2:76cb93b511f2 | 798 | * wait(0.5); |
| wim | 2:76cb93b511f2 | 799 | * serial_i2c.putc('*'); |
| wim | 0:d64854a60f95 | 800 | * pc.putc('*'); |
| wim | 0:d64854a60f95 | 801 | * } |
| wim | 0:d64854a60f95 | 802 | * } |
| wim | 0:d64854a60f95 | 803 | * |
| wim | 0:d64854a60f95 | 804 | * @endcode |
| wim | 0:d64854a60f95 | 805 | */ |
| wim | 0:d64854a60f95 | 806 | class SC16IS750_I2C : public SC16IS750 { |
| wim | 0:d64854a60f95 | 807 | public: |
| wim | 0:d64854a60f95 | 808 | |
| wim | 4:12446ee9f9c8 | 809 | /** Create an SC16IS750_I2C object using a specified I2C bus and slaveaddress |
| wim | 0:d64854a60f95 | 810 | * |
| wim | 0:d64854a60f95 | 811 | * @param I2C &i2c the I2C port to connect to |
| wim | 0:d64854a60f95 | 812 | * @param char deviceAddress the address of the SC16IS750 |
| wim | 4:12446ee9f9c8 | 813 | * @param rst Pinname for Reset pin (active low) Optional, Default = NC |
| wim | 0:d64854a60f95 | 814 | */ |
| wim | 4:12446ee9f9c8 | 815 | SC16IS750_I2C(I2C *i2c, uint8_t deviceAddress = SC16IS750_DEFAULT_ADDR, PinName rst = NC); |
| wim | 4:12446ee9f9c8 | 816 | |
| wim | 4:12446ee9f9c8 | 817 | |
| wim | 4:12446ee9f9c8 | 818 | /** Destruct SC16IS750_I2C bridge object |
| wim | 4:12446ee9f9c8 | 819 | * |
| wim | 4:12446ee9f9c8 | 820 | * @param none |
| wim | 4:12446ee9f9c8 | 821 | * @return none |
| wim | 4:12446ee9f9c8 | 822 | */ |
| wim | 4:12446ee9f9c8 | 823 | virtual ~SC16IS750_I2C(); |
| wim | 4:12446ee9f9c8 | 824 | |
| wim | 0:d64854a60f95 | 825 | |
| wim | 0:d64854a60f95 | 826 | /** Write value to internal register. |
| wim | 1:0440152c5387 | 827 | * @param registerAddress The address of the Register (enum RegisterName) |
| wim | 0:d64854a60f95 | 828 | * @param data The 8bit value to write |
| wim | 0:d64854a60f95 | 829 | * @return none |
| wim | 0:d64854a60f95 | 830 | */ |
| wim | 0:d64854a60f95 | 831 | virtual void writeRegister(SC16IS750::RegisterName register_address, char data ); |
| wim | 0:d64854a60f95 | 832 | |
| wim | 0:d64854a60f95 | 833 | /** Read value from internal register. |
| wim | 1:0440152c5387 | 834 | * @param registerAddress The address of the Register (enum RegisterName) |
| wim | 0:d64854a60f95 | 835 | * @return char The 8bit value read from the register |
| wim | 0:d64854a60f95 | 836 | */ |
| wim | 0:d64854a60f95 | 837 | virtual char readRegister(SC16IS750::RegisterName register_address ); |
| wim | 0:d64854a60f95 | 838 | |
| wim | 3:9783b6bde958 | 839 | |
| wim | 3:9783b6bde958 | 840 | /** Write multiple datavalues to Transmitregister. |
| wim | 3:9783b6bde958 | 841 | * More Efficient implementation than writing individual bytes |
| wim | 3:9783b6bde958 | 842 | * Assume that previous check confirmed that the FIFO has sufficient free space to store the data |
| wim | 3:9783b6bde958 | 843 | * Pure virtual, must be declared in derived class. |
| wim | 3:9783b6bde958 | 844 | * @param char* databytes The pointer to the block of data |
| wim | 3:9783b6bde958 | 845 | * @param len The number of bytes to write |
| wim | 3:9783b6bde958 | 846 | * @return none |
| wim | 3:9783b6bde958 | 847 | */ |
| wim | 3:9783b6bde958 | 848 | virtual void writeDataBlock (const char *data, int len ); |
| wim | 3:9783b6bde958 | 849 | |
| wim | 4:12446ee9f9c8 | 850 | |
| wim | 4:12446ee9f9c8 | 851 | /** Hardware Reset SC16IS750 device. |
| wim | 4:12446ee9f9c8 | 852 | * This method is only functional when the Reset pin has been declared and is also connected |
| wim | 4:12446ee9f9c8 | 853 | * @param none |
| wim | 4:12446ee9f9c8 | 854 | * @return none |
| wim | 4:12446ee9f9c8 | 855 | */ |
| wim | 4:12446ee9f9c8 | 856 | virtual void hwReset(); |
| wim | 4:12446ee9f9c8 | 857 | |
| wim | 4:12446ee9f9c8 | 858 | |
| wim | 0:d64854a60f95 | 859 | protected: |
| wim | 0:d64854a60f95 | 860 | //protected is accessible to derived classes, but not to external users |
| wim | 0:d64854a60f95 | 861 | |
| wim | 0:d64854a60f95 | 862 | |
| wim | 0:d64854a60f95 | 863 | private: |
| wim | 0:d64854a60f95 | 864 | I2C *_i2c; //I2C bus reference |
| wim | 0:d64854a60f95 | 865 | uint8_t _slaveAddress; //I2C Slave address of device |
| wim | 4:12446ee9f9c8 | 866 | |
| wim | 4:12446ee9f9c8 | 867 | /** Optional Hardware Reset pin for the bridge device (active low) |
| wim | 4:12446ee9f9c8 | 868 | * Default PinName value is NC |
| wim | 4:12446ee9f9c8 | 869 | */ |
| wim | 4:12446ee9f9c8 | 870 | DigitalOut* _reset; //Reset the Bridge device (active low) |
| wim | 4:12446ee9f9c8 | 871 | |
| wim | 4:12446ee9f9c8 | 872 | }; |
| wim | 4:12446ee9f9c8 | 873 | |
| wim | 4:12446ee9f9c8 | 874 | |
| wim | 4:12446ee9f9c8 | 875 | |
| wim | 4:12446ee9f9c8 | 876 | /** Class SC16IS752_SPI for a bridge between SPI and a Serial port |
| wim | 4:12446ee9f9c8 | 877 | * |
| wim | 4:12446ee9f9c8 | 878 | * @code |
| wim | 4:12446ee9f9c8 | 879 | * #include "mbed.h" |
| wim | 4:12446ee9f9c8 | 880 | * #include "SC16IS750.h" |
| wim | 4:12446ee9f9c8 | 881 | * |
| wim | 4:12446ee9f9c8 | 882 | * SPI spi(PTD2, PTD3, PTD1); //MOSI, MISO, SCK |
| wim | 4:12446ee9f9c8 | 883 | * SC16IS750_SPI serial_spi(&spi, PTD0, NC, SC16IS750::Channel_B); |
| wim | 4:12446ee9f9c8 | 884 | * |
| wim | 4:12446ee9f9c8 | 885 | * Serial pc(USBTX,USBRX); |
| wim | 4:12446ee9f9c8 | 886 | * |
| wim | 4:12446ee9f9c8 | 887 | * int main() { |
| wim | 4:12446ee9f9c8 | 888 | * pc.printf("\nHello World!\n"); |
| wim | 4:12446ee9f9c8 | 889 | * |
| wim | 4:12446ee9f9c8 | 890 | * while(1) { |
| wim | 4:12446ee9f9c8 | 891 | * serial_spi.ioSetState(0x00); |
| wim | 4:12446ee9f9c8 | 892 | * wait(0.5); |
| wim | 4:12446ee9f9c8 | 893 | * serial_spi.ioSetState(0xFF); |
| wim | 4:12446ee9f9c8 | 894 | * wait(0.5); |
| wim | 4:12446ee9f9c8 | 895 | * serial_spi.putc('*'); |
| wim | 4:12446ee9f9c8 | 896 | * pc.putc('*'); |
| wim | 4:12446ee9f9c8 | 897 | * } |
| wim | 4:12446ee9f9c8 | 898 | * } |
| wim | 4:12446ee9f9c8 | 899 | * |
| wim | 4:12446ee9f9c8 | 900 | * @endcode |
| wim | 4:12446ee9f9c8 | 901 | */ |
| wim | 4:12446ee9f9c8 | 902 | class SC16IS752_SPI : public SC16IS750 { |
| wim | 4:12446ee9f9c8 | 903 | public: |
| wim | 4:12446ee9f9c8 | 904 | |
| wim | 4:12446ee9f9c8 | 905 | /** Create an SC16IS752_SPI object using a specified SPI bus and CS |
| wim | 4:12446ee9f9c8 | 906 | * |
| wim | 4:12446ee9f9c8 | 907 | * @param SPI &spi the SPI port to connect to |
| wim | 4:12446ee9f9c8 | 908 | * @param cs Pinname of the CS pin (active low) |
| wim | 4:12446ee9f9c8 | 909 | * @param rst Pinname for Reset pin (active low) Optional, Default = NC |
| wim | 4:12446ee9f9c8 | 910 | * @param channel UART ChannelName, Default = Channel_A |
| wim | 4:12446ee9f9c8 | 911 | */ |
| wim | 4:12446ee9f9c8 | 912 | SC16IS752_SPI(SPI *spi, PinName cs, PinName rst = NC, ChannelName channel = SC16IS750::Channel_A ); |
| wim | 4:12446ee9f9c8 | 913 | |
| wim | 4:12446ee9f9c8 | 914 | /** Destruct SC16IS752_SPI bridge object |
| wim | 4:12446ee9f9c8 | 915 | * |
| wim | 4:12446ee9f9c8 | 916 | * @param none |
| wim | 4:12446ee9f9c8 | 917 | * @return none |
| wim | 4:12446ee9f9c8 | 918 | */ |
| wim | 4:12446ee9f9c8 | 919 | virtual ~SC16IS752_SPI(); |
| wim | 4:12446ee9f9c8 | 920 | |
| wim | 4:12446ee9f9c8 | 921 | |
| wim | 4:12446ee9f9c8 | 922 | /** Write value to internal register. |
| wim | 4:12446ee9f9c8 | 923 | * @param registerAddress The address of the Register (enum RegisterName) |
| wim | 4:12446ee9f9c8 | 924 | * @param data The 8bit value to write |
| wim | 4:12446ee9f9c8 | 925 | * @return none |
| wim | 4:12446ee9f9c8 | 926 | */ |
| wim | 4:12446ee9f9c8 | 927 | virtual void writeRegister(SC16IS750::RegisterName registerAddress, char data); |
| wim | 4:12446ee9f9c8 | 928 | |
| wim | 4:12446ee9f9c8 | 929 | /** Read value from internal register. |
| wim | 4:12446ee9f9c8 | 930 | * @param registerAddress The address of the Register (enum RegisterName) |
| wim | 4:12446ee9f9c8 | 931 | * @return char The 8bit value read from the register |
| wim | 4:12446ee9f9c8 | 932 | */ |
| wim | 4:12446ee9f9c8 | 933 | virtual char readRegister(SC16IS750::RegisterName registerAddress); |
| wim | 4:12446ee9f9c8 | 934 | |
| wim | 4:12446ee9f9c8 | 935 | /** Write multiple datavalues to Transmitregister. |
| wim | 4:12446ee9f9c8 | 936 | * More Efficient implementation than writing individual bytes |
| wim | 4:12446ee9f9c8 | 937 | * Assume that previous check confirmed that the FIFO has sufficient free space to store the data |
| wim | 4:12446ee9f9c8 | 938 | * |
| wim | 4:12446ee9f9c8 | 939 | * @param char* databytes The pointer to the block of data |
| wim | 4:12446ee9f9c8 | 940 | * @param len The number of bytes to write |
| wim | 4:12446ee9f9c8 | 941 | * @return none |
| wim | 4:12446ee9f9c8 | 942 | */ |
| wim | 4:12446ee9f9c8 | 943 | virtual void writeDataBlock (const char *data, int len ); |
| wim | 4:12446ee9f9c8 | 944 | |
| wim | 4:12446ee9f9c8 | 945 | /** Hardware Reset SC16IS750 device. |
| wim | 4:12446ee9f9c8 | 946 | * This method is only functional when the Reset pin has been declared and is also connected |
| wim | 4:12446ee9f9c8 | 947 | * @param none |
| wim | 4:12446ee9f9c8 | 948 | * @return none |
| wim | 4:12446ee9f9c8 | 949 | */ |
| wim | 4:12446ee9f9c8 | 950 | virtual void hwReset(); |
| wim | 4:12446ee9f9c8 | 951 | |
| wim | 4:12446ee9f9c8 | 952 | |
| wim | 4:12446ee9f9c8 | 953 | protected: |
| wim | 4:12446ee9f9c8 | 954 | //protected is accessible to derived classes, but not to external users |
| wim | 4:12446ee9f9c8 | 955 | |
| wim | 4:12446ee9f9c8 | 956 | |
| wim | 4:12446ee9f9c8 | 957 | private: |
| wim | 4:12446ee9f9c8 | 958 | SPI *_spi; //SPI bus reference |
| wim | 4:12446ee9f9c8 | 959 | DigitalOut _cs; //CS of SPI device (active low) |
| wim | 4:12446ee9f9c8 | 960 | |
| wim | 4:12446ee9f9c8 | 961 | /** Optional Hardware Reset pin for the bridge device (active low) |
| wim | 4:12446ee9f9c8 | 962 | * Default PinName value is NC |
| wim | 4:12446ee9f9c8 | 963 | */ |
| wim | 4:12446ee9f9c8 | 964 | DigitalOut* _reset; //Reset the Bridge device (active low) |
| wim | 4:12446ee9f9c8 | 965 | |
| wim | 4:12446ee9f9c8 | 966 | // Save Channel setting |
| wim | 4:12446ee9f9c8 | 967 | ChannelName _channel; |
| wim | 4:12446ee9f9c8 | 968 | |
| wim | 4:12446ee9f9c8 | 969 | }; |
| wim | 4:12446ee9f9c8 | 970 | |
| wim | 4:12446ee9f9c8 | 971 | |
| wim | 4:12446ee9f9c8 | 972 | |
| wim | 4:12446ee9f9c8 | 973 | /** Class SC16IS752_I2C for a bridge between I2C and a Serial port |
| wim | 4:12446ee9f9c8 | 974 | * |
| wim | 4:12446ee9f9c8 | 975 | * @code |
| wim | 4:12446ee9f9c8 | 976 | * #include "mbed.h" |
| wim | 4:12446ee9f9c8 | 977 | * #include "SC16IS750.h" |
| wim | 4:12446ee9f9c8 | 978 | * |
| wim | 4:12446ee9f9c8 | 979 | * I2C i2c(PTE0, PTE1); //SDA, SCL |
| wim | 4:12446ee9f9c8 | 980 | * SC16IS752_I2C serial_i2c(&i2c, DEFAULT_SC16IS750_ADDR, NC, SC16IS750::Channel_A); |
| wim | 4:12446ee9f9c8 | 981 | * |
| wim | 4:12446ee9f9c8 | 982 | * Serial pc(USBTX,USBRX); |
| wim | 4:12446ee9f9c8 | 983 | * |
| wim | 4:12446ee9f9c8 | 984 | * int main() { |
| wim | 4:12446ee9f9c8 | 985 | * pc.printf("\nHello World!\n"); |
| wim | 4:12446ee9f9c8 | 986 | * |
| wim | 4:12446ee9f9c8 | 987 | * while(1) { |
| wim | 4:12446ee9f9c8 | 988 | * serial_i2c.ioSetState(0x00); |
| wim | 4:12446ee9f9c8 | 989 | * wait(0.5); |
| wim | 4:12446ee9f9c8 | 990 | * serial_i2c.ioSetState(0xFF); |
| wim | 4:12446ee9f9c8 | 991 | * wait(0.5); |
| wim | 4:12446ee9f9c8 | 992 | * serial_i2c.putc('*'); |
| wim | 4:12446ee9f9c8 | 993 | * pc.putc('*'); |
| wim | 4:12446ee9f9c8 | 994 | * } |
| wim | 4:12446ee9f9c8 | 995 | * } |
| wim | 4:12446ee9f9c8 | 996 | * |
| wim | 4:12446ee9f9c8 | 997 | * @endcode |
| wim | 4:12446ee9f9c8 | 998 | */ |
| wim | 4:12446ee9f9c8 | 999 | class SC16IS752_I2C : public SC16IS750 { |
| wim | 4:12446ee9f9c8 | 1000 | public: |
| wim | 4:12446ee9f9c8 | 1001 | |
| wim | 4:12446ee9f9c8 | 1002 | /** Create an SC16IS752_I2C object using a specified I2C bus, slaveaddress and Channel |
| wim | 4:12446ee9f9c8 | 1003 | * |
| wim | 4:12446ee9f9c8 | 1004 | * @param I2C &i2c the I2C port to connect to |
| wim | 4:12446ee9f9c8 | 1005 | * @param char deviceAddress the address of the SC16IS750 |
| wim | 4:12446ee9f9c8 | 1006 | * @param rst Pinname for Reset pin (active low) Optional, Default = NC |
| wim | 4:12446ee9f9c8 | 1007 | * @param channel UART ChannelName, Default = Channel_A |
| wim | 4:12446ee9f9c8 | 1008 | */ |
| wim | 4:12446ee9f9c8 | 1009 | SC16IS752_I2C(I2C *i2c, uint8_t deviceAddress = SC16IS750_DEFAULT_ADDR, PinName rst = NC, ChannelName channel = SC16IS750::Channel_A); |
| wim | 4:12446ee9f9c8 | 1010 | |
| wim | 4:12446ee9f9c8 | 1011 | |
| wim | 4:12446ee9f9c8 | 1012 | /** Destruct SC16IS752_I2C bridge object |
| wim | 4:12446ee9f9c8 | 1013 | * |
| wim | 4:12446ee9f9c8 | 1014 | * @param none |
| wim | 4:12446ee9f9c8 | 1015 | * @return none |
| wim | 4:12446ee9f9c8 | 1016 | */ |
| wim | 4:12446ee9f9c8 | 1017 | virtual ~SC16IS752_I2C(); |
| wim | 4:12446ee9f9c8 | 1018 | |
| wim | 4:12446ee9f9c8 | 1019 | |
| wim | 4:12446ee9f9c8 | 1020 | /** Write value to internal register. |
| wim | 4:12446ee9f9c8 | 1021 | * @param registerAddress The address of the Register (enum RegisterName) |
| wim | 4:12446ee9f9c8 | 1022 | * @param data The 8bit value to write |
| wim | 4:12446ee9f9c8 | 1023 | * @return none |
| wim | 4:12446ee9f9c8 | 1024 | */ |
| wim | 4:12446ee9f9c8 | 1025 | virtual void writeRegister(SC16IS750::RegisterName register_address, char data ); |
| wim | 4:12446ee9f9c8 | 1026 | |
| wim | 4:12446ee9f9c8 | 1027 | /** Read value from internal register. |
| wim | 4:12446ee9f9c8 | 1028 | * @param registerAddress The address of the Register (enum RegisterName) |
| wim | 4:12446ee9f9c8 | 1029 | * @return char The 8bit value read from the register |
| wim | 4:12446ee9f9c8 | 1030 | */ |
| wim | 4:12446ee9f9c8 | 1031 | virtual char readRegister(SC16IS750::RegisterName register_address ); |
| wim | 4:12446ee9f9c8 | 1032 | |
| wim | 4:12446ee9f9c8 | 1033 | |
| wim | 4:12446ee9f9c8 | 1034 | /** Write multiple datavalues to Transmitregister. |
| wim | 4:12446ee9f9c8 | 1035 | * More Efficient implementation than writing individual bytes |
| wim | 4:12446ee9f9c8 | 1036 | * Assume that previous check confirmed that the FIFO has sufficient free space to store the data |
| wim | 4:12446ee9f9c8 | 1037 | * Pure virtual, must be declared in derived class. |
| wim | 4:12446ee9f9c8 | 1038 | * @param char* databytes The pointer to the block of data |
| wim | 4:12446ee9f9c8 | 1039 | * @param len The number of bytes to write |
| wim | 4:12446ee9f9c8 | 1040 | * @return none |
| wim | 4:12446ee9f9c8 | 1041 | */ |
| wim | 4:12446ee9f9c8 | 1042 | virtual void writeDataBlock (const char *data, int len ); |
| wim | 4:12446ee9f9c8 | 1043 | |
| wim | 4:12446ee9f9c8 | 1044 | |
| wim | 4:12446ee9f9c8 | 1045 | /** Hardware Reset SC16IS752 device. |
| wim | 4:12446ee9f9c8 | 1046 | * This method is only functional when the Reset pin has been declared and is also connected |
| wim | 4:12446ee9f9c8 | 1047 | * @param none |
| wim | 4:12446ee9f9c8 | 1048 | * @return none |
| wim | 4:12446ee9f9c8 | 1049 | */ |
| wim | 4:12446ee9f9c8 | 1050 | virtual void hwReset(); |
| wim | 4:12446ee9f9c8 | 1051 | |
| wim | 4:12446ee9f9c8 | 1052 | |
| wim | 4:12446ee9f9c8 | 1053 | protected: |
| wim | 4:12446ee9f9c8 | 1054 | //protected is accessible to derived classes, but not to external users |
| wim | 4:12446ee9f9c8 | 1055 | |
| wim | 4:12446ee9f9c8 | 1056 | |
| wim | 4:12446ee9f9c8 | 1057 | private: |
| wim | 4:12446ee9f9c8 | 1058 | I2C *_i2c; //I2C bus reference |
| wim | 4:12446ee9f9c8 | 1059 | uint8_t _slaveAddress; //I2C Slave address of device |
| wim | 4:12446ee9f9c8 | 1060 | |
| wim | 4:12446ee9f9c8 | 1061 | /** Optional Hardware Reset pin for the bridge device (active low) |
| wim | 4:12446ee9f9c8 | 1062 | * Default PinName value is NC |
| wim | 4:12446ee9f9c8 | 1063 | */ |
| wim | 4:12446ee9f9c8 | 1064 | DigitalOut* _reset; //Reset the Bridge device (active low) |
| wim | 4:12446ee9f9c8 | 1065 | |
| wim | 4:12446ee9f9c8 | 1066 | // Save Channel setting |
| wim | 4:12446ee9f9c8 | 1067 | ChannelName _channel; |
| wim | 4:12446ee9f9c8 | 1068 | |
| wim | 0:d64854a60f95 | 1069 | }; |
| wim | 0:d64854a60f95 | 1070 | |
| wim | 0:d64854a60f95 | 1071 | |
| wim | 0:d64854a60f95 | 1072 | #endif // _SC16IS750_H |