Driver for TI's CC1200 radio ICs. Forget hardcoded register settings -- this driver calculates everything from scratch!
Dependents: CC1200-MorseEncoder CC1200-Examples
CC1200 Driver
by Jamie Smith / USC Rocket Propulsion Lab
After months of work, we are proud to present our driver for Texas Instruments' CC1200 digital radio IC! This driver has been written from scratch to be an easy and flexible way of using this radio transceiver. For our application, we needed to be able to tune each and every setting of the radio to try and eke that last bit of performance of our system - so using premade configurations alone wasn't going to cut it! Instead, this driver calculates each parameter of the radio using the equations and instructions given in the datasheet. So, you can tweak parameters to your heart's content, and you shouldn't have to do any math yourself!
Features
- Automatic calculation of correct register values for:
- RF frequency
- FSK deviation
- Symbol rate
- Output power
- RX filter bandwidth (this one's harder than it looks!)
- Easy handling of data packets
- GPIO configuration
- Preamble and sync word configuration
- RTOS compatible (always locks SPI bus during transactions)
- Two debug levels available
- RSSI and LQI support
Not Supported
- Transparent mode
- FM mode
- ASK parameter configuration
- Frequency offsets
Examples
- See the example project here for an example of how to use the driver.
- Another example (using a more exotic configuration) is the CC1200-MorseEncoder.
Changelog
Version 1.2 May 3 2021
- Added unfinished infinite length packet support via the readStream() and writeStream() functions. The API is complete and basic usage works but there's still a bug I haven't been able to track down yet where incorrect data is transmitted at the end of a stream. Use with caution!
- Added
preferHigherCICDec
parameter tosetRXFilterBandwidth
- Removed
setIFMixCFG()
(which takes a byte parameter) and replaced it withsetIFCfg()
, which takes documented enum class values. - Added
setAGCSettleWait()
, which per my testing is needed for correct 430MHz operation. - Added support for reading RSSI and LQI values, both from packet appended status bytes and from the registers.
- Update 430MHz black box registers based on SmartRF values
- Removed
setIQMismatchCompensationEnabled()
. This call has been replaced by the new 2nd parameter tosetIFCfg()
.
Version 1.1 Aug 28 2020
- Add fixed length packet support and other features needed for Morse support.
- Fix bug causing weird behavior with low sample rates (<1ksps).
NOTE: you must now call setPacketMode() when configuring the radio.
Version 1.0 Aug 10 2020
Initial Release
CC1200Bits.h@0:0c3532738887, 2020-06-30 (annotated)
- Committer:
- Jamie Smith
- Date:
- Tue Jun 30 02:26:28 2020 -0700
- Revision:
- 0:0c3532738887
- Child:
- 1:98af824b145e
Add initial version of driver
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
Jamie Smith |
0:0c3532738887 | 1 | // |
Jamie Smith |
0:0c3532738887 | 2 | // Bit shifts for CC1200 registers |
Jamie Smith |
0:0c3532738887 | 3 | // |
Jamie Smith |
0:0c3532738887 | 4 | |
Jamie Smith |
0:0c3532738887 | 5 | #ifndef LIGHTSPEEDRANGEFINDER_CC1200BITS_H |
Jamie Smith |
0:0c3532738887 | 6 | #define LIGHTSPEEDRANGEFINDER_CC1200BITS_H |
Jamie Smith |
0:0c3532738887 | 7 | |
Jamie Smith |
0:0c3532738887 | 8 | #define PKT_CFG2_BYTE_SWAP_EN 6 |
Jamie Smith |
0:0c3532738887 | 9 | #define PKT_CFG2_FG_MODE_EN 5 |
Jamie Smith |
0:0c3532738887 | 10 | #define PKT_CFG2_CCA_MODE 2 |
Jamie Smith |
0:0c3532738887 | 11 | #define PKT_CFG2_PKT_FORMAT 0 |
Jamie Smith |
0:0c3532738887 | 12 | |
Jamie Smith |
0:0c3532738887 | 13 | #define MDMCFG2_ASK_SHAPE 7 |
Jamie Smith |
0:0c3532738887 | 14 | #define MDMCFG2_SYMBOL_MAP_CFG 4 |
Jamie Smith |
0:0c3532738887 | 15 | #define MDMCFG2_UPSAMPLER_P 1 |
Jamie Smith |
0:0c3532738887 | 16 | #define MDMCFG2_CFM_DATA_EN 0 |
Jamie Smith |
0:0c3532738887 | 17 | |
Jamie Smith |
0:0c3532738887 | 18 | #define MDMCFG1_CARRIER_SENSE_GATE 7 |
Jamie Smith |
0:0c3532738887 | 19 | #define MDMCFG1_FIFO_EN 6 |
Jamie Smith |
0:0c3532738887 | 20 | #define MDMCFG1_MANCHESTER_EN 5 |
Jamie Smith |
0:0c3532738887 | 21 | #define MDMCFG1_INVERT_DATA_EN 4 |
Jamie Smith |
0:0c3532738887 | 22 | #define MDMCFG1_COLLISION_DETECT_EN 3 |
Jamie Smith |
0:0c3532738887 | 23 | #define MDMCFG1_DVGA_GAIN 1 |
Jamie Smith |
0:0c3532738887 | 24 | #define MDMCFG1_SINGLE_ADC_EN 7 |
Jamie Smith |
0:0c3532738887 | 25 | |
Jamie Smith |
0:0c3532738887 | 26 | #define MDMCFG0_TRANSPARENT_MODE_EN 6 |
Jamie Smith |
0:0c3532738887 | 27 | #define MDMCFG0_TRANSPARENT_INTFACT 4 |
Jamie Smith |
0:0c3532738887 | 28 | #define MDMCFG0_DATA_FILTER_EN 3 |
Jamie Smith |
0:0c3532738887 | 29 | #define MDMCFG0_VITERBI_EN 2 |
Jamie Smith |
0:0c3532738887 | 30 | |
Jamie Smith |
0:0c3532738887 | 31 | #define MODCFG_DEV_E_MODEM_MODE 6 |
Jamie Smith |
0:0c3532738887 | 32 | #define MODCFG_DEV_E_MOD_FORMAT 3 |
Jamie Smith |
0:0c3532738887 | 33 | #define MODCFG_DEV_E_DEV_E 0 |
Jamie Smith |
0:0c3532738887 | 34 | |
Jamie Smith |
0:0c3532738887 | 35 | #define SYMBOL_RATE2_SRATE_E 4 |
Jamie Smith |
0:0c3532738887 | 36 | #define SYMBOL_RATE2_SRATE_M_19_16 0 |
Jamie Smith |
0:0c3532738887 | 37 | |
Jamie Smith |
0:0c3532738887 | 38 | #define PA_CFG1_PA_RAMP_SHAPE_EN 6 |
Jamie Smith |
0:0c3532738887 | 39 | #define PA_CFG1_PA_POWER_RAMP 0 |
Jamie Smith |
0:0c3532738887 | 40 | |
Jamie Smith |
0:0c3532738887 | 41 | #define PA_CFG0_FIRST_IPL 5 |
Jamie Smith |
0:0c3532738887 | 42 | #define PA_CFG0_SECOND_IPL 2 |
Jamie Smith |
0:0c3532738887 | 43 | #define PA_CFG0_RAMP_SHAPE 0 |
Jamie Smith |
0:0c3532738887 | 44 | |
Jamie Smith |
0:0c3532738887 | 45 | #define CHAN_BW_ADC_CIC_DECFACT 6 |
Jamie Smith |
0:0c3532738887 | 46 | #define CHAN_BW_BB_CIC_DECFACT 0 |
Jamie Smith |
0:0c3532738887 | 47 | |
Jamie Smith |
0:0c3532738887 | 48 | #define DCFILT_CFG_DCFILT_FREEZE_COEFF 6 |
Jamie Smith |
0:0c3532738887 | 49 | #define DCFILT_CFG_DCFILT_BW_SETTLE 3 |
Jamie Smith |
0:0c3532738887 | 50 | #define DCFILT_CFG_DCFILT_BW 0 |
Jamie Smith |
0:0c3532738887 | 51 | |
Jamie Smith |
0:0c3532738887 | 52 | #define PKT_CFG1_FEC_EN 7 |
Jamie Smith |
0:0c3532738887 | 53 | #define PKT_CFG1_WHITE_DATA 6 |
Jamie Smith |
0:0c3532738887 | 54 | #define PKT_CFG1_PN9_SWAP_EN 5 |
Jamie Smith |
0:0c3532738887 | 55 | #define PKT_CFG1_ADDR_CHECK_CFG 3 |
Jamie Smith |
0:0c3532738887 | 56 | #define PKT_CFG1_CRC_CFG 1 |
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0:0c3532738887 | 57 | #define PKT_CFG1_APPEND_STATUS |
Jamie Smith |
0:0c3532738887 | 58 | |
Jamie Smith |
0:0c3532738887 | 59 | #define PKT_CFG0_LENGTH_CONFIG 5 |
Jamie Smith |
0:0c3532738887 | 60 | #define PKT_CFG0_PKT_BIT_LEN 2 |
Jamie Smith |
0:0c3532738887 | 61 | #define PKT_CFG0_UART_MODE_EN 1 |
Jamie Smith |
0:0c3532738887 | 62 | #define PKT_CFG0_UART_SWAP_EN 0 |
Jamie Smith |
0:0c3532738887 | 63 | |
Jamie Smith |
0:0c3532738887 | 64 | #define RFEND_CFG1_RXOFF_MODE 4 |
Jamie Smith |
0:0c3532738887 | 65 | #define RFEND_CFG1_RX_TIME 1 |
Jamie Smith |
0:0c3532738887 | 66 | #define RFEND_CFG1_RX_TIME_QUAL 0 |
Jamie Smith |
0:0c3532738887 | 67 | |
Jamie Smith |
0:0c3532738887 | 68 | #define RFEND_CFG0_CAL_END_WAKE_UP_EN 6 |
Jamie Smith |
0:0c3532738887 | 69 | #define RFEND_CFG0_TXOFF_MODE 4 |
Jamie Smith |
0:0c3532738887 | 70 | #define RFEND_CFG0_TERM_ON_BAD_PACKET_EN 3 |
Jamie Smith |
0:0c3532738887 | 71 | #define RFEND_CFG0_ANT_DIV_RX_TERM_CFG 0 |
Jamie Smith |
0:0c3532738887 | 72 | |
Jamie Smith |
0:0c3532738887 | 73 | #define FS_CFG_FS_LOCK_EN 4 |
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0:0c3532738887 | 74 | #define FS_CFG_FSD_BANDSELECT 0 |
Jamie Smith |
0:0c3532738887 | 75 | |
Jamie Smith |
0:0c3532738887 | 76 | #define FSCAL_CTRL_LOCK 0 |
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0:0c3532738887 | 77 | |
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0:0c3532738887 | 78 | #define IF_MIX_CFG_CMIX_CFG 2 |
Jamie Smith |
0:0c3532738887 | 79 | |
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0:0c3532738887 | 80 | // bits are the same for all GPIO registers |
Jamie Smith |
0:0c3532738887 | 81 | #define GPIO_ATRAN 7 |
Jamie Smith |
0:0c3532738887 | 82 | #define GPIO_INV 6 |
Jamie Smith |
0:0c3532738887 | 83 | #define GPIO_CFG 0 |
Jamie Smith |
0:0c3532738887 | 84 | |
Jamie Smith |
0:0c3532738887 | 85 | #define IQIC_IQIC_EN 7 |
Jamie Smith |
0:0c3532738887 | 86 | #define IQIC_IQIC_UPDATE_COEFF_EN 6 |
Jamie Smith |
0:0c3532738887 | 87 | #define IQIC_BLEN_SETTLE 4 |
Jamie Smith |
0:0c3532738887 | 88 | #define IQIC_BLEN 2 |
Jamie Smith |
0:0c3532738887 | 89 | #define IQIC_IMGCH_LEVEL_THR 0 |
Jamie Smith |
0:0c3532738887 | 90 | |
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0:0c3532738887 | 91 | #define SYNC_CFG0_AUTO_CLEAR 5 |
Jamie Smith |
0:0c3532738887 | 92 | #define SYNC_CFG0_RX_CONFIG_LIMITATION 4 |
Jamie Smith |
0:0c3532738887 | 93 | #define SYNC_CFG0_PQT_GATING_EN 3 |
Jamie Smith |
0:0c3532738887 | 94 | #define SYNC_CFG0_EXT_SYNC_DETECT 2 |
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0:0c3532738887 | 95 | #define SYNC_CFG0_STRICT_SYNC_CHECK 0 |
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0:0c3532738887 | 96 | |
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0:0c3532738887 | 97 | #define SYNC_CFG1_SYNC_MODE 5 |
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0:0c3532738887 | 98 | #define SYNC_CFG1_SYNC_THR 0 |
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0:0c3532738887 | 99 | |
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0:0c3532738887 | 100 | #define SETTLING_CFG_FS_AUTOCAL 3 |
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0:0c3532738887 | 101 | #define SETTLING_CFG_LOCK_TIME 1 |
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0:0c3532738887 | 102 | #define SETTLING_CFG_FSREG_TIME 0 |
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0:0c3532738887 | 103 | |
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0:0c3532738887 | 104 | #define PREAMBLE_CFG1_NUM_PREAMBLE 2 |
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0:0c3532738887 | 105 | #define PREAMBLE_CFG1_PREAMBLE_WORD 0 |
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0:0c3532738887 | 106 | |
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0:0c3532738887 | 107 | #define PREAMBLE_CFG0_PQT_EN 7 |
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0:0c3532738887 | 108 | #define PREAMBLE_CFG0_PQT_VALID_TIMEOUT 4 |
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0:0c3532738887 | 109 | #define PREAMBLE_CFG0_PQT 0 |
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0:0c3532738887 | 110 | |
Jamie Smith |
0:0c3532738887 | 111 | #endif //LIGHTSPEEDRANGEFINDER_CC1200BITS_H |