MK64F12_can.h

00001 /*
00002 ** ###################################################################
00003 **     Compilers:           Keil ARM C/C++ Compiler
00004 **                          Freescale C/C++ for Embedded ARM
00005 **                          GNU C Compiler
00006 **                          IAR ANSI C/C++ Compiler for ARM
00007 **
00008 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
00009 **     Version:             rev. 2.5, 2014-02-10
00010 **     Build:               b140604
00011 **
00012 **     Abstract:
00013 **         Extension to the CMSIS register access layer header.
00014 **
00015 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
00016 **     All rights reserved.
00017 **
00018 **     (C) COPYRIGHT 2015-2015 ARM Limited
00019 **     ALL RIGHTS RESERVED
00020 **
00021 **     Redistribution and use in source and binary forms, with or without modification,
00022 **     are permitted provided that the following conditions are met:
00023 **
00024 **     o Redistributions of source code must retain the above copyright notice, this list
00025 **       of conditions and the following disclaimer.
00026 **
00027 **     o Redistributions in binary form must reproduce the above copyright notice, this
00028 **       list of conditions and the following disclaimer in the documentation and/or
00029 **       other materials provided with the distribution.
00030 **
00031 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00032 **       contributors may be used to endorse or promote products derived from this
00033 **       software without specific prior written permission.
00034 **
00035 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00036 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00037 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00038 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00039 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00040 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00041 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00042 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00043 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00044 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00045 **
00046 **     http:                 www.freescale.com
00047 **     mail:                 support@freescale.com
00048 **
00049 **     Revisions:
00050 **     - rev. 1.0 (2013-08-12)
00051 **         Initial version.
00052 **     - rev. 2.0 (2013-10-29)
00053 **         Register accessor macros added to the memory map.
00054 **         Symbols for Processor Expert memory map compatibility added to the memory map.
00055 **         Startup file for gcc has been updated according to CMSIS 3.2.
00056 **         System initialization updated.
00057 **         MCG - registers updated.
00058 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
00059 **     - rev. 2.1 (2013-10-30)
00060 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
00061 **     - rev. 2.2 (2013-12-09)
00062 **         DMA - EARS register removed.
00063 **         AIPS0, AIPS1 - MPRA register updated.
00064 **     - rev. 2.3 (2014-01-24)
00065 **         Update according to reference manual rev. 2
00066 **         ENET, MCG, MCM, SIM, USB - registers updated
00067 **     - rev. 2.4 (2014-02-10)
00068 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00069 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00070 **     - rev. 2.5 (2014-02-10)
00071 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00072 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00073 **         Module access macro module_BASES replaced by module_BASE_PTRS.
00074 **     - rev. 2.6 (2015-08-03) (ARM)
00075 **         All accesses to memory are replaced by equivalent macros; this allows
00076 **         memory read/write operations to be re-defined if needed (for example,
00077 **         to implement new security features
00078 **
00079 ** ###################################################################
00080 */
00081 
00082 /*
00083  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
00084  *
00085  * This file was generated automatically and any changes may be lost.
00086  */
00087 #ifndef __HW_CAN_REGISTERS_H__
00088 #define __HW_CAN_REGISTERS_H__
00089 
00090 #include "MK64F12.h"
00091 #include "fsl_bitaccess.h"
00092 
00093 /*
00094  * MK64F12 CAN
00095  *
00096  * Flex Controller Area Network module
00097  *
00098  * Registers defined in this header file:
00099  * - HW_CAN_MCR - Module Configuration Register
00100  * - HW_CAN_CTRL1 - Control 1 register
00101  * - HW_CAN_TIMER - Free Running Timer
00102  * - HW_CAN_RXMGMASK - Rx Mailboxes Global Mask Register
00103  * - HW_CAN_RX14MASK - Rx 14 Mask register
00104  * - HW_CAN_RX15MASK - Rx 15 Mask register
00105  * - HW_CAN_ECR - Error Counter
00106  * - HW_CAN_ESR1 - Error and Status 1 register
00107  * - HW_CAN_IMASK1 - Interrupt Masks 1 register
00108  * - HW_CAN_IFLAG1 - Interrupt Flags 1 register
00109  * - HW_CAN_CTRL2 - Control 2 register
00110  * - HW_CAN_ESR2 - Error and Status 2 register
00111  * - HW_CAN_CRCR - CRC Register
00112  * - HW_CAN_RXFGMASK - Rx FIFO Global Mask register
00113  * - HW_CAN_RXFIR - Rx FIFO Information Register
00114  * - HW_CAN_CSn - Message Buffer 0 CS Register
00115  * - HW_CAN_IDn - Message Buffer 0 ID Register
00116  * - HW_CAN_WORD0n - Message Buffer 0 WORD0 Register
00117  * - HW_CAN_WORD1n - Message Buffer 0 WORD1 Register
00118  * - HW_CAN_RXIMRn - Rx Individual Mask Registers
00119  *
00120  * - hw_can_t - Struct containing all module registers.
00121  */
00122 
00123 #define HW_CAN_INSTANCE_COUNT (1U) /*!< Number of instances of the CAN module. */
00124 
00125 /*******************************************************************************
00126  * HW_CAN_MCR - Module Configuration Register
00127  ******************************************************************************/
00128 
00129 /*!
00130  * @brief HW_CAN_MCR - Module Configuration Register (RW)
00131  *
00132  * Reset value: 0xD890000FU
00133  *
00134  * This register defines global system configurations, such as the module
00135  * operation modes and the maximum message buffer configuration.
00136  */
00137 typedef union _hw_can_mcr
00138 {
00139     uint32_t U;
00140     struct _hw_can_mcr_bitfields
00141     {
00142         uint32_t MAXMB : 7;            /*!< [6:0] Number Of The Last Message Buffer */
00143         uint32_t RESERVED0 : 1;        /*!< [7]  */
00144         uint32_t IDAM : 2;             /*!< [9:8] ID Acceptance Mode */
00145         uint32_t RESERVED1 : 2;        /*!< [11:10]  */
00146         uint32_t AEN : 1;              /*!< [12] Abort Enable */
00147         uint32_t LPRIOEN : 1;          /*!< [13] Local Priority Enable */
00148         uint32_t RESERVED2 : 2;        /*!< [15:14]  */
00149         uint32_t IRMQ : 1;             /*!< [16] Individual Rx Masking And Queue Enable */
00150         uint32_t SRXDIS : 1;           /*!< [17] Self Reception Disable */
00151         uint32_t RESERVED3 : 1;        /*!< [18]  */
00152         uint32_t WAKSRC : 1;           /*!< [19] Wake Up Source */
00153         uint32_t LPMACK : 1;           /*!< [20] Low-Power Mode Acknowledge */
00154         uint32_t WRNEN : 1;            /*!< [21] Warning Interrupt Enable */
00155         uint32_t SLFWAK : 1;           /*!< [22] Self Wake Up */
00156         uint32_t SUPV : 1;             /*!< [23] Supervisor Mode */
00157         uint32_t FRZACK : 1;           /*!< [24] Freeze Mode Acknowledge */
00158         uint32_t SOFTRST : 1;          /*!< [25] Soft Reset */
00159         uint32_t WAKMSK : 1;           /*!< [26] Wake Up Interrupt Mask */
00160         uint32_t NOTRDY : 1;           /*!< [27] FlexCAN Not Ready */
00161         uint32_t HALT : 1;             /*!< [28] Halt FlexCAN */
00162         uint32_t RFEN : 1;             /*!< [29] Rx FIFO Enable */
00163         uint32_t FRZ : 1;              /*!< [30] Freeze Enable */
00164         uint32_t MDIS : 1;             /*!< [31] Module Disable */
00165     } B;
00166 } hw_can_mcr_t;
00167 
00168 /*!
00169  * @name Constants and macros for entire CAN_MCR register
00170  */
00171 /*@{*/
00172 #define HW_CAN_MCR_ADDR(x)       ((x) + 0x0U)
00173 
00174 #define HW_CAN_MCR(x)            (*(__IO hw_can_mcr_t *) HW_CAN_MCR_ADDR(x))
00175 #define HW_CAN_MCR_RD(x)         (ADDRESS_READ(hw_can_mcr_t, HW_CAN_MCR_ADDR(x)))
00176 #define HW_CAN_MCR_WR(x, v)      (ADDRESS_WRITE(hw_can_mcr_t, HW_CAN_MCR_ADDR(x), v))
00177 #define HW_CAN_MCR_SET(x, v)     (HW_CAN_MCR_WR(x, HW_CAN_MCR_RD(x) |  (v)))
00178 #define HW_CAN_MCR_CLR(x, v)     (HW_CAN_MCR_WR(x, HW_CAN_MCR_RD(x) & ~(v)))
00179 #define HW_CAN_MCR_TOG(x, v)     (HW_CAN_MCR_WR(x, HW_CAN_MCR_RD(x) ^  (v)))
00180 /*@}*/
00181 
00182 /*
00183  * Constants & macros for individual CAN_MCR bitfields
00184  */
00185 
00186 /*!
00187  * @name Register CAN_MCR, field MAXMB[6:0] (RW)
00188  *
00189  * This 7-bit field defines the number of the last Message Buffers that will
00190  * take part in the matching and arbitration processes. The reset value (0x0F) is
00191  * equivalent to a 16 MB configuration. This field can be written only in Freeze
00192  * mode because it is blocked by hardware in other modes. Number of the last MB =
00193  * MAXMB MAXMB must be programmed with a value smaller than the parameter
00194  * NUMBER_OF_MB, otherwise the number of the last effective Message Buffer will be:
00195  * (NUMBER_OF_MB - 1) Additionally, the value of MAXMB must encompass the FIFO size
00196  * defined by CTRL2[RFFN]. MAXMB also impacts the definition of the minimum number
00197  * of peripheral clocks per CAN bit as described in Table "Minimum Ratio Between
00198  * Peripheral Clock Frequency and CAN Bit Rate" (in Section "Arbitration and
00199  * Matching Timing").
00200  */
00201 /*@{*/
00202 #define BP_CAN_MCR_MAXMB     (0U)          /*!< Bit position for CAN_MCR_MAXMB. */
00203 #define BM_CAN_MCR_MAXMB     (0x0000007FU) /*!< Bit mask for CAN_MCR_MAXMB. */
00204 #define BS_CAN_MCR_MAXMB     (7U)          /*!< Bit field size in bits for CAN_MCR_MAXMB. */
00205 
00206 /*! @brief Read current value of the CAN_MCR_MAXMB field. */
00207 #define BR_CAN_MCR_MAXMB(x)  (UNION_READ(hw_can_mcr_t, HW_CAN_MCR_ADDR(x), U, B.MAXMB))
00208 
00209 /*! @brief Format value for bitfield CAN_MCR_MAXMB. */
00210 #define BF_CAN_MCR_MAXMB(v)  ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_MAXMB) & BM_CAN_MCR_MAXMB)
00211 
00212 /*! @brief Set the MAXMB field to a new value. */
00213 #define BW_CAN_MCR_MAXMB(x, v) (HW_CAN_MCR_WR(x, (HW_CAN_MCR_RD(x) & ~BM_CAN_MCR_MAXMB) | BF_CAN_MCR_MAXMB(v)))
00214 /*@}*/
00215 
00216 /*!
00217  * @name Register CAN_MCR, field IDAM[9:8] (RW)
00218  *
00219  * This 2-bit field identifies the format of the Rx FIFO ID Filter Table
00220  * elements. Note that all elements of the table are configured at the same time by this
00221  * field (they are all the same format). See Section "Rx FIFO Structure". This
00222  * field can be written only in Freeze mode because it is blocked by hardware in
00223  * other modes.
00224  *
00225  * Values:
00226  * - 00 - Format A: One full ID (standard and extended) per ID Filter Table
00227  *     element.
00228  * - 01 - Format B: Two full standard IDs or two partial 14-bit (standard and
00229  *     extended) IDs per ID Filter Table element.
00230  * - 10 - Format C: Four partial 8-bit Standard IDs per ID Filter Table element.
00231  * - 11 - Format D: All frames rejected.
00232  */
00233 /*@{*/
00234 #define BP_CAN_MCR_IDAM      (8U)          /*!< Bit position for CAN_MCR_IDAM. */
00235 #define BM_CAN_MCR_IDAM      (0x00000300U) /*!< Bit mask for CAN_MCR_IDAM. */
00236 #define BS_CAN_MCR_IDAM      (2U)          /*!< Bit field size in bits for CAN_MCR_IDAM. */
00237 
00238 /*! @brief Read current value of the CAN_MCR_IDAM field. */
00239 #define BR_CAN_MCR_IDAM(x)   (UNION_READ(hw_can_mcr_t, HW_CAN_MCR_ADDR(x), U, B.IDAM))
00240 
00241 /*! @brief Format value for bitfield CAN_MCR_IDAM. */
00242 #define BF_CAN_MCR_IDAM(v)   ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_IDAM) & BM_CAN_MCR_IDAM)
00243 
00244 /*! @brief Set the IDAM field to a new value. */
00245 #define BW_CAN_MCR_IDAM(x, v) (HW_CAN_MCR_WR(x, (HW_CAN_MCR_RD(x) & ~BM_CAN_MCR_IDAM) | BF_CAN_MCR_IDAM(v)))
00246 /*@}*/
00247 
00248 /*!
00249  * @name Register CAN_MCR, field AEN[12] (RW)
00250  *
00251  * This bit is supplied for backwards compatibility with legacy applications.
00252  * When asserted, it enables the Tx abort mechanism. This mechanism guarantees a
00253  * safe procedure for aborting a pending transmission, so that no frame is sent in
00254  * the CAN bus without notification. This bit can be written only in Freeze mode
00255  * because it is blocked by hardware in other modes. When MCR[AEN] is asserted,
00256  * only the abort mechanism (see Section "Transmission Abort Mechanism") must be
00257  * used for updating Mailboxes configured for transmission. Writing the Abort code
00258  * into Rx Mailboxes can cause unpredictable results when the MCR[AEN] is
00259  * asserted.
00260  *
00261  * Values:
00262  * - 0 - Abort disabled.
00263  * - 1 - Abort enabled.
00264  */
00265 /*@{*/
00266 #define BP_CAN_MCR_AEN       (12U)         /*!< Bit position for CAN_MCR_AEN. */
00267 #define BM_CAN_MCR_AEN       (0x00001000U) /*!< Bit mask for CAN_MCR_AEN. */
00268 #define BS_CAN_MCR_AEN       (1U)          /*!< Bit field size in bits for CAN_MCR_AEN. */
00269 
00270 /*! @brief Read current value of the CAN_MCR_AEN field. */
00271 #define BR_CAN_MCR_AEN(x)    (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_AEN)))
00272 
00273 /*! @brief Format value for bitfield CAN_MCR_AEN. */
00274 #define BF_CAN_MCR_AEN(v)    ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_AEN) & BM_CAN_MCR_AEN)
00275 
00276 /*! @brief Set the AEN field to a new value. */
00277 #define BW_CAN_MCR_AEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_AEN), v))
00278 /*@}*/
00279 
00280 /*!
00281  * @name Register CAN_MCR, field LPRIOEN[13] (RW)
00282  *
00283  * This bit is provided for backwards compatibility with legacy applications. It
00284  * controls whether the local priority feature is enabled or not. It is used to
00285  * expand the ID used during the arbitration process. With this expanded ID
00286  * concept, the arbitration process is done based on the full 32-bit word, but the
00287  * actual transmitted ID still has 11-bit for standard frames and 29-bit for
00288  * extended frames. This bit can be written only in Freeze mode because it is blocked by
00289  * hardware in other modes.
00290  *
00291  * Values:
00292  * - 0 - Local Priority disabled.
00293  * - 1 - Local Priority enabled.
00294  */
00295 /*@{*/
00296 #define BP_CAN_MCR_LPRIOEN   (13U)         /*!< Bit position for CAN_MCR_LPRIOEN. */
00297 #define BM_CAN_MCR_LPRIOEN   (0x00002000U) /*!< Bit mask for CAN_MCR_LPRIOEN. */
00298 #define BS_CAN_MCR_LPRIOEN   (1U)          /*!< Bit field size in bits for CAN_MCR_LPRIOEN. */
00299 
00300 /*! @brief Read current value of the CAN_MCR_LPRIOEN field. */
00301 #define BR_CAN_MCR_LPRIOEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_LPRIOEN)))
00302 
00303 /*! @brief Format value for bitfield CAN_MCR_LPRIOEN. */
00304 #define BF_CAN_MCR_LPRIOEN(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_LPRIOEN) & BM_CAN_MCR_LPRIOEN)
00305 
00306 /*! @brief Set the LPRIOEN field to a new value. */
00307 #define BW_CAN_MCR_LPRIOEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_LPRIOEN), v))
00308 /*@}*/
00309 
00310 /*!
00311  * @name Register CAN_MCR, field IRMQ[16] (RW)
00312  *
00313  * This bit indicates whether Rx matching process will be based either on
00314  * individual masking and queue or on masking scheme with RXMGMASK, RX14MASK and
00315  * RX15MASK, RXFGMASK. This bit can be written only in Freeze mode because it is
00316  * blocked by hardware in other modes.
00317  *
00318  * Values:
00319  * - 0 - Individual Rx masking and queue feature are disabled. For backward
00320  *     compatibility with legacy applications, the reading of C/S word locks the MB
00321  *     even if it is EMPTY.
00322  * - 1 - Individual Rx masking and queue feature are enabled.
00323  */
00324 /*@{*/
00325 #define BP_CAN_MCR_IRMQ      (16U)         /*!< Bit position for CAN_MCR_IRMQ. */
00326 #define BM_CAN_MCR_IRMQ      (0x00010000U) /*!< Bit mask for CAN_MCR_IRMQ. */
00327 #define BS_CAN_MCR_IRMQ      (1U)          /*!< Bit field size in bits for CAN_MCR_IRMQ. */
00328 
00329 /*! @brief Read current value of the CAN_MCR_IRMQ field. */
00330 #define BR_CAN_MCR_IRMQ(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_IRMQ)))
00331 
00332 /*! @brief Format value for bitfield CAN_MCR_IRMQ. */
00333 #define BF_CAN_MCR_IRMQ(v)   ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_IRMQ) & BM_CAN_MCR_IRMQ)
00334 
00335 /*! @brief Set the IRMQ field to a new value. */
00336 #define BW_CAN_MCR_IRMQ(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_IRMQ), v))
00337 /*@}*/
00338 
00339 /*!
00340  * @name Register CAN_MCR, field SRXDIS[17] (RW)
00341  *
00342  * This bit defines whether FlexCAN is allowed to receive frames transmitted by
00343  * itself. If this bit is asserted, frames transmitted by the module will not be
00344  * stored in any MB, regardless if the MB is programmed with an ID that matches
00345  * the transmitted frame, and no interrupt flag or interrupt signal will be
00346  * generated due to the frame reception. This bit can be written only in Freeze mode
00347  * because it is blocked by hardware in other modes.
00348  *
00349  * Values:
00350  * - 0 - Self reception enabled.
00351  * - 1 - Self reception disabled.
00352  */
00353 /*@{*/
00354 #define BP_CAN_MCR_SRXDIS    (17U)         /*!< Bit position for CAN_MCR_SRXDIS. */
00355 #define BM_CAN_MCR_SRXDIS    (0x00020000U) /*!< Bit mask for CAN_MCR_SRXDIS. */
00356 #define BS_CAN_MCR_SRXDIS    (1U)          /*!< Bit field size in bits for CAN_MCR_SRXDIS. */
00357 
00358 /*! @brief Read current value of the CAN_MCR_SRXDIS field. */
00359 #define BR_CAN_MCR_SRXDIS(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SRXDIS)))
00360 
00361 /*! @brief Format value for bitfield CAN_MCR_SRXDIS. */
00362 #define BF_CAN_MCR_SRXDIS(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_SRXDIS) & BM_CAN_MCR_SRXDIS)
00363 
00364 /*! @brief Set the SRXDIS field to a new value. */
00365 #define BW_CAN_MCR_SRXDIS(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SRXDIS), v))
00366 /*@}*/
00367 
00368 /*!
00369  * @name Register CAN_MCR, field WAKSRC[19] (RW)
00370  *
00371  * This bit defines whether the integrated low-pass filter is applied to protect
00372  * the Rx CAN input from spurious wake up. This bit can be written only in
00373  * Freeze mode because it is blocked by hardware in other modes.
00374  *
00375  * Values:
00376  * - 0 - FlexCAN uses the unfiltered Rx input to detect recessive to dominant
00377  *     edges on the CAN bus.
00378  * - 1 - FlexCAN uses the filtered Rx input to detect recessive to dominant
00379  *     edges on the CAN bus.
00380  */
00381 /*@{*/
00382 #define BP_CAN_MCR_WAKSRC    (19U)         /*!< Bit position for CAN_MCR_WAKSRC. */
00383 #define BM_CAN_MCR_WAKSRC    (0x00080000U) /*!< Bit mask for CAN_MCR_WAKSRC. */
00384 #define BS_CAN_MCR_WAKSRC    (1U)          /*!< Bit field size in bits for CAN_MCR_WAKSRC. */
00385 
00386 /*! @brief Read current value of the CAN_MCR_WAKSRC field. */
00387 #define BR_CAN_MCR_WAKSRC(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WAKSRC)))
00388 
00389 /*! @brief Format value for bitfield CAN_MCR_WAKSRC. */
00390 #define BF_CAN_MCR_WAKSRC(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_WAKSRC) & BM_CAN_MCR_WAKSRC)
00391 
00392 /*! @brief Set the WAKSRC field to a new value. */
00393 #define BW_CAN_MCR_WAKSRC(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WAKSRC), v))
00394 /*@}*/
00395 
00396 /*!
00397  * @name Register CAN_MCR, field LPMACK[20] (RO)
00398  *
00399  * This read-only bit indicates that FlexCAN is in a low-power mode (Disable
00400  * mode , Stop mode ). A low-power mode cannot be entered until all current
00401  * transmission or reception processes have finished, so the CPU can poll the LPMACK bit
00402  * to know when FlexCAN has actually entered low power mode. LPMACK will be
00403  * asserted within 180 CAN bits from the low-power mode request by the CPU, and
00404  * negated within 2 CAN bits after the low-power mode request removal (see Section
00405  * "Protocol Timing").
00406  *
00407  * Values:
00408  * - 0 - FlexCAN is not in a low-power mode.
00409  * - 1 - FlexCAN is in a low-power mode.
00410  */
00411 /*@{*/
00412 #define BP_CAN_MCR_LPMACK    (20U)         /*!< Bit position for CAN_MCR_LPMACK. */
00413 #define BM_CAN_MCR_LPMACK    (0x00100000U) /*!< Bit mask for CAN_MCR_LPMACK. */
00414 #define BS_CAN_MCR_LPMACK    (1U)          /*!< Bit field size in bits for CAN_MCR_LPMACK. */
00415 
00416 /*! @brief Read current value of the CAN_MCR_LPMACK field. */
00417 #define BR_CAN_MCR_LPMACK(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_LPMACK)))
00418 /*@}*/
00419 
00420 /*!
00421  * @name Register CAN_MCR, field WRNEN[21] (RW)
00422  *
00423  * When asserted, this bit enables the generation of the TWRNINT and RWRNINT
00424  * flags in the Error and Status Register. If WRNEN is negated, the TWRNINT and
00425  * RWRNINT flags will always be zero, independent of the values of the error
00426  * counters, and no warning interrupt will ever be generated. This bit can be written
00427  * only in Freeze mode because it is blocked by hardware in other modes.
00428  *
00429  * Values:
00430  * - 0 - TWRNINT and RWRNINT bits are zero, independent of the values in the
00431  *     error counters.
00432  * - 1 - TWRNINT and RWRNINT bits are set when the respective error counter
00433  *     transitions from less than 96 to greater than or equal to 96.
00434  */
00435 /*@{*/
00436 #define BP_CAN_MCR_WRNEN     (21U)         /*!< Bit position for CAN_MCR_WRNEN. */
00437 #define BM_CAN_MCR_WRNEN     (0x00200000U) /*!< Bit mask for CAN_MCR_WRNEN. */
00438 #define BS_CAN_MCR_WRNEN     (1U)          /*!< Bit field size in bits for CAN_MCR_WRNEN. */
00439 
00440 /*! @brief Read current value of the CAN_MCR_WRNEN field. */
00441 #define BR_CAN_MCR_WRNEN(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WRNEN)))
00442 
00443 /*! @brief Format value for bitfield CAN_MCR_WRNEN. */
00444 #define BF_CAN_MCR_WRNEN(v)  ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_WRNEN) & BM_CAN_MCR_WRNEN)
00445 
00446 /*! @brief Set the WRNEN field to a new value. */
00447 #define BW_CAN_MCR_WRNEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WRNEN), v))
00448 /*@}*/
00449 
00450 /*!
00451  * @name Register CAN_MCR, field SLFWAK[22] (RW)
00452  *
00453  * This bit enables the Self Wake Up feature when FlexCAN is in a low-power mode
00454  * other than Disable mode. When this feature is enabled, the FlexCAN module
00455  * monitors the bus for wake up event, that is, a recessive-to-dominant transition.
00456  * If a wake up event is detected during Stop mode, then FlexCAN generates, if
00457  * enabled to do so, a Wake Up interrupt to the CPU so that it can exit Stop mode
00458  * globally and FlexCAN can request to resume the clocks. When FlexCAN is in a
00459  * low-power mode other than Disable mode, this bit cannot be written as it is
00460  * blocked by hardware.
00461  *
00462  * Values:
00463  * - 0 - FlexCAN Self Wake Up feature is disabled.
00464  * - 1 - FlexCAN Self Wake Up feature is enabled.
00465  */
00466 /*@{*/
00467 #define BP_CAN_MCR_SLFWAK    (22U)         /*!< Bit position for CAN_MCR_SLFWAK. */
00468 #define BM_CAN_MCR_SLFWAK    (0x00400000U) /*!< Bit mask for CAN_MCR_SLFWAK. */
00469 #define BS_CAN_MCR_SLFWAK    (1U)          /*!< Bit field size in bits for CAN_MCR_SLFWAK. */
00470 
00471 /*! @brief Read current value of the CAN_MCR_SLFWAK field. */
00472 #define BR_CAN_MCR_SLFWAK(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SLFWAK)))
00473 
00474 /*! @brief Format value for bitfield CAN_MCR_SLFWAK. */
00475 #define BF_CAN_MCR_SLFWAK(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_SLFWAK) & BM_CAN_MCR_SLFWAK)
00476 
00477 /*! @brief Set the SLFWAK field to a new value. */
00478 #define BW_CAN_MCR_SLFWAK(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SLFWAK), v))
00479 /*@}*/
00480 
00481 /*!
00482  * @name Register CAN_MCR, field SUPV[23] (RW)
00483  *
00484  * This bit configures the FlexCAN to be either in Supervisor or User mode. The
00485  * registers affected by this bit are marked as S/U in the Access Type column of
00486  * the module memory map. Reset value of this bit is 1, so the affected registers
00487  * start with Supervisor access allowance only . This bit can be written only in
00488  * Freeze mode because it is blocked by hardware in other modes.
00489  *
00490  * Values:
00491  * - 0 - FlexCAN is in User mode. Affected registers allow both Supervisor and
00492  *     Unrestricted accesses .
00493  * - 1 - FlexCAN is in Supervisor mode. Affected registers allow only Supervisor
00494  *     access. Unrestricted access behaves as though the access was done to an
00495  *     unimplemented register location .
00496  */
00497 /*@{*/
00498 #define BP_CAN_MCR_SUPV      (23U)         /*!< Bit position for CAN_MCR_SUPV. */
00499 #define BM_CAN_MCR_SUPV      (0x00800000U) /*!< Bit mask for CAN_MCR_SUPV. */
00500 #define BS_CAN_MCR_SUPV      (1U)          /*!< Bit field size in bits for CAN_MCR_SUPV. */
00501 
00502 /*! @brief Read current value of the CAN_MCR_SUPV field. */
00503 #define BR_CAN_MCR_SUPV(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SUPV)))
00504 
00505 /*! @brief Format value for bitfield CAN_MCR_SUPV. */
00506 #define BF_CAN_MCR_SUPV(v)   ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_SUPV) & BM_CAN_MCR_SUPV)
00507 
00508 /*! @brief Set the SUPV field to a new value. */
00509 #define BW_CAN_MCR_SUPV(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SUPV), v))
00510 /*@}*/
00511 
00512 /*!
00513  * @name Register CAN_MCR, field FRZACK[24] (RO)
00514  *
00515  * This read-only bit indicates that FlexCAN is in Freeze mode and its prescaler
00516  * is stopped. The Freeze mode request cannot be granted until current
00517  * transmission or reception processes have finished. Therefore the software can poll the
00518  * FRZACK bit to know when FlexCAN has actually entered Freeze mode. If Freeze
00519  * Mode request is negated, then this bit is negated after the FlexCAN prescaler is
00520  * running again. If Freeze mode is requested while FlexCAN is in a low power
00521  * mode, then the FRZACK bit will be set only when the low-power mode is exited.
00522  * See Section "Freeze Mode". FRZACK will be asserted within 178 CAN bits from the
00523  * freeze mode request by the CPU, and negated within 2 CAN bits after the freeze
00524  * mode request removal (see Section "Protocol Timing").
00525  *
00526  * Values:
00527  * - 0 - FlexCAN not in Freeze mode, prescaler running.
00528  * - 1 - FlexCAN in Freeze mode, prescaler stopped.
00529  */
00530 /*@{*/
00531 #define BP_CAN_MCR_FRZACK    (24U)         /*!< Bit position for CAN_MCR_FRZACK. */
00532 #define BM_CAN_MCR_FRZACK    (0x01000000U) /*!< Bit mask for CAN_MCR_FRZACK. */
00533 #define BS_CAN_MCR_FRZACK    (1U)          /*!< Bit field size in bits for CAN_MCR_FRZACK. */
00534 
00535 /*! @brief Read current value of the CAN_MCR_FRZACK field. */
00536 #define BR_CAN_MCR_FRZACK(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_FRZACK)))
00537 /*@}*/
00538 
00539 /*!
00540  * @name Register CAN_MCR, field SOFTRST[25] (RW)
00541  *
00542  * When this bit is asserted, FlexCAN resets its internal state machines and
00543  * some of the memory mapped registers. The following registers are reset: MCR
00544  * (except the MDIS bit), TIMER , ECR, ESR1, ESR2, IMASK1, IMASK2, IFLAG1, IFLAG2 and
00545  * CRCR. Configuration registers that control the interface to the CAN bus are
00546  * not affected by soft reset. The following registers are unaffected: CTRL1,
00547  * CTRL2, all RXIMR registers, RXMGMASK, RX14MASK, RX15MASK, RXFGMASK, RXFIR, all
00548  * Message Buffers . The SOFTRST bit can be asserted directly by the CPU when it
00549  * writes to the MCR Register, but it is also asserted when global soft reset is
00550  * requested at MCU level . Because soft reset is synchronous and has to follow a
00551  * request/acknowledge procedure across clock domains, it may take some time to
00552  * fully propagate its effect. The SOFTRST bit remains asserted while reset is
00553  * pending, and is automatically negated when reset completes. Therefore, software can
00554  * poll this bit to know when the soft reset has completed. Soft reset cannot be
00555  * applied while clocks are shut down in a low power mode. The module should be
00556  * first removed from low power mode, and then soft reset can be applied.
00557  *
00558  * Values:
00559  * - 0 - No reset request.
00560  * - 1 - Resets the registers affected by soft reset.
00561  */
00562 /*@{*/
00563 #define BP_CAN_MCR_SOFTRST   (25U)         /*!< Bit position for CAN_MCR_SOFTRST. */
00564 #define BM_CAN_MCR_SOFTRST   (0x02000000U) /*!< Bit mask for CAN_MCR_SOFTRST. */
00565 #define BS_CAN_MCR_SOFTRST   (1U)          /*!< Bit field size in bits for CAN_MCR_SOFTRST. */
00566 
00567 /*! @brief Read current value of the CAN_MCR_SOFTRST field. */
00568 #define BR_CAN_MCR_SOFTRST(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SOFTRST)))
00569 
00570 /*! @brief Format value for bitfield CAN_MCR_SOFTRST. */
00571 #define BF_CAN_MCR_SOFTRST(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_SOFTRST) & BM_CAN_MCR_SOFTRST)
00572 
00573 /*! @brief Set the SOFTRST field to a new value. */
00574 #define BW_CAN_MCR_SOFTRST(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SOFTRST), v))
00575 /*@}*/
00576 
00577 /*!
00578  * @name Register CAN_MCR, field WAKMSK[26] (RW)
00579  *
00580  * This bit enables the Wake Up Interrupt generation under Self Wake Up
00581  * mechanism.
00582  *
00583  * Values:
00584  * - 0 - Wake Up Interrupt is disabled.
00585  * - 1 - Wake Up Interrupt is enabled.
00586  */
00587 /*@{*/
00588 #define BP_CAN_MCR_WAKMSK    (26U)         /*!< Bit position for CAN_MCR_WAKMSK. */
00589 #define BM_CAN_MCR_WAKMSK    (0x04000000U) /*!< Bit mask for CAN_MCR_WAKMSK. */
00590 #define BS_CAN_MCR_WAKMSK    (1U)          /*!< Bit field size in bits for CAN_MCR_WAKMSK. */
00591 
00592 /*! @brief Read current value of the CAN_MCR_WAKMSK field. */
00593 #define BR_CAN_MCR_WAKMSK(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WAKMSK)))
00594 
00595 /*! @brief Format value for bitfield CAN_MCR_WAKMSK. */
00596 #define BF_CAN_MCR_WAKMSK(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_WAKMSK) & BM_CAN_MCR_WAKMSK)
00597 
00598 /*! @brief Set the WAKMSK field to a new value. */
00599 #define BW_CAN_MCR_WAKMSK(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WAKMSK), v))
00600 /*@}*/
00601 
00602 /*!
00603  * @name Register CAN_MCR, field NOTRDY[27] (RO)
00604  *
00605  * This read-only bit indicates that FlexCAN is either in Disable mode , Stop
00606  * mode or Freeze mode. It is negated once FlexCAN has exited these modes.
00607  *
00608  * Values:
00609  * - 0 - FlexCAN module is either in Normal mode, Listen-Only mode or Loop-Back
00610  *     mode.
00611  * - 1 - FlexCAN module is either in Disable mode , Stop mode or Freeze mode.
00612  */
00613 /*@{*/
00614 #define BP_CAN_MCR_NOTRDY    (27U)         /*!< Bit position for CAN_MCR_NOTRDY. */
00615 #define BM_CAN_MCR_NOTRDY    (0x08000000U) /*!< Bit mask for CAN_MCR_NOTRDY. */
00616 #define BS_CAN_MCR_NOTRDY    (1U)          /*!< Bit field size in bits for CAN_MCR_NOTRDY. */
00617 
00618 /*! @brief Read current value of the CAN_MCR_NOTRDY field. */
00619 #define BR_CAN_MCR_NOTRDY(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_NOTRDY)))
00620 /*@}*/
00621 
00622 /*!
00623  * @name Register CAN_MCR, field HALT[28] (RW)
00624  *
00625  * Assertion of this bit puts the FlexCAN module into Freeze mode. The CPU
00626  * should clear it after initializing the Message Buffers and Control Register. No
00627  * reception or transmission is performed by FlexCAN before this bit is cleared.
00628  * Freeze mode cannot be entered while FlexCAN is in a low power mode.
00629  *
00630  * Values:
00631  * - 0 - No Freeze mode request.
00632  * - 1 - Enters Freeze mode if the FRZ bit is asserted.
00633  */
00634 /*@{*/
00635 #define BP_CAN_MCR_HALT      (28U)         /*!< Bit position for CAN_MCR_HALT. */
00636 #define BM_CAN_MCR_HALT      (0x10000000U) /*!< Bit mask for CAN_MCR_HALT. */
00637 #define BS_CAN_MCR_HALT      (1U)          /*!< Bit field size in bits for CAN_MCR_HALT. */
00638 
00639 /*! @brief Read current value of the CAN_MCR_HALT field. */
00640 #define BR_CAN_MCR_HALT(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_HALT)))
00641 
00642 /*! @brief Format value for bitfield CAN_MCR_HALT. */
00643 #define BF_CAN_MCR_HALT(v)   ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_HALT) & BM_CAN_MCR_HALT)
00644 
00645 /*! @brief Set the HALT field to a new value. */
00646 #define BW_CAN_MCR_HALT(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_HALT), v))
00647 /*@}*/
00648 
00649 /*!
00650  * @name Register CAN_MCR, field RFEN[29] (RW)
00651  *
00652  * This bit controls whether the Rx FIFO feature is enabled or not. When RFEN is
00653  * set, MBs 0 to 5 cannot be used for normal reception and transmission because
00654  * the corresponding memory region (0x80-0xDC) is used by the FIFO engine as well
00655  * as additional MBs (up to 32, depending on CTRL2[RFFN] setting) which are used
00656  * as Rx FIFO ID Filter Table elements. RFEN also impacts the definition of the
00657  * minimum number of peripheral clocks per CAN bit as described in the table
00658  * "Minimum Ratio Between Peripheral Clock Frequency and CAN Bit Rate" (in section
00659  * "Arbitration and Matching Timing"). This bit can be written only in Freeze mode
00660  * because it is blocked by hardware in other modes.
00661  *
00662  * Values:
00663  * - 0 - Rx FIFO not enabled.
00664  * - 1 - Rx FIFO enabled.
00665  */
00666 /*@{*/
00667 #define BP_CAN_MCR_RFEN      (29U)         /*!< Bit position for CAN_MCR_RFEN. */
00668 #define BM_CAN_MCR_RFEN      (0x20000000U) /*!< Bit mask for CAN_MCR_RFEN. */
00669 #define BS_CAN_MCR_RFEN      (1U)          /*!< Bit field size in bits for CAN_MCR_RFEN. */
00670 
00671 /*! @brief Read current value of the CAN_MCR_RFEN field. */
00672 #define BR_CAN_MCR_RFEN(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_RFEN)))
00673 
00674 /*! @brief Format value for bitfield CAN_MCR_RFEN. */
00675 #define BF_CAN_MCR_RFEN(v)   ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_RFEN) & BM_CAN_MCR_RFEN)
00676 
00677 /*! @brief Set the RFEN field to a new value. */
00678 #define BW_CAN_MCR_RFEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_RFEN), v))
00679 /*@}*/
00680 
00681 /*!
00682  * @name Register CAN_MCR, field FRZ[30] (RW)
00683  *
00684  * The FRZ bit specifies the FlexCAN behavior when the HALT bit in the MCR
00685  * Register is set or when Debug mode is requested at MCU level . When FRZ is
00686  * asserted, FlexCAN is enabled to enter Freeze mode. Negation of this bit field causes
00687  * FlexCAN to exit from Freeze mode.
00688  *
00689  * Values:
00690  * - 0 - Not enabled to enter Freeze mode.
00691  * - 1 - Enabled to enter Freeze mode.
00692  */
00693 /*@{*/
00694 #define BP_CAN_MCR_FRZ       (30U)         /*!< Bit position for CAN_MCR_FRZ. */
00695 #define BM_CAN_MCR_FRZ       (0x40000000U) /*!< Bit mask for CAN_MCR_FRZ. */
00696 #define BS_CAN_MCR_FRZ       (1U)          /*!< Bit field size in bits for CAN_MCR_FRZ. */
00697 
00698 /*! @brief Read current value of the CAN_MCR_FRZ field. */
00699 #define BR_CAN_MCR_FRZ(x)    (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_FRZ)))
00700 
00701 /*! @brief Format value for bitfield CAN_MCR_FRZ. */
00702 #define BF_CAN_MCR_FRZ(v)    ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_FRZ) & BM_CAN_MCR_FRZ)
00703 
00704 /*! @brief Set the FRZ field to a new value. */
00705 #define BW_CAN_MCR_FRZ(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_FRZ), v))
00706 /*@}*/
00707 
00708 /*!
00709  * @name Register CAN_MCR, field MDIS[31] (RW)
00710  *
00711  * This bit controls whether FlexCAN is enabled or not. When disabled, FlexCAN
00712  * disables the clocks to the CAN Protocol Engine and Controller Host Interface
00713  * sub-modules. This is the only bit within this register not affected by soft
00714  * reset.
00715  *
00716  * Values:
00717  * - 0 - Enable the FlexCAN module.
00718  * - 1 - Disable the FlexCAN module.
00719  */
00720 /*@{*/
00721 #define BP_CAN_MCR_MDIS      (31U)         /*!< Bit position for CAN_MCR_MDIS. */
00722 #define BM_CAN_MCR_MDIS      (0x80000000U) /*!< Bit mask for CAN_MCR_MDIS. */
00723 #define BS_CAN_MCR_MDIS      (1U)          /*!< Bit field size in bits for CAN_MCR_MDIS. */
00724 
00725 /*! @brief Read current value of the CAN_MCR_MDIS field. */
00726 #define BR_CAN_MCR_MDIS(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_MDIS)))
00727 
00728 /*! @brief Format value for bitfield CAN_MCR_MDIS. */
00729 #define BF_CAN_MCR_MDIS(v)   ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_MDIS) & BM_CAN_MCR_MDIS)
00730 
00731 /*! @brief Set the MDIS field to a new value. */
00732 #define BW_CAN_MCR_MDIS(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_MDIS), v))
00733 /*@}*/
00734 
00735 /*******************************************************************************
00736  * HW_CAN_CTRL1 - Control 1 register
00737  ******************************************************************************/
00738 
00739 /*!
00740  * @brief HW_CAN_CTRL1 - Control 1 register (RW)
00741  *
00742  * Reset value: 0x00000000U
00743  *
00744  * This register is defined for specific FlexCAN control features related to the
00745  * CAN bus, such as bit-rate, programmable sampling point within an Rx bit, Loop
00746  * Back mode, Listen-Only mode, Bus Off recovery behavior and interrupt enabling
00747  * (Bus-Off, Error, Warning). It also determines the Division Factor for the
00748  * clock prescaler.
00749  */
00750 typedef union _hw_can_ctrl1
00751 {
00752     uint32_t U;
00753     struct _hw_can_ctrl1_bitfields
00754     {
00755         uint32_t PROPSEG : 3;          /*!< [2:0] Propagation Segment */
00756         uint32_t LOM : 1;              /*!< [3] Listen-Only Mode */
00757         uint32_t LBUF : 1;             /*!< [4] Lowest Buffer Transmitted First */
00758         uint32_t TSYN : 1;             /*!< [5] Timer Sync */
00759         uint32_t BOFFREC : 1;          /*!< [6] Bus Off Recovery */
00760         uint32_t SMP : 1;              /*!< [7] CAN Bit Sampling */
00761         uint32_t RESERVED0 : 2;        /*!< [9:8]  */
00762         uint32_t RWRNMSK : 1;          /*!< [10] Rx Warning Interrupt Mask */
00763         uint32_t TWRNMSK : 1;          /*!< [11] Tx Warning Interrupt Mask */
00764         uint32_t LPB : 1;              /*!< [12] Loop Back Mode */
00765         uint32_t CLKSRC : 1;           /*!< [13] CAN Engine Clock Source */
00766         uint32_t ERRMSK : 1;           /*!< [14] Error Mask */
00767         uint32_t BOFFMSK : 1;          /*!< [15] Bus Off Mask */
00768         uint32_t PSEG2 : 3;            /*!< [18:16] Phase Segment 2 */
00769         uint32_t PSEG1 : 3;            /*!< [21:19] Phase Segment 1 */
00770         uint32_t RJW : 2;              /*!< [23:22] Resync Jump Width */
00771         uint32_t PRESDIV : 8;          /*!< [31:24] Prescaler Division Factor */
00772     } B;
00773 } hw_can_ctrl1_t;
00774 
00775 /*!
00776  * @name Constants and macros for entire CAN_CTRL1 register
00777  */
00778 /*@{*/
00779 #define HW_CAN_CTRL1_ADDR(x)     ((x) + 0x4U)
00780 
00781 #define HW_CAN_CTRL1(x)          (*(__IO hw_can_ctrl1_t *) HW_CAN_CTRL1_ADDR(x))
00782 #define HW_CAN_CTRL1_RD(x)       (ADDRESS_READ(hw_can_ctrl1_t, HW_CAN_CTRL1_ADDR(x)))
00783 #define HW_CAN_CTRL1_WR(x, v)    (ADDRESS_WRITE(hw_can_ctrl1_t, HW_CAN_CTRL1_ADDR(x), v))
00784 #define HW_CAN_CTRL1_SET(x, v)   (HW_CAN_CTRL1_WR(x, HW_CAN_CTRL1_RD(x) |  (v)))
00785 #define HW_CAN_CTRL1_CLR(x, v)   (HW_CAN_CTRL1_WR(x, HW_CAN_CTRL1_RD(x) & ~(v)))
00786 #define HW_CAN_CTRL1_TOG(x, v)   (HW_CAN_CTRL1_WR(x, HW_CAN_CTRL1_RD(x) ^  (v)))
00787 /*@}*/
00788 
00789 /*
00790  * Constants & macros for individual CAN_CTRL1 bitfields
00791  */
00792 
00793 /*!
00794  * @name Register CAN_CTRL1, field PROPSEG[2:0] (RW)
00795  *
00796  * This 3-bit field defines the length of the Propagation Segment in the bit
00797  * time. The valid programmable values are 0-7. This field can be written only in
00798  * Freeze mode because it is blocked by hardware in other modes. Propagation
00799  * Segment Time = (PROPSEG + 1) * Time-Quanta. Time-Quantum = one Sclock period.
00800  */
00801 /*@{*/
00802 #define BP_CAN_CTRL1_PROPSEG (0U)          /*!< Bit position for CAN_CTRL1_PROPSEG. */
00803 #define BM_CAN_CTRL1_PROPSEG (0x00000007U) /*!< Bit mask for CAN_CTRL1_PROPSEG. */
00804 #define BS_CAN_CTRL1_PROPSEG (3U)          /*!< Bit field size in bits for CAN_CTRL1_PROPSEG. */
00805 
00806 /*! @brief Read current value of the CAN_CTRL1_PROPSEG field. */
00807 #define BR_CAN_CTRL1_PROPSEG(x) (UNION_READ(hw_can_ctrl1_t, HW_CAN_CTRL1_ADDR(x), U, B.PROPSEG))
00808 
00809 /*! @brief Format value for bitfield CAN_CTRL1_PROPSEG. */
00810 #define BF_CAN_CTRL1_PROPSEG(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_PROPSEG) & BM_CAN_CTRL1_PROPSEG)
00811 
00812 /*! @brief Set the PROPSEG field to a new value. */
00813 #define BW_CAN_CTRL1_PROPSEG(x, v) (HW_CAN_CTRL1_WR(x, (HW_CAN_CTRL1_RD(x) & ~BM_CAN_CTRL1_PROPSEG) | BF_CAN_CTRL1_PROPSEG(v)))
00814 /*@}*/
00815 
00816 /*!
00817  * @name Register CAN_CTRL1, field LOM[3] (RW)
00818  *
00819  * This bit configures FlexCAN to operate in Listen-Only mode. In this mode,
00820  * transmission is disabled, all error counters are frozen and the module operates
00821  * in a CAN Error Passive mode. Only messages acknowledged by another CAN station
00822  * will be received. If FlexCAN detects a message that has not been acknowledged,
00823  * it will flag a BIT0 error without changing the REC, as if it was trying to
00824  * acknowledge the message. Listen-Only mode acknowledgement can be obtained by the
00825  * state of ESR1[FLTCONF] field which is Passive Error when Listen-Only mode is
00826  * entered. There can be some delay between the Listen-Only mode request and
00827  * acknowledge. This bit can be written only in Freeze mode because it is blocked by
00828  * hardware in other modes.
00829  *
00830  * Values:
00831  * - 0 - Listen-Only mode is deactivated.
00832  * - 1 - FlexCAN module operates in Listen-Only mode.
00833  */
00834 /*@{*/
00835 #define BP_CAN_CTRL1_LOM     (3U)          /*!< Bit position for CAN_CTRL1_LOM. */
00836 #define BM_CAN_CTRL1_LOM     (0x00000008U) /*!< Bit mask for CAN_CTRL1_LOM. */
00837 #define BS_CAN_CTRL1_LOM     (1U)          /*!< Bit field size in bits for CAN_CTRL1_LOM. */
00838 
00839 /*! @brief Read current value of the CAN_CTRL1_LOM field. */
00840 #define BR_CAN_CTRL1_LOM(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LOM)))
00841 
00842 /*! @brief Format value for bitfield CAN_CTRL1_LOM. */
00843 #define BF_CAN_CTRL1_LOM(v)  ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_LOM) & BM_CAN_CTRL1_LOM)
00844 
00845 /*! @brief Set the LOM field to a new value. */
00846 #define BW_CAN_CTRL1_LOM(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LOM), v))
00847 /*@}*/
00848 
00849 /*!
00850  * @name Register CAN_CTRL1, field LBUF[4] (RW)
00851  *
00852  * This bit defines the ordering mechanism for Message Buffer transmission. When
00853  * asserted, the LPRIOEN bit does not affect the priority arbitration. This bit
00854  * can be written only in Freeze mode because it is blocked by hardware in other
00855  * modes.
00856  *
00857  * Values:
00858  * - 0 - Buffer with highest priority is transmitted first.
00859  * - 1 - Lowest number buffer is transmitted first.
00860  */
00861 /*@{*/
00862 #define BP_CAN_CTRL1_LBUF    (4U)          /*!< Bit position for CAN_CTRL1_LBUF. */
00863 #define BM_CAN_CTRL1_LBUF    (0x00000010U) /*!< Bit mask for CAN_CTRL1_LBUF. */
00864 #define BS_CAN_CTRL1_LBUF    (1U)          /*!< Bit field size in bits for CAN_CTRL1_LBUF. */
00865 
00866 /*! @brief Read current value of the CAN_CTRL1_LBUF field. */
00867 #define BR_CAN_CTRL1_LBUF(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LBUF)))
00868 
00869 /*! @brief Format value for bitfield CAN_CTRL1_LBUF. */
00870 #define BF_CAN_CTRL1_LBUF(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_LBUF) & BM_CAN_CTRL1_LBUF)
00871 
00872 /*! @brief Set the LBUF field to a new value. */
00873 #define BW_CAN_CTRL1_LBUF(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LBUF), v))
00874 /*@}*/
00875 
00876 /*!
00877  * @name Register CAN_CTRL1, field TSYN[5] (RW)
00878  *
00879  * This bit enables a mechanism that resets the free-running timer each time a
00880  * message is received in Message Buffer 0. This feature provides means to
00881  * synchronize multiple FlexCAN stations with a special "SYNC" message, that is, global
00882  * network time. If the RFEN bit in MCR is set (Rx FIFO enabled), the first
00883  * available Mailbox, according to CTRL2[RFFN] setting, is used for timer
00884  * synchronization instead of MB0. This bit can be written only in Freeze mode because it is
00885  * blocked by hardware in other modes.
00886  *
00887  * Values:
00888  * - 0 - Timer Sync feature disabled
00889  * - 1 - Timer Sync feature enabled
00890  */
00891 /*@{*/
00892 #define BP_CAN_CTRL1_TSYN    (5U)          /*!< Bit position for CAN_CTRL1_TSYN. */
00893 #define BM_CAN_CTRL1_TSYN    (0x00000020U) /*!< Bit mask for CAN_CTRL1_TSYN. */
00894 #define BS_CAN_CTRL1_TSYN    (1U)          /*!< Bit field size in bits for CAN_CTRL1_TSYN. */
00895 
00896 /*! @brief Read current value of the CAN_CTRL1_TSYN field. */
00897 #define BR_CAN_CTRL1_TSYN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_TSYN)))
00898 
00899 /*! @brief Format value for bitfield CAN_CTRL1_TSYN. */
00900 #define BF_CAN_CTRL1_TSYN(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_TSYN) & BM_CAN_CTRL1_TSYN)
00901 
00902 /*! @brief Set the TSYN field to a new value. */
00903 #define BW_CAN_CTRL1_TSYN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_TSYN), v))
00904 /*@}*/
00905 
00906 /*!
00907  * @name Register CAN_CTRL1, field BOFFREC[6] (RW)
00908  *
00909  * This bit defines how FlexCAN recovers from Bus Off state. If this bit is
00910  * negated, automatic recovering from Bus Off state occurs according to the CAN
00911  * Specification 2.0B. If the bit is asserted, automatic recovering from Bus Off is
00912  * disabled and the module remains in Bus Off state until the bit is negated by the
00913  * user. If the negation occurs before 128 sequences of 11 recessive bits are
00914  * detected on the CAN bus, then Bus Off recovery happens as if the BOFFREC bit had
00915  * never been asserted. If the negation occurs after 128 sequences of 11
00916  * recessive bits occurred, then FlexCAN will re-synchronize to the bus by waiting for
00917  * 11 recessive bits before joining the bus. After negation, the BOFFREC bit can
00918  * be re-asserted again during Bus Off, but it will be effective only the next
00919  * time the module enters Bus Off. If BOFFREC was negated when the module entered
00920  * Bus Off, asserting it during Bus Off will not be effective for the current Bus
00921  * Off recovery.
00922  *
00923  * Values:
00924  * - 0 - Automatic recovering from Bus Off state enabled, according to CAN Spec
00925  *     2.0 part B.
00926  * - 1 - Automatic recovering from Bus Off state disabled.
00927  */
00928 /*@{*/
00929 #define BP_CAN_CTRL1_BOFFREC (6U)          /*!< Bit position for CAN_CTRL1_BOFFREC. */
00930 #define BM_CAN_CTRL1_BOFFREC (0x00000040U) /*!< Bit mask for CAN_CTRL1_BOFFREC. */
00931 #define BS_CAN_CTRL1_BOFFREC (1U)          /*!< Bit field size in bits for CAN_CTRL1_BOFFREC. */
00932 
00933 /*! @brief Read current value of the CAN_CTRL1_BOFFREC field. */
00934 #define BR_CAN_CTRL1_BOFFREC(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_BOFFREC)))
00935 
00936 /*! @brief Format value for bitfield CAN_CTRL1_BOFFREC. */
00937 #define BF_CAN_CTRL1_BOFFREC(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_BOFFREC) & BM_CAN_CTRL1_BOFFREC)
00938 
00939 /*! @brief Set the BOFFREC field to a new value. */
00940 #define BW_CAN_CTRL1_BOFFREC(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_BOFFREC), v))
00941 /*@}*/
00942 
00943 /*!
00944  * @name Register CAN_CTRL1, field SMP[7] (RW)
00945  *
00946  * This bit defines the sampling mode of CAN bits at the Rx input. This bit can
00947  * be written only in Freeze mode because it is blocked by hardware in other
00948  * modes.
00949  *
00950  * Values:
00951  * - 0 - Just one sample is used to determine the bit value.
00952  * - 1 - Three samples are used to determine the value of the received bit: the
00953  *     regular one (sample point) and 2 preceding samples; a majority rule is
00954  *     used.
00955  */
00956 /*@{*/
00957 #define BP_CAN_CTRL1_SMP     (7U)          /*!< Bit position for CAN_CTRL1_SMP. */
00958 #define BM_CAN_CTRL1_SMP     (0x00000080U) /*!< Bit mask for CAN_CTRL1_SMP. */
00959 #define BS_CAN_CTRL1_SMP     (1U)          /*!< Bit field size in bits for CAN_CTRL1_SMP. */
00960 
00961 /*! @brief Read current value of the CAN_CTRL1_SMP field. */
00962 #define BR_CAN_CTRL1_SMP(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_SMP)))
00963 
00964 /*! @brief Format value for bitfield CAN_CTRL1_SMP. */
00965 #define BF_CAN_CTRL1_SMP(v)  ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_SMP) & BM_CAN_CTRL1_SMP)
00966 
00967 /*! @brief Set the SMP field to a new value. */
00968 #define BW_CAN_CTRL1_SMP(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_SMP), v))
00969 /*@}*/
00970 
00971 /*!
00972  * @name Register CAN_CTRL1, field RWRNMSK[10] (RW)
00973  *
00974  * This bit provides a mask for the Rx Warning Interrupt associated with the
00975  * RWRNINT flag in the Error and Status Register. This bit is read as zero when
00976  * MCR[WRNEN] bit is negated. This bit can be written only if MCR[WRNEN] bit is
00977  * asserted.
00978  *
00979  * Values:
00980  * - 0 - Rx Warning Interrupt disabled.
00981  * - 1 - Rx Warning Interrupt enabled.
00982  */
00983 /*@{*/
00984 #define BP_CAN_CTRL1_RWRNMSK (10U)         /*!< Bit position for CAN_CTRL1_RWRNMSK. */
00985 #define BM_CAN_CTRL1_RWRNMSK (0x00000400U) /*!< Bit mask for CAN_CTRL1_RWRNMSK. */
00986 #define BS_CAN_CTRL1_RWRNMSK (1U)          /*!< Bit field size in bits for CAN_CTRL1_RWRNMSK. */
00987 
00988 /*! @brief Read current value of the CAN_CTRL1_RWRNMSK field. */
00989 #define BR_CAN_CTRL1_RWRNMSK(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_RWRNMSK)))
00990 
00991 /*! @brief Format value for bitfield CAN_CTRL1_RWRNMSK. */
00992 #define BF_CAN_CTRL1_RWRNMSK(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_RWRNMSK) & BM_CAN_CTRL1_RWRNMSK)
00993 
00994 /*! @brief Set the RWRNMSK field to a new value. */
00995 #define BW_CAN_CTRL1_RWRNMSK(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_RWRNMSK), v))
00996 /*@}*/
00997 
00998 /*!
00999  * @name Register CAN_CTRL1, field TWRNMSK[11] (RW)
01000  *
01001  * This bit provides a mask for the Tx Warning Interrupt associated with the
01002  * TWRNINT flag in the Error and Status Register. This bit is read as zero when
01003  * MCR[WRNEN] bit is negated. This bit can be written only if MCR[WRNEN] bit is
01004  * asserted.
01005  *
01006  * Values:
01007  * - 0 - Tx Warning Interrupt disabled.
01008  * - 1 - Tx Warning Interrupt enabled.
01009  */
01010 /*@{*/
01011 #define BP_CAN_CTRL1_TWRNMSK (11U)         /*!< Bit position for CAN_CTRL1_TWRNMSK. */
01012 #define BM_CAN_CTRL1_TWRNMSK (0x00000800U) /*!< Bit mask for CAN_CTRL1_TWRNMSK. */
01013 #define BS_CAN_CTRL1_TWRNMSK (1U)          /*!< Bit field size in bits for CAN_CTRL1_TWRNMSK. */
01014 
01015 /*! @brief Read current value of the CAN_CTRL1_TWRNMSK field. */
01016 #define BR_CAN_CTRL1_TWRNMSK(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_TWRNMSK)))
01017 
01018 /*! @brief Format value for bitfield CAN_CTRL1_TWRNMSK. */
01019 #define BF_CAN_CTRL1_TWRNMSK(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_TWRNMSK) & BM_CAN_CTRL1_TWRNMSK)
01020 
01021 /*! @brief Set the TWRNMSK field to a new value. */
01022 #define BW_CAN_CTRL1_TWRNMSK(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_TWRNMSK), v))
01023 /*@}*/
01024 
01025 /*!
01026  * @name Register CAN_CTRL1, field LPB[12] (RW)
01027  *
01028  * This bit configures FlexCAN to operate in Loop-Back mode. In this mode,
01029  * FlexCAN performs an internal loop back that can be used for self test operation.
01030  * The bit stream output of the transmitter is fed back internally to the receiver
01031  * input. The Rx CAN input pin is ignored and the Tx CAN output goes to the
01032  * recessive state (logic 1). FlexCAN behaves as it normally does when transmitting,
01033  * and treats its own transmitted message as a message received from a remote
01034  * node. In this mode, FlexCAN ignores the bit sent during the ACK slot in the CAN
01035  * frame acknowledge field, generating an internal acknowledge bit to ensure proper
01036  * reception of its own message. Both transmit and receive interrupts are
01037  * generated. This bit can be written only in Freeze mode because it is blocked by
01038  * hardware in other modes. In this mode, the MCR[SRXDIS] cannot be asserted because
01039  * this will impede the self reception of a transmitted message.
01040  *
01041  * Values:
01042  * - 0 - Loop Back disabled.
01043  * - 1 - Loop Back enabled.
01044  */
01045 /*@{*/
01046 #define BP_CAN_CTRL1_LPB     (12U)         /*!< Bit position for CAN_CTRL1_LPB. */
01047 #define BM_CAN_CTRL1_LPB     (0x00001000U) /*!< Bit mask for CAN_CTRL1_LPB. */
01048 #define BS_CAN_CTRL1_LPB     (1U)          /*!< Bit field size in bits for CAN_CTRL1_LPB. */
01049 
01050 /*! @brief Read current value of the CAN_CTRL1_LPB field. */
01051 #define BR_CAN_CTRL1_LPB(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LPB)))
01052 
01053 /*! @brief Format value for bitfield CAN_CTRL1_LPB. */
01054 #define BF_CAN_CTRL1_LPB(v)  ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_LPB) & BM_CAN_CTRL1_LPB)
01055 
01056 /*! @brief Set the LPB field to a new value. */
01057 #define BW_CAN_CTRL1_LPB(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LPB), v))
01058 /*@}*/
01059 
01060 /*!
01061  * @name Register CAN_CTRL1, field CLKSRC[13] (RW)
01062  *
01063  * This bit selects the clock source to the CAN Protocol Engine (PE) to be
01064  * either the peripheral clock (driven by the PLL) or the crystal oscillator clock.
01065  * The selected clock is the one fed to the prescaler to generate the Serial Clock
01066  * (Sclock). In order to guarantee reliable operation, this bit can be written
01067  * only in Disable mode because it is blocked by hardware in other modes. See
01068  * Section "Protocol Timing".
01069  *
01070  * Values:
01071  * - 0 - The CAN engine clock source is the oscillator clock. Under this
01072  *     condition, the oscillator clock frequency must be lower than the bus clock.
01073  * - 1 - The CAN engine clock source is the peripheral clock.
01074  */
01075 /*@{*/
01076 #define BP_CAN_CTRL1_CLKSRC  (13U)         /*!< Bit position for CAN_CTRL1_CLKSRC. */
01077 #define BM_CAN_CTRL1_CLKSRC  (0x00002000U) /*!< Bit mask for CAN_CTRL1_CLKSRC. */
01078 #define BS_CAN_CTRL1_CLKSRC  (1U)          /*!< Bit field size in bits for CAN_CTRL1_CLKSRC. */
01079 
01080 /*! @brief Read current value of the CAN_CTRL1_CLKSRC field. */
01081 #define BR_CAN_CTRL1_CLKSRC(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_CLKSRC)))
01082 
01083 /*! @brief Format value for bitfield CAN_CTRL1_CLKSRC. */
01084 #define BF_CAN_CTRL1_CLKSRC(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_CLKSRC) & BM_CAN_CTRL1_CLKSRC)
01085 
01086 /*! @brief Set the CLKSRC field to a new value. */
01087 #define BW_CAN_CTRL1_CLKSRC(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_CLKSRC), v))
01088 /*@}*/
01089 
01090 /*!
01091  * @name Register CAN_CTRL1, field ERRMSK[14] (RW)
01092  *
01093  * This bit provides a mask for the Error Interrupt.
01094  *
01095  * Values:
01096  * - 0 - Error interrupt disabled.
01097  * - 1 - Error interrupt enabled.
01098  */
01099 /*@{*/
01100 #define BP_CAN_CTRL1_ERRMSK  (14U)         /*!< Bit position for CAN_CTRL1_ERRMSK. */
01101 #define BM_CAN_CTRL1_ERRMSK  (0x00004000U) /*!< Bit mask for CAN_CTRL1_ERRMSK. */
01102 #define BS_CAN_CTRL1_ERRMSK  (1U)          /*!< Bit field size in bits for CAN_CTRL1_ERRMSK. */
01103 
01104 /*! @brief Read current value of the CAN_CTRL1_ERRMSK field. */
01105 #define BR_CAN_CTRL1_ERRMSK(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_ERRMSK)))
01106 
01107 /*! @brief Format value for bitfield CAN_CTRL1_ERRMSK. */
01108 #define BF_CAN_CTRL1_ERRMSK(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_ERRMSK) & BM_CAN_CTRL1_ERRMSK)
01109 
01110 /*! @brief Set the ERRMSK field to a new value. */
01111 #define BW_CAN_CTRL1_ERRMSK(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_ERRMSK), v))
01112 /*@}*/
01113 
01114 /*!
01115  * @name Register CAN_CTRL1, field BOFFMSK[15] (RW)
01116  *
01117  * This bit provides a mask for the Bus Off Interrupt.
01118  *
01119  * Values:
01120  * - 0 - Bus Off interrupt disabled.
01121  * - 1 - Bus Off interrupt enabled.
01122  */
01123 /*@{*/
01124 #define BP_CAN_CTRL1_BOFFMSK (15U)         /*!< Bit position for CAN_CTRL1_BOFFMSK. */
01125 #define BM_CAN_CTRL1_BOFFMSK (0x00008000U) /*!< Bit mask for CAN_CTRL1_BOFFMSK. */
01126 #define BS_CAN_CTRL1_BOFFMSK (1U)          /*!< Bit field size in bits for CAN_CTRL1_BOFFMSK. */
01127 
01128 /*! @brief Read current value of the CAN_CTRL1_BOFFMSK field. */
01129 #define BR_CAN_CTRL1_BOFFMSK(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_BOFFMSK)))
01130 
01131 /*! @brief Format value for bitfield CAN_CTRL1_BOFFMSK. */
01132 #define BF_CAN_CTRL1_BOFFMSK(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_BOFFMSK) & BM_CAN_CTRL1_BOFFMSK)
01133 
01134 /*! @brief Set the BOFFMSK field to a new value. */
01135 #define BW_CAN_CTRL1_BOFFMSK(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_BOFFMSK), v))
01136 /*@}*/
01137 
01138 /*!
01139  * @name Register CAN_CTRL1, field PSEG2[18:16] (RW)
01140  *
01141  * This 3-bit field defines the length of Phase Buffer Segment 2 in the bit
01142  * time. The valid programmable values are 1-7. This field can be written only in
01143  * Freeze mode because it is blocked by hardware in other modes. Phase Buffer
01144  * Segment 2 = (PSEG2 + 1) * Time-Quanta.
01145  */
01146 /*@{*/
01147 #define BP_CAN_CTRL1_PSEG2   (16U)         /*!< Bit position for CAN_CTRL1_PSEG2. */
01148 #define BM_CAN_CTRL1_PSEG2   (0x00070000U) /*!< Bit mask for CAN_CTRL1_PSEG2. */
01149 #define BS_CAN_CTRL1_PSEG2   (3U)          /*!< Bit field size in bits for CAN_CTRL1_PSEG2. */
01150 
01151 /*! @brief Read current value of the CAN_CTRL1_PSEG2 field. */
01152 #define BR_CAN_CTRL1_PSEG2(x) (UNION_READ(hw_can_ctrl1_t, HW_CAN_CTRL1_ADDR(x), U, B.PSEG2))
01153 
01154 /*! @brief Format value for bitfield CAN_CTRL1_PSEG2. */
01155 #define BF_CAN_CTRL1_PSEG2(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_PSEG2) & BM_CAN_CTRL1_PSEG2)
01156 
01157 /*! @brief Set the PSEG2 field to a new value. */
01158 #define BW_CAN_CTRL1_PSEG2(x, v) (HW_CAN_CTRL1_WR(x, (HW_CAN_CTRL1_RD(x) & ~BM_CAN_CTRL1_PSEG2) | BF_CAN_CTRL1_PSEG2(v)))
01159 /*@}*/
01160 
01161 /*!
01162  * @name Register CAN_CTRL1, field PSEG1[21:19] (RW)
01163  *
01164  * This 3-bit field defines the length of Phase Buffer Segment 1 in the bit
01165  * time. The valid programmable values are 0-7. This field can be written only in
01166  * Freeze mode because it is blocked by hardware in other modes. Phase Buffer
01167  * Segment 1 = (PSEG1 + 1) * Time-Quanta.
01168  */
01169 /*@{*/
01170 #define BP_CAN_CTRL1_PSEG1   (19U)         /*!< Bit position for CAN_CTRL1_PSEG1. */
01171 #define BM_CAN_CTRL1_PSEG1   (0x00380000U) /*!< Bit mask for CAN_CTRL1_PSEG1. */
01172 #define BS_CAN_CTRL1_PSEG1   (3U)          /*!< Bit field size in bits for CAN_CTRL1_PSEG1. */
01173 
01174 /*! @brief Read current value of the CAN_CTRL1_PSEG1 field. */
01175 #define BR_CAN_CTRL1_PSEG1(x) (UNION_READ(hw_can_ctrl1_t, HW_CAN_CTRL1_ADDR(x), U, B.PSEG1))
01176 
01177 /*! @brief Format value for bitfield CAN_CTRL1_PSEG1. */
01178 #define BF_CAN_CTRL1_PSEG1(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_PSEG1) & BM_CAN_CTRL1_PSEG1)
01179 
01180 /*! @brief Set the PSEG1 field to a new value. */
01181 #define BW_CAN_CTRL1_PSEG1(x, v) (HW_CAN_CTRL1_WR(x, (HW_CAN_CTRL1_RD(x) & ~BM_CAN_CTRL1_PSEG1) | BF_CAN_CTRL1_PSEG1(v)))
01182 /*@}*/
01183 
01184 /*!
01185  * @name Register CAN_CTRL1, field RJW[23:22] (RW)
01186  *
01187  * This 2-bit field defines the maximum number of time quanta that a bit time
01188  * can be changed by one re-synchronization. One time quantum is equal to the
01189  * Sclock period. The valid programmable values are 0-3. This field can be written
01190  * only in Freeze mode because it is blocked by hardware in other modes. Resync Jump
01191  * Width = RJW + 1.
01192  */
01193 /*@{*/
01194 #define BP_CAN_CTRL1_RJW     (22U)         /*!< Bit position for CAN_CTRL1_RJW. */
01195 #define BM_CAN_CTRL1_RJW     (0x00C00000U) /*!< Bit mask for CAN_CTRL1_RJW. */
01196 #define BS_CAN_CTRL1_RJW     (2U)          /*!< Bit field size in bits for CAN_CTRL1_RJW. */
01197 
01198 /*! @brief Read current value of the CAN_CTRL1_RJW field. */
01199 #define BR_CAN_CTRL1_RJW(x)  (UNION_READ(hw_can_ctrl1_t, HW_CAN_CTRL1_ADDR(x), U, B.RJW))
01200 
01201 /*! @brief Format value for bitfield CAN_CTRL1_RJW. */
01202 #define BF_CAN_CTRL1_RJW(v)  ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_RJW) & BM_CAN_CTRL1_RJW)
01203 
01204 /*! @brief Set the RJW field to a new value. */
01205 #define BW_CAN_CTRL1_RJW(x, v) (HW_CAN_CTRL1_WR(x, (HW_CAN_CTRL1_RD(x) & ~BM_CAN_CTRL1_RJW) | BF_CAN_CTRL1_RJW(v)))
01206 /*@}*/
01207 
01208 /*!
01209  * @name Register CAN_CTRL1, field PRESDIV[31:24] (RW)
01210  *
01211  * This 8-bit field defines the ratio between the PE clock frequency and the
01212  * Serial Clock (Sclock) frequency. The Sclock period defines the time quantum of
01213  * the CAN protocol. For the reset value, the Sclock frequency is equal to the PE
01214  * clock frequency. The Maximum value of this field is 0xFF, that gives a minimum
01215  * Sclock frequency equal to the PE clock frequency divided by 256. See Section
01216  * "Protocol Timing". This field can be written only in Freeze mode because it is
01217  * blocked by hardware in other modes. Sclock frequency = PE clock frequency /
01218  * (PRESDIV + 1)
01219  */
01220 /*@{*/
01221 #define BP_CAN_CTRL1_PRESDIV (24U)         /*!< Bit position for CAN_CTRL1_PRESDIV. */
01222 #define BM_CAN_CTRL1_PRESDIV (0xFF000000U) /*!< Bit mask for CAN_CTRL1_PRESDIV. */
01223 #define BS_CAN_CTRL1_PRESDIV (8U)          /*!< Bit field size in bits for CAN_CTRL1_PRESDIV. */
01224 
01225 /*! @brief Read current value of the CAN_CTRL1_PRESDIV field. */
01226 #define BR_CAN_CTRL1_PRESDIV(x) (UNION_READ(hw_can_ctrl1_t, HW_CAN_CTRL1_ADDR(x), U, B.PRESDIV))
01227 
01228 /*! @brief Format value for bitfield CAN_CTRL1_PRESDIV. */
01229 #define BF_CAN_CTRL1_PRESDIV(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_PRESDIV) & BM_CAN_CTRL1_PRESDIV)
01230 
01231 /*! @brief Set the PRESDIV field to a new value. */
01232 #define BW_CAN_CTRL1_PRESDIV(x, v) (HW_CAN_CTRL1_WR(x, (HW_CAN_CTRL1_RD(x) & ~BM_CAN_CTRL1_PRESDIV) | BF_CAN_CTRL1_PRESDIV(v)))
01233 /*@}*/
01234 
01235 /*******************************************************************************
01236  * HW_CAN_TIMER - Free Running Timer
01237  ******************************************************************************/
01238 
01239 /*!
01240  * @brief HW_CAN_TIMER - Free Running Timer (RW)
01241  *
01242  * Reset value: 0x00000000U
01243  *
01244  * This register represents a 16-bit free running counter that can be read and
01245  * written by the CPU. The timer starts from 0x0 after Reset, counts linearly to
01246  * 0xFFFF, and wraps around. The timer is clocked by the FlexCAN bit-clock, which
01247  * defines the baud rate on the CAN bus. During a message transmission/reception,
01248  * it increments by one for each bit that is received or transmitted. When there
01249  * is no message on the bus, it counts using the previously programmed baud
01250  * rate. The timer is not incremented during Disable , Stop, and Freeze modes. The
01251  * timer value is captured when the second bit of the identifier field of any frame
01252  * is on the CAN bus. This captured value is written into the Time Stamp entry
01253  * in a message buffer after a successful reception or transmission of a message.
01254  * If bit CTRL1[TSYN] is asserted, the Timer is reset whenever a message is
01255  * received in the first available Mailbox, according to CTRL2[RFFN] setting. The CPU
01256  * can write to this register anytime. However, if the write occurs at the same
01257  * time that the Timer is being reset by a reception in the first Mailbox, then
01258  * the write value is discarded. Reading this register affects the Mailbox
01259  * Unlocking procedure; see Section "Mailbox Lock Mechanism".
01260  */
01261 typedef union _hw_can_timer
01262 {
01263     uint32_t U;
01264     struct _hw_can_timer_bitfields
01265     {
01266         uint32_t TIMER : 16;           /*!< [15:0] Timer Value */
01267         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
01268     } B;
01269 } hw_can_timer_t;
01270 
01271 /*!
01272  * @name Constants and macros for entire CAN_TIMER register
01273  */
01274 /*@{*/
01275 #define HW_CAN_TIMER_ADDR(x)     ((x) + 0x8U)
01276 
01277 #define HW_CAN_TIMER(x)          (*(__IO hw_can_timer_t *) HW_CAN_TIMER_ADDR(x))
01278 #define HW_CAN_TIMER_RD(x)       (ADDRESS_READ(hw_can_timer_t, HW_CAN_TIMER_ADDR(x)))
01279 #define HW_CAN_TIMER_WR(x, v)    (ADDRESS_WRITE(hw_can_timer_t, HW_CAN_TIMER_ADDR(x), v))
01280 #define HW_CAN_TIMER_SET(x, v)   (HW_CAN_TIMER_WR(x, HW_CAN_TIMER_RD(x) |  (v)))
01281 #define HW_CAN_TIMER_CLR(x, v)   (HW_CAN_TIMER_WR(x, HW_CAN_TIMER_RD(x) & ~(v)))
01282 #define HW_CAN_TIMER_TOG(x, v)   (HW_CAN_TIMER_WR(x, HW_CAN_TIMER_RD(x) ^  (v)))
01283 /*@}*/
01284 
01285 /*
01286  * Constants & macros for individual CAN_TIMER bitfields
01287  */
01288 
01289 /*!
01290  * @name Register CAN_TIMER, field TIMER[15:0] (RW)
01291  *
01292  * Contains the free-running counter value.
01293  */
01294 /*@{*/
01295 #define BP_CAN_TIMER_TIMER   (0U)          /*!< Bit position for CAN_TIMER_TIMER. */
01296 #define BM_CAN_TIMER_TIMER   (0x0000FFFFU) /*!< Bit mask for CAN_TIMER_TIMER. */
01297 #define BS_CAN_TIMER_TIMER   (16U)         /*!< Bit field size in bits for CAN_TIMER_TIMER. */
01298 
01299 /*! @brief Read current value of the CAN_TIMER_TIMER field. */
01300 #define BR_CAN_TIMER_TIMER(x) (UNION_READ(hw_can_timer_t, HW_CAN_TIMER_ADDR(x), U, B.TIMER))
01301 
01302 /*! @brief Format value for bitfield CAN_TIMER_TIMER. */
01303 #define BF_CAN_TIMER_TIMER(v) ((uint32_t)((uint32_t)(v) << BP_CAN_TIMER_TIMER) & BM_CAN_TIMER_TIMER)
01304 
01305 /*! @brief Set the TIMER field to a new value. */
01306 #define BW_CAN_TIMER_TIMER(x, v) (HW_CAN_TIMER_WR(x, (HW_CAN_TIMER_RD(x) & ~BM_CAN_TIMER_TIMER) | BF_CAN_TIMER_TIMER(v)))
01307 /*@}*/
01308 
01309 /*******************************************************************************
01310  * HW_CAN_RXMGMASK - Rx Mailboxes Global Mask Register
01311  ******************************************************************************/
01312 
01313 /*!
01314  * @brief HW_CAN_RXMGMASK - Rx Mailboxes Global Mask Register (RW)
01315  *
01316  * Reset value: 0xFFFFFFFFU
01317  *
01318  * This register is located in RAM. RXMGMASK is provided for legacy application
01319  * support. When the MCR[IRMQ] bit is negated, RXMGMASK is always in effect. When
01320  * the MCR[IRMQ] bit is asserted, RXMGMASK has no effect. RXMGMASK is used to
01321  * mask the filter fields of all Rx MBs, excluding MBs 14-15, which have individual
01322  * mask registers. This register can only be written in Freeze mode as it is
01323  * blocked by hardware in other modes.
01324  */
01325 typedef union _hw_can_rxmgmask
01326 {
01327     uint32_t U;
01328     struct _hw_can_rxmgmask_bitfields
01329     {
01330         uint32_t MG : 32;              /*!< [31:0] Rx Mailboxes Global Mask Bits */
01331     } B;
01332 } hw_can_rxmgmask_t;
01333 
01334 /*!
01335  * @name Constants and macros for entire CAN_RXMGMASK register
01336  */
01337 /*@{*/
01338 #define HW_CAN_RXMGMASK_ADDR(x)  ((x) + 0x10U)
01339 
01340 #define HW_CAN_RXMGMASK(x)       (*(__IO hw_can_rxmgmask_t *) HW_CAN_RXMGMASK_ADDR(x))
01341 #define HW_CAN_RXMGMASK_RD(x)    (ADDRESS_READ(hw_can_rxmgmask_t, HW_CAN_RXMGMASK_ADDR(x)))
01342 #define HW_CAN_RXMGMASK_WR(x, v) (ADDRESS_WRITE(hw_can_rxmgmask_t, HW_CAN_RXMGMASK_ADDR(x), v))
01343 #define HW_CAN_RXMGMASK_SET(x, v) (HW_CAN_RXMGMASK_WR(x, HW_CAN_RXMGMASK_RD(x) |  (v)))
01344 #define HW_CAN_RXMGMASK_CLR(x, v) (HW_CAN_RXMGMASK_WR(x, HW_CAN_RXMGMASK_RD(x) & ~(v)))
01345 #define HW_CAN_RXMGMASK_TOG(x, v) (HW_CAN_RXMGMASK_WR(x, HW_CAN_RXMGMASK_RD(x) ^  (v)))
01346 /*@}*/
01347 
01348 /*
01349  * Constants & macros for individual CAN_RXMGMASK bitfields
01350  */
01351 
01352 /*!
01353  * @name Register CAN_RXMGMASK, field MG[31:0] (RW)
01354  *
01355  * These bits mask the Mailbox filter bits. Note that the alignment with the ID
01356  * word of the Mailbox is not perfect as the two most significant MG bits affect
01357  * the fields RTR and IDE, which are located in the Control and Status word of
01358  * the Mailbox. The following table shows in detail which MG bits mask each Mailbox
01359  * filter field. SMB[RTR] RTR bit of the Incoming Frame. It is saved into an
01360  * auxiliary MB called Rx Serial Message Buffer (Rx SMB). CTRL2[RRS] CTRL2[EACEN]
01361  * Mailbox filter fields MB[RTR] MB[IDE] MB[ID] Reserved 0 - 0 note If the
01362  * CTRL2[EACEN] bit is negated, the RTR bit of Mailbox is never compared with the RTR bit
01363  * of the incoming frame. note If the CTRL2[EACEN] bit is negated, the IDE bit
01364  * of Mailbox is always compared with the IDE bit of the incoming frame. MG[28:0]
01365  * MG[31:29] 0 - 1 MG[31] MG[30] MG[28:0] MG[29] 1 0 - - - - MG[31:0] 1 1 0 - -
01366  * MG[28:0] MG[31:29] 1 1 1 MG[31] MG[30] MG[28:0] MG[29]
01367  *
01368  * Values:
01369  * - 0 - The corresponding bit in the filter is "don't care."
01370  * - 1 - The corresponding bit in the filter is checked.
01371  */
01372 /*@{*/
01373 #define BP_CAN_RXMGMASK_MG   (0U)          /*!< Bit position for CAN_RXMGMASK_MG. */
01374 #define BM_CAN_RXMGMASK_MG   (0xFFFFFFFFU) /*!< Bit mask for CAN_RXMGMASK_MG. */
01375 #define BS_CAN_RXMGMASK_MG   (32U)         /*!< Bit field size in bits for CAN_RXMGMASK_MG. */
01376 
01377 /*! @brief Read current value of the CAN_RXMGMASK_MG field. */
01378 #define BR_CAN_RXMGMASK_MG(x) (HW_CAN_RXMGMASK(x).U)
01379 
01380 /*! @brief Format value for bitfield CAN_RXMGMASK_MG. */
01381 #define BF_CAN_RXMGMASK_MG(v) ((uint32_t)((uint32_t)(v) << BP_CAN_RXMGMASK_MG) & BM_CAN_RXMGMASK_MG)
01382 
01383 /*! @brief Set the MG field to a new value. */
01384 #define BW_CAN_RXMGMASK_MG(x, v) (HW_CAN_RXMGMASK_WR(x, v))
01385 /*@}*/
01386 
01387 /*******************************************************************************
01388  * HW_CAN_RX14MASK - Rx 14 Mask register
01389  ******************************************************************************/
01390 
01391 /*!
01392  * @brief HW_CAN_RX14MASK - Rx 14 Mask register (RW)
01393  *
01394  * Reset value: 0xFFFFFFFFU
01395  *
01396  * This register is located in RAM. RX14MASK is provided for legacy application
01397  * support. When the MCR[IRMQ] bit is asserted, RX14MASK has no effect. RX14MASK
01398  * is used to mask the filter fields of Message Buffer 14. This register can only
01399  * be programmed while the module is in Freeze mode as it is blocked by hardware
01400  * in other modes.
01401  */
01402 typedef union _hw_can_rx14mask
01403 {
01404     uint32_t U;
01405     struct _hw_can_rx14mask_bitfields
01406     {
01407         uint32_t RX14M : 32;           /*!< [31:0] Rx Buffer 14 Mask Bits */
01408     } B;
01409 } hw_can_rx14mask_t;
01410 
01411 /*!
01412  * @name Constants and macros for entire CAN_RX14MASK register
01413  */
01414 /*@{*/
01415 #define HW_CAN_RX14MASK_ADDR(x)  ((x) + 0x14U)
01416 
01417 #define HW_CAN_RX14MASK(x)       (*(__IO hw_can_rx14mask_t *) HW_CAN_RX14MASK_ADDR(x))
01418 #define HW_CAN_RX14MASK_RD(x)    (ADDRESS_READ(hw_can_rx14mask_t, HW_CAN_RX14MASK_ADDR(x)))
01419 #define HW_CAN_RX14MASK_WR(x, v) (ADDRESS_WRITE(hw_can_rx14mask_t, HW_CAN_RX14MASK_ADDR(x), v))
01420 #define HW_CAN_RX14MASK_SET(x, v) (HW_CAN_RX14MASK_WR(x, HW_CAN_RX14MASK_RD(x) |  (v)))
01421 #define HW_CAN_RX14MASK_CLR(x, v) (HW_CAN_RX14MASK_WR(x, HW_CAN_RX14MASK_RD(x) & ~(v)))
01422 #define HW_CAN_RX14MASK_TOG(x, v) (HW_CAN_RX14MASK_WR(x, HW_CAN_RX14MASK_RD(x) ^  (v)))
01423 /*@}*/
01424 
01425 /*
01426  * Constants & macros for individual CAN_RX14MASK bitfields
01427  */
01428 
01429 /*!
01430  * @name Register CAN_RX14MASK, field RX14M[31:0] (RW)
01431  *
01432  * Each mask bit masks the corresponding Mailbox 14 filter field in the same way
01433  * that RXMGMASK masks other Mailboxes' filters. See the description of the
01434  * CAN_RXMGMASK register.
01435  *
01436  * Values:
01437  * - 0 - The corresponding bit in the filter is "don't care."
01438  * - 1 - The corresponding bit in the filter is checked.
01439  */
01440 /*@{*/
01441 #define BP_CAN_RX14MASK_RX14M (0U)         /*!< Bit position for CAN_RX14MASK_RX14M. */
01442 #define BM_CAN_RX14MASK_RX14M (0xFFFFFFFFU) /*!< Bit mask for CAN_RX14MASK_RX14M. */
01443 #define BS_CAN_RX14MASK_RX14M (32U)        /*!< Bit field size in bits for CAN_RX14MASK_RX14M. */
01444 
01445 /*! @brief Read current value of the CAN_RX14MASK_RX14M field. */
01446 #define BR_CAN_RX14MASK_RX14M(x) (HW_CAN_RX14MASK(x).U)
01447 
01448 /*! @brief Format value for bitfield CAN_RX14MASK_RX14M. */
01449 #define BF_CAN_RX14MASK_RX14M(v) ((uint32_t)((uint32_t)(v) << BP_CAN_RX14MASK_RX14M) & BM_CAN_RX14MASK_RX14M)
01450 
01451 /*! @brief Set the RX14M field to a new value. */
01452 #define BW_CAN_RX14MASK_RX14M(x, v) (HW_CAN_RX14MASK_WR(x, v))
01453 /*@}*/
01454 
01455 /*******************************************************************************
01456  * HW_CAN_RX15MASK - Rx 15 Mask register
01457  ******************************************************************************/
01458 
01459 /*!
01460  * @brief HW_CAN_RX15MASK - Rx 15 Mask register (RW)
01461  *
01462  * Reset value: 0xFFFFFFFFU
01463  *
01464  * This register is located in RAM. RX15MASK is provided for legacy application
01465  * support. When the MCR[IRMQ] bit is asserted, RX15MASK has no effect. RX15MASK
01466  * is used to mask the filter fields of Message Buffer 15. This register can be
01467  * programmed only while the module is in Freeze mode because it is blocked by
01468  * hardware in other modes.
01469  */
01470 typedef union _hw_can_rx15mask
01471 {
01472     uint32_t U;
01473     struct _hw_can_rx15mask_bitfields
01474     {
01475         uint32_t RX15M : 32;           /*!< [31:0] Rx Buffer 15 Mask Bits */
01476     } B;
01477 } hw_can_rx15mask_t;
01478 
01479 /*!
01480  * @name Constants and macros for entire CAN_RX15MASK register
01481  */
01482 /*@{*/
01483 #define HW_CAN_RX15MASK_ADDR(x)  ((x) + 0x18U)
01484 
01485 #define HW_CAN_RX15MASK(x)       (*(__IO hw_can_rx15mask_t *) HW_CAN_RX15MASK_ADDR(x))
01486 #define HW_CAN_RX15MASK_RD(x)    (ADDRESS_READ(hw_can_rx15mask_t, HW_CAN_RX15MASK_ADDR(x)))
01487 #define HW_CAN_RX15MASK_WR(x, v) (ADDRESS_WRITE(hw_can_rx15mask_t, HW_CAN_RX15MASK_ADDR(x), v))
01488 #define HW_CAN_RX15MASK_SET(x, v) (HW_CAN_RX15MASK_WR(x, HW_CAN_RX15MASK_RD(x) |  (v)))
01489 #define HW_CAN_RX15MASK_CLR(x, v) (HW_CAN_RX15MASK_WR(x, HW_CAN_RX15MASK_RD(x) & ~(v)))
01490 #define HW_CAN_RX15MASK_TOG(x, v) (HW_CAN_RX15MASK_WR(x, HW_CAN_RX15MASK_RD(x) ^  (v)))
01491 /*@}*/
01492 
01493 /*
01494  * Constants & macros for individual CAN_RX15MASK bitfields
01495  */
01496 
01497 /*!
01498  * @name Register CAN_RX15MASK, field RX15M[31:0] (RW)
01499  *
01500  * Each mask bit masks the corresponding Mailbox 15 filter field in the same way
01501  * that RXMGMASK masks other Mailboxes' filters. See the description of the
01502  * CAN_RXMGMASK register.
01503  *
01504  * Values:
01505  * - 0 - The corresponding bit in the filter is "don't care."
01506  * - 1 - The corresponding bit in the filter is checked.
01507  */
01508 /*@{*/
01509 #define BP_CAN_RX15MASK_RX15M (0U)         /*!< Bit position for CAN_RX15MASK_RX15M. */
01510 #define BM_CAN_RX15MASK_RX15M (0xFFFFFFFFU) /*!< Bit mask for CAN_RX15MASK_RX15M. */
01511 #define BS_CAN_RX15MASK_RX15M (32U)        /*!< Bit field size in bits for CAN_RX15MASK_RX15M. */
01512 
01513 /*! @brief Read current value of the CAN_RX15MASK_RX15M field. */
01514 #define BR_CAN_RX15MASK_RX15M(x) (HW_CAN_RX15MASK(x).U)
01515 
01516 /*! @brief Format value for bitfield CAN_RX15MASK_RX15M. */
01517 #define BF_CAN_RX15MASK_RX15M(v) ((uint32_t)((uint32_t)(v) << BP_CAN_RX15MASK_RX15M) & BM_CAN_RX15MASK_RX15M)
01518 
01519 /*! @brief Set the RX15M field to a new value. */
01520 #define BW_CAN_RX15MASK_RX15M(x, v) (HW_CAN_RX15MASK_WR(x, v))
01521 /*@}*/
01522 
01523 /*******************************************************************************
01524  * HW_CAN_ECR - Error Counter
01525  ******************************************************************************/
01526 
01527 /*!
01528  * @brief HW_CAN_ECR - Error Counter (RW)
01529  *
01530  * Reset value: 0x00000000U
01531  *
01532  * This register has two 8-bit fields reflecting the value of two FlexCAN error
01533  * counters: Transmit Error Counter (TXERRCNT field) and Receive Error Counter
01534  * (RXERRCNT field). The rules for increasing and decreasing these counters are
01535  * described in the CAN protocol and are completely implemented in the FlexCAN
01536  * module. Both counters are read-only except in Freeze mode, where they can be
01537  * written by the CPU. FlexCAN responds to any bus state as described in the protocol,
01538  * for example, transmit Error Active or Error Passive flag, delay its
01539  * transmission start time (Error Passive) and avoid any influence on the bus when in Bus
01540  * Off state. The following are the basic rules for FlexCAN bus state transitions:
01541  * If the value of TXERRCNT or RXERRCNT increases to be greater than or equal to
01542  * 128, the FLTCONF field in the Error and Status Register is updated to reflect
01543  * 'Error Passive' state. If the FlexCAN state is 'Error Passive', and either
01544  * TXERRCNT or RXERRCNT decrements to a value less than or equal to 127 while the
01545  * other already satisfies this condition, the FLTCONF field in the Error and
01546  * Status Register is updated to reflect 'Error Active' state. If the value of
01547  * TXERRCNT increases to be greater than 255, the FLTCONF field in the Error and Status
01548  * Register is updated to reflect 'Bus Off' state, and an interrupt may be
01549  * issued. The value of TXERRCNT is then reset to zero. If FlexCAN is in 'Bus Off'
01550  * state, then TXERRCNT is cascaded together with another internal counter to count
01551  * the 128th occurrences of 11 consecutive recessive bits on the bus. Hence,
01552  * TXERRCNT is reset to zero and counts in a manner where the internal counter counts
01553  * 11 such bits and then wraps around while incrementing the TXERRCNT. When
01554  * TXERRCNT reaches the value of 128, the FLTCONF field in the Error and Status
01555  * Register is updated to be 'Error Active' and both error counters are reset to zero.
01556  * At any instance of dominant bit following a stream of less than 11
01557  * consecutive recessive bits, the internal counter resets itself to zero without affecting
01558  * the TXERRCNT value. If during system start-up, only one node is operating,
01559  * then its TXERRCNT increases in each message it is trying to transmit, as a
01560  * result of acknowledge errors (indicated by the ACKERR bit in the Error and Status
01561  * Register). After the transition to 'Error Passive' state, the TXERRCNT does not
01562  * increment anymore by acknowledge errors. Therefore the device never goes to
01563  * the 'Bus Off' state. If the RXERRCNT increases to a value greater than 127, it
01564  * is not incremented further, even if more errors are detected while being a
01565  * receiver. At the next successful message reception, the counter is set to a value
01566  * between 119 and 127 to resume to 'Error Active' state.
01567  */
01568 typedef union _hw_can_ecr
01569 {
01570     uint32_t U;
01571     struct _hw_can_ecr_bitfields
01572     {
01573         uint32_t TXERRCNT : 8;         /*!< [7:0] Transmit Error Counter */
01574         uint32_t RXERRCNT : 8;         /*!< [15:8] Receive Error Counter */
01575         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
01576     } B;
01577 } hw_can_ecr_t;
01578 
01579 /*!
01580  * @name Constants and macros for entire CAN_ECR register
01581  */
01582 /*@{*/
01583 #define HW_CAN_ECR_ADDR(x)       ((x) + 0x1CU)
01584 
01585 #define HW_CAN_ECR(x)            (*(__IO hw_can_ecr_t *) HW_CAN_ECR_ADDR(x))
01586 #define HW_CAN_ECR_RD(x)         (ADDRESS_READ(hw_can_ecr_t, HW_CAN_ECR_ADDR(x)))
01587 #define HW_CAN_ECR_WR(x, v)      (ADDRESS_WRITE(hw_can_ecr_t, HW_CAN_ECR_ADDR(x), v))
01588 #define HW_CAN_ECR_SET(x, v)     (HW_CAN_ECR_WR(x, HW_CAN_ECR_RD(x) |  (v)))
01589 #define HW_CAN_ECR_CLR(x, v)     (HW_CAN_ECR_WR(x, HW_CAN_ECR_RD(x) & ~(v)))
01590 #define HW_CAN_ECR_TOG(x, v)     (HW_CAN_ECR_WR(x, HW_CAN_ECR_RD(x) ^  (v)))
01591 /*@}*/
01592 
01593 /*
01594  * Constants & macros for individual CAN_ECR bitfields
01595  */
01596 
01597 /*!
01598  * @name Register CAN_ECR, field TXERRCNT[7:0] (RW)
01599  */
01600 /*@{*/
01601 #define BP_CAN_ECR_TXERRCNT  (0U)          /*!< Bit position for CAN_ECR_TXERRCNT. */
01602 #define BM_CAN_ECR_TXERRCNT  (0x000000FFU) /*!< Bit mask for CAN_ECR_TXERRCNT. */
01603 #define BS_CAN_ECR_TXERRCNT  (8U)          /*!< Bit field size in bits for CAN_ECR_TXERRCNT. */
01604 
01605 /*! @brief Read current value of the CAN_ECR_TXERRCNT field. */
01606 #define BR_CAN_ECR_TXERRCNT(x) (UNION_READ(hw_can_ecr_t, HW_CAN_ECR_ADDR(x), U, B.TXERRCNT))
01607 
01608 /*! @brief Format value for bitfield CAN_ECR_TXERRCNT. */
01609 #define BF_CAN_ECR_TXERRCNT(v) ((uint32_t)((uint32_t)(v) << BP_CAN_ECR_TXERRCNT) & BM_CAN_ECR_TXERRCNT)
01610 
01611 /*! @brief Set the TXERRCNT field to a new value. */
01612 #define BW_CAN_ECR_TXERRCNT(x, v) (HW_CAN_ECR_WR(x, (HW_CAN_ECR_RD(x) & ~BM_CAN_ECR_TXERRCNT) | BF_CAN_ECR_TXERRCNT(v)))
01613 /*@}*/
01614 
01615 /*!
01616  * @name Register CAN_ECR, field RXERRCNT[15:8] (RW)
01617  */
01618 /*@{*/
01619 #define BP_CAN_ECR_RXERRCNT  (8U)          /*!< Bit position for CAN_ECR_RXERRCNT. */
01620 #define BM_CAN_ECR_RXERRCNT  (0x0000FF00U) /*!< Bit mask for CAN_ECR_RXERRCNT. */
01621 #define BS_CAN_ECR_RXERRCNT  (8U)          /*!< Bit field size in bits for CAN_ECR_RXERRCNT. */
01622 
01623 /*! @brief Read current value of the CAN_ECR_RXERRCNT field. */
01624 #define BR_CAN_ECR_RXERRCNT(x) (UNION_READ(hw_can_ecr_t, HW_CAN_ECR_ADDR(x), U, B.RXERRCNT))
01625 
01626 /*! @brief Format value for bitfield CAN_ECR_RXERRCNT. */
01627 #define BF_CAN_ECR_RXERRCNT(v) ((uint32_t)((uint32_t)(v) << BP_CAN_ECR_RXERRCNT) & BM_CAN_ECR_RXERRCNT)
01628 
01629 /*! @brief Set the RXERRCNT field to a new value. */
01630 #define BW_CAN_ECR_RXERRCNT(x, v) (HW_CAN_ECR_WR(x, (HW_CAN_ECR_RD(x) & ~BM_CAN_ECR_RXERRCNT) | BF_CAN_ECR_RXERRCNT(v)))
01631 /*@}*/
01632 
01633 /*******************************************************************************
01634  * HW_CAN_ESR1 - Error and Status 1 register
01635  ******************************************************************************/
01636 
01637 /*!
01638  * @brief HW_CAN_ESR1 - Error and Status 1 register (RW)
01639  *
01640  * Reset value: 0x00000000U
01641  *
01642  * This register reflects various error conditions, some general status of the
01643  * device and it is the source of interrupts to the CPU. The CPU read action
01644  * clears bits 15-10. Therefore the reported error conditions (bits 15-10) are those
01645  * that occurred since the last time the CPU read this register. Bits 9-3 are
01646  * status bits. The following table shows the FlexCAN state variables and their
01647  * meanings. Other combinations not shown in the table are reserved. SYNCH IDLE TX RX
01648  * FlexCAN State 0 0 0 0 Not synchronized to CAN bus 1 1 x x Idle 1 0 1 0
01649  * Transmitting 1 0 0 1 Receiving
01650  */
01651 typedef union _hw_can_esr1
01652 {
01653     uint32_t U;
01654     struct _hw_can_esr1_bitfields
01655     {
01656         uint32_t WAKINT : 1;           /*!< [0] Wake-Up Interrupt */
01657         uint32_t ERRINT : 1;           /*!< [1] Error Interrupt */
01658         uint32_t BOFFINT : 1;          /*!< [2] Bus Off Interrupt */
01659         uint32_t RX : 1;               /*!< [3] FlexCAN In Reception */
01660         uint32_t FLTCONF : 2;          /*!< [5:4] Fault Confinement State */
01661         uint32_t TX : 1;               /*!< [6] FlexCAN In Transmission */
01662         uint32_t IDLE : 1;             /*!< [7]  */
01663         uint32_t RXWRN : 1;            /*!< [8] Rx Error Warning */
01664         uint32_t TXWRN : 1;            /*!< [9] TX Error Warning */
01665         uint32_t STFERR : 1;           /*!< [10] Stuffing Error */
01666         uint32_t FRMERR : 1;           /*!< [11] Form Error */
01667         uint32_t CRCERR : 1;           /*!< [12] Cyclic Redundancy Check Error */
01668         uint32_t ACKERR : 1;           /*!< [13] Acknowledge Error */
01669         uint32_t BIT0ERR : 1;          /*!< [14] Bit0 Error */
01670         uint32_t BIT1ERR : 1;          /*!< [15] Bit1 Error */
01671         uint32_t RWRNINT : 1;          /*!< [16] Rx Warning Interrupt Flag */
01672         uint32_t TWRNINT : 1;          /*!< [17] Tx Warning Interrupt Flag */
01673         uint32_t SYNCH : 1;            /*!< [18] CAN Synchronization Status */
01674         uint32_t RESERVED0 : 13;       /*!< [31:19]  */
01675     } B;
01676 } hw_can_esr1_t;
01677 
01678 /*!
01679  * @name Constants and macros for entire CAN_ESR1 register
01680  */
01681 /*@{*/
01682 #define HW_CAN_ESR1_ADDR(x)      ((x) + 0x20U)
01683 
01684 #define HW_CAN_ESR1(x)           (*(__IO hw_can_esr1_t *) HW_CAN_ESR1_ADDR(x))
01685 #define HW_CAN_ESR1_RD(x)        (ADDRESS_READ(hw_can_esr1_t, HW_CAN_ESR1_ADDR(x)))
01686 #define HW_CAN_ESR1_WR(x, v)     (ADDRESS_WRITE(hw_can_esr1_t, HW_CAN_ESR1_ADDR(x), v))
01687 #define HW_CAN_ESR1_SET(x, v)    (HW_CAN_ESR1_WR(x, HW_CAN_ESR1_RD(x) |  (v)))
01688 #define HW_CAN_ESR1_CLR(x, v)    (HW_CAN_ESR1_WR(x, HW_CAN_ESR1_RD(x) & ~(v)))
01689 #define HW_CAN_ESR1_TOG(x, v)    (HW_CAN_ESR1_WR(x, HW_CAN_ESR1_RD(x) ^  (v)))
01690 /*@}*/
01691 
01692 /*
01693  * Constants & macros for individual CAN_ESR1 bitfields
01694  */
01695 
01696 /*!
01697  * @name Register CAN_ESR1, field WAKINT[0] (W1C)
01698  *
01699  * This field applies when FlexCAN is in low-power mode under Self Wake Up
01700  * mechanism: Stop mode When a recessive-to-dominant transition is detected on the CAN
01701  * bus and if the MCR[WAKMSK] bit is set, an interrupt is generated to the CPU.
01702  * This bit is cleared by writing it to 1. When MCR[SLFWAK] is negated, this flag
01703  * is masked. The CPU must clear this flag before disabling the bit. Otherwise
01704  * it will be set when the SLFWAK is set again. Writing 0 has no effect.
01705  *
01706  * Values:
01707  * - 0 - No such occurrence.
01708  * - 1 - Indicates a recessive to dominant transition was received on the CAN
01709  *     bus.
01710  */
01711 /*@{*/
01712 #define BP_CAN_ESR1_WAKINT   (0U)          /*!< Bit position for CAN_ESR1_WAKINT. */
01713 #define BM_CAN_ESR1_WAKINT   (0x00000001U) /*!< Bit mask for CAN_ESR1_WAKINT. */
01714 #define BS_CAN_ESR1_WAKINT   (1U)          /*!< Bit field size in bits for CAN_ESR1_WAKINT. */
01715 
01716 /*! @brief Read current value of the CAN_ESR1_WAKINT field. */
01717 #define BR_CAN_ESR1_WAKINT(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_WAKINT)))
01718 
01719 /*! @brief Format value for bitfield CAN_ESR1_WAKINT. */
01720 #define BF_CAN_ESR1_WAKINT(v) ((uint32_t)((uint32_t)(v) << BP_CAN_ESR1_WAKINT) & BM_CAN_ESR1_WAKINT)
01721 
01722 /*! @brief Set the WAKINT field to a new value. */
01723 #define BW_CAN_ESR1_WAKINT(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_WAKINT), v))
01724 /*@}*/
01725 
01726 /*!
01727  * @name Register CAN_ESR1, field ERRINT[1] (W1C)
01728  *
01729  * This bit indicates that at least one of the Error Bits (bits 15-10) is set.
01730  * If the corresponding mask bit CTRL1[ERRMSK] is set, an interrupt is generated
01731  * to the CPU. This bit is cleared by writing it to 1. Writing 0 has no effect.
01732  *
01733  * Values:
01734  * - 0 - No such occurrence.
01735  * - 1 - Indicates setting of any Error Bit in the Error and Status Register.
01736  */
01737 /*@{*/
01738 #define BP_CAN_ESR1_ERRINT   (1U)          /*!< Bit position for CAN_ESR1_ERRINT. */
01739 #define BM_CAN_ESR1_ERRINT   (0x00000002U) /*!< Bit mask for CAN_ESR1_ERRINT. */
01740 #define BS_CAN_ESR1_ERRINT   (1U)          /*!< Bit field size in bits for CAN_ESR1_ERRINT. */
01741 
01742 /*! @brief Read current value of the CAN_ESR1_ERRINT field. */
01743 #define BR_CAN_ESR1_ERRINT(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_ERRINT)))
01744 
01745 /*! @brief Format value for bitfield CAN_ESR1_ERRINT. */
01746 #define BF_CAN_ESR1_ERRINT(v) ((uint32_t)((uint32_t)(v) << BP_CAN_ESR1_ERRINT) & BM_CAN_ESR1_ERRINT)
01747 
01748 /*! @brief Set the ERRINT field to a new value. */
01749 #define BW_CAN_ESR1_ERRINT(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_ERRINT), v))
01750 /*@}*/
01751 
01752 /*!
01753  * @name Register CAN_ESR1, field BOFFINT[2] (W1C)
01754  *
01755  * This bit is set when FlexCAN enters 'Bus Off' state. If the corresponding
01756  * mask bit in the Control Register (BOFFMSK) is set, an interrupt is generated to
01757  * the CPU. This bit is cleared by writing it to 1. Writing 0 has no effect.
01758  *
01759  * Values:
01760  * - 0 - No such occurrence.
01761  * - 1 - FlexCAN module entered Bus Off state.
01762  */
01763 /*@{*/
01764 #define BP_CAN_ESR1_BOFFINT  (2U)          /*!< Bit position for CAN_ESR1_BOFFINT. */
01765 #define BM_CAN_ESR1_BOFFINT  (0x00000004U) /*!< Bit mask for CAN_ESR1_BOFFINT. */
01766 #define BS_CAN_ESR1_BOFFINT  (1U)          /*!< Bit field size in bits for CAN_ESR1_BOFFINT. */
01767 
01768 /*! @brief Read current value of the CAN_ESR1_BOFFINT field. */
01769 #define BR_CAN_ESR1_BOFFINT(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_BOFFINT)))
01770 
01771 /*! @brief Format value for bitfield CAN_ESR1_BOFFINT. */
01772 #define BF_CAN_ESR1_BOFFINT(v) ((uint32_t)((uint32_t)(v) << BP_CAN_ESR1_BOFFINT) & BM_CAN_ESR1_BOFFINT)
01773 
01774 /*! @brief Set the BOFFINT field to a new value. */
01775 #define BW_CAN_ESR1_BOFFINT(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_BOFFINT), v))
01776 /*@}*/
01777 
01778 /*!
01779  * @name Register CAN_ESR1, field RX[3] (RO)
01780  *
01781  * This bit indicates if FlexCAN is receiving a message. See the table in the
01782  * overall CAN_ESR1 register description.
01783  *
01784  * Values:
01785  * - 0 - FlexCAN is not receiving a message.
01786  * - 1 - FlexCAN is receiving a message.
01787  */
01788 /*@{*/
01789 #define BP_CAN_ESR1_RX       (3U)          /*!< Bit position for CAN_ESR1_RX. */
01790 #define BM_CAN_ESR1_RX       (0x00000008U) /*!< Bit mask for CAN_ESR1_RX. */
01791 #define BS_CAN_ESR1_RX       (1U)          /*!< Bit field size in bits for CAN_ESR1_RX. */
01792 
01793 /*! @brief Read current value of the CAN_ESR1_RX field. */
01794 #define BR_CAN_ESR1_RX(x)    (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_RX)))
01795 /*@}*/
01796 
01797 /*!
01798  * @name Register CAN_ESR1, field FLTCONF[5:4] (RO)
01799  *
01800  * This 2-bit field indicates the Confinement State of the FlexCAN module. If
01801  * the LOM bit in the Control Register is asserted, after some delay that depends
01802  * on the CAN bit timing the FLTCONF field will indicate "Error Passive". The very
01803  * same delay affects the way how FLTCONF reflects an update to ECR register by
01804  * the CPU. It may be necessary up to one CAN bit time to get them coherent
01805  * again. Because the Control Register is not affected by soft reset, the FLTCONF
01806  * field will not be affected by soft reset if the LOM bit is asserted.
01807  *
01808  * Values:
01809  * - 00 - Error Active
01810  * - 01 - Error Passive
01811  * - 1x - Bus Off
01812  */
01813 /*@{*/
01814 #define BP_CAN_ESR1_FLTCONF  (4U)          /*!< Bit position for CAN_ESR1_FLTCONF. */
01815 #define BM_CAN_ESR1_FLTCONF  (0x00000030U) /*!< Bit mask for CAN_ESR1_FLTCONF. */
01816 #define BS_CAN_ESR1_FLTCONF  (2U)          /*!< Bit field size in bits for CAN_ESR1_FLTCONF. */
01817 
01818 /*! @brief Read current value of the CAN_ESR1_FLTCONF field. */
01819 #define BR_CAN_ESR1_FLTCONF(x) (UNION_READ(hw_can_esr1_t, HW_CAN_ESR1_ADDR(x), U, B.FLTCONF))
01820 /*@}*/
01821 
01822 /*!
01823  * @name Register CAN_ESR1, field TX[6] (RO)
01824  *
01825  * This bit indicates if FlexCAN is transmitting a message. See the table in the
01826  * overall CAN_ESR1 register description.
01827  *
01828  * Values:
01829  * - 0 - FlexCAN is not transmitting a message.
01830  * - 1 - FlexCAN is transmitting a message.
01831  */
01832 /*@{*/
01833 #define BP_CAN_ESR1_TX       (6U)          /*!< Bit position for CAN_ESR1_TX. */
01834 #define BM_CAN_ESR1_TX       (0x00000040U) /*!< Bit mask for CAN_ESR1_TX. */
01835 #define BS_CAN_ESR1_TX       (1U)          /*!< Bit field size in bits for CAN_ESR1_TX. */
01836 
01837 /*! @brief Read current value of the CAN_ESR1_TX field. */
01838 #define BR_CAN_ESR1_TX(x)    (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_TX)))
01839 /*@}*/
01840 
01841 /*!
01842  * @name Register CAN_ESR1, field IDLE[7] (RO)
01843  *
01844  * This bit indicates when CAN bus is in IDLE state. See the table in the
01845  * overall CAN_ESR1 register description.
01846  *
01847  * Values:
01848  * - 0 - No such occurrence.
01849  * - 1 - CAN bus is now IDLE.
01850  */
01851 /*@{*/
01852 #define BP_CAN_ESR1_IDLE     (7U)          /*!< Bit position for CAN_ESR1_IDLE. */
01853 #define BM_CAN_ESR1_IDLE     (0x00000080U) /*!< Bit mask for CAN_ESR1_IDLE. */
01854 #define BS_CAN_ESR1_IDLE     (1U)          /*!< Bit field size in bits for CAN_ESR1_IDLE. */
01855 
01856 /*! @brief Read current value of the CAN_ESR1_IDLE field. */
01857 #define BR_CAN_ESR1_IDLE(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_IDLE)))
01858 /*@}*/
01859 
01860 /*!
01861  * @name Register CAN_ESR1, field RXWRN[8] (RO)
01862  *
01863  * This bit indicates when repetitive errors are occurring during message
01864  * reception. This bit is not updated during Freeze mode.
01865  *
01866  * Values:
01867  * - 0 - No such occurrence.
01868  * - 1 - RXERRCNT is greater than or equal to 96.
01869  */
01870 /*@{*/
01871 #define BP_CAN_ESR1_RXWRN    (8U)          /*!< Bit position for CAN_ESR1_RXWRN. */
01872 #define BM_CAN_ESR1_RXWRN    (0x00000100U) /*!< Bit mask for CAN_ESR1_RXWRN. */
01873 #define BS_CAN_ESR1_RXWRN    (1U)          /*!< Bit field size in bits for CAN_ESR1_RXWRN. */
01874 
01875 /*! @brief Read current value of the CAN_ESR1_RXWRN field. */
01876 #define BR_CAN_ESR1_RXWRN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_RXWRN)))
01877 /*@}*/
01878 
01879 /*!
01880  * @name Register CAN_ESR1, field TXWRN[9] (RO)
01881  *
01882  * This bit indicates when repetitive errors are occurring during message
01883  * transmission. This bit is not updated during Freeze mode.
01884  *
01885  * Values:
01886  * - 0 - No such occurrence.
01887  * - 1 - TXERRCNT is greater than or equal to 96.
01888  */
01889 /*@{*/
01890 #define BP_CAN_ESR1_TXWRN    (9U)          /*!< Bit position for CAN_ESR1_TXWRN. */
01891 #define BM_CAN_ESR1_TXWRN    (0x00000200U) /*!< Bit mask for CAN_ESR1_TXWRN. */
01892 #define BS_CAN_ESR1_TXWRN    (1U)          /*!< Bit field size in bits for CAN_ESR1_TXWRN. */
01893 
01894 /*! @brief Read current value of the CAN_ESR1_TXWRN field. */
01895 #define BR_CAN_ESR1_TXWRN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_TXWRN)))
01896 /*@}*/
01897 
01898 /*!
01899  * @name Register CAN_ESR1, field STFERR[10] (RO)
01900  *
01901  * This bit indicates that a Stuffing Error has been etected.
01902  *
01903  * Values:
01904  * - 0 - No such occurrence.
01905  * - 1 - A Stuffing Error occurred since last read of this register.
01906  */
01907 /*@{*/
01908 #define BP_CAN_ESR1_STFERR   (10U)         /*!< Bit position for CAN_ESR1_STFERR. */
01909 #define BM_CAN_ESR1_STFERR   (0x00000400U) /*!< Bit mask for CAN_ESR1_STFERR. */
01910 #define BS_CAN_ESR1_STFERR   (1U)          /*!< Bit field size in bits for CAN_ESR1_STFERR. */
01911 
01912 /*! @brief Read current value of the CAN_ESR1_STFERR field. */
01913 #define BR_CAN_ESR1_STFERR(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_STFERR)))
01914 /*@}*/
01915 
01916 /*!
01917  * @name Register CAN_ESR1, field FRMERR[11] (RO)
01918  *
01919  * This bit indicates that a Form Error has been detected by the receiver node,
01920  * that is, a fixed-form bit field contains at least one illegal bit.
01921  *
01922  * Values:
01923  * - 0 - No such occurrence.
01924  * - 1 - A Form Error occurred since last read of this register.
01925  */
01926 /*@{*/
01927 #define BP_CAN_ESR1_FRMERR   (11U)         /*!< Bit position for CAN_ESR1_FRMERR. */
01928 #define BM_CAN_ESR1_FRMERR   (0x00000800U) /*!< Bit mask for CAN_ESR1_FRMERR. */
01929 #define BS_CAN_ESR1_FRMERR   (1U)          /*!< Bit field size in bits for CAN_ESR1_FRMERR. */
01930 
01931 /*! @brief Read current value of the CAN_ESR1_FRMERR field. */
01932 #define BR_CAN_ESR1_FRMERR(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_FRMERR)))
01933 /*@}*/
01934 
01935 /*!
01936  * @name Register CAN_ESR1, field CRCERR[12] (RO)
01937  *
01938  * This bit indicates that a CRC Error has been detected by the receiver node,
01939  * that is, the calculated CRC is different from the received.
01940  *
01941  * Values:
01942  * - 0 - No such occurrence.
01943  * - 1 - A CRC error occurred since last read of this register.
01944  */
01945 /*@{*/
01946 #define BP_CAN_ESR1_CRCERR   (12U)         /*!< Bit position for CAN_ESR1_CRCERR. */
01947 #define BM_CAN_ESR1_CRCERR   (0x00001000U) /*!< Bit mask for CAN_ESR1_CRCERR. */
01948 #define BS_CAN_ESR1_CRCERR   (1U)          /*!< Bit field size in bits for CAN_ESR1_CRCERR. */
01949 
01950 /*! @brief Read current value of the CAN_ESR1_CRCERR field. */
01951 #define BR_CAN_ESR1_CRCERR(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_CRCERR)))
01952 /*@}*/
01953 
01954 /*!
01955  * @name Register CAN_ESR1, field ACKERR[13] (RO)
01956  *
01957  * This bit indicates that an Acknowledge Error has been detected by the
01958  * transmitter node, that is, a dominant bit has not been detected during the ACK SLOT.
01959  *
01960  * Values:
01961  * - 0 - No such occurrence.
01962  * - 1 - An ACK error occurred since last read of this register.
01963  */
01964 /*@{*/
01965 #define BP_CAN_ESR1_ACKERR   (13U)         /*!< Bit position for CAN_ESR1_ACKERR. */
01966 #define BM_CAN_ESR1_ACKERR   (0x00002000U) /*!< Bit mask for CAN_ESR1_ACKERR. */
01967 #define BS_CAN_ESR1_ACKERR   (1U)          /*!< Bit field size in bits for CAN_ESR1_ACKERR. */
01968 
01969 /*! @brief Read current value of the CAN_ESR1_ACKERR field. */
01970 #define BR_CAN_ESR1_ACKERR(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_ACKERR)))
01971 /*@}*/
01972 
01973 /*!
01974  * @name Register CAN_ESR1, field BIT0ERR[14] (RO)
01975  *
01976  * This bit indicates when an inconsistency occurs between the transmitted and
01977  * the received bit in a message.
01978  *
01979  * Values:
01980  * - 0 - No such occurrence.
01981  * - 1 - At least one bit sent as dominant is received as recessive.
01982  */
01983 /*@{*/
01984 #define BP_CAN_ESR1_BIT0ERR  (14U)         /*!< Bit position for CAN_ESR1_BIT0ERR. */
01985 #define BM_CAN_ESR1_BIT0ERR  (0x00004000U) /*!< Bit mask for CAN_ESR1_BIT0ERR. */
01986 #define BS_CAN_ESR1_BIT0ERR  (1U)          /*!< Bit field size in bits for CAN_ESR1_BIT0ERR. */
01987 
01988 /*! @brief Read current value of the CAN_ESR1_BIT0ERR field. */
01989 #define BR_CAN_ESR1_BIT0ERR(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_BIT0ERR)))
01990 /*@}*/
01991 
01992 /*!
01993  * @name Register CAN_ESR1, field BIT1ERR[15] (RO)
01994  *
01995  * This bit indicates when an inconsistency occurs between the transmitted and
01996  * the received bit in a message. This bit is not set by a transmitter in case of
01997  * arbitration field or ACK slot, or in case of a node sending a passive error
01998  * flag that detects dominant bits.
01999  *
02000  * Values:
02001  * - 0 - No such occurrence.
02002  * - 1 - At least one bit sent as recessive is received as dominant.
02003  */
02004 /*@{*/
02005 #define BP_CAN_ESR1_BIT1ERR  (15U)         /*!< Bit position for CAN_ESR1_BIT1ERR. */
02006 #define BM_CAN_ESR1_BIT1ERR  (0x00008000U) /*!< Bit mask for CAN_ESR1_BIT1ERR. */
02007 #define BS_CAN_ESR1_BIT1ERR  (1U)          /*!< Bit field size in bits for CAN_ESR1_BIT1ERR. */
02008 
02009 /*! @brief Read current value of the CAN_ESR1_BIT1ERR field. */
02010 #define BR_CAN_ESR1_BIT1ERR(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_BIT1ERR)))
02011 /*@}*/
02012 
02013 /*!
02014  * @name Register CAN_ESR1, field RWRNINT[16] (W1C)
02015  *
02016  * If the WRNEN bit in MCR is asserted, the RWRNINT bit is set when the RXWRN
02017  * flag transitions from 0 to 1, meaning that the Rx error counters reached 96. If
02018  * the corresponding mask bit in the Control Register (RWRNMSK) is set, an
02019  * interrupt is generated to the CPU. This bit is cleared by writing it to 1. When
02020  * WRNEN is negated, this flag is masked. CPU must clear this flag before disabling
02021  * the bit. Otherwise it will be set when the WRNEN is set again. Writing 0 has no
02022  * effect. This bit is not updated during Freeze mode.
02023  *
02024  * Values:
02025  * - 0 - No such occurrence.
02026  * - 1 - The Rx error counter transitioned from less than 96 to greater than or
02027  *     equal to 96.
02028  */
02029 /*@{*/
02030 #define BP_CAN_ESR1_RWRNINT  (16U)         /*!< Bit position for CAN_ESR1_RWRNINT. */
02031 #define BM_CAN_ESR1_RWRNINT  (0x00010000U) /*!< Bit mask for CAN_ESR1_RWRNINT. */
02032 #define BS_CAN_ESR1_RWRNINT  (1U)          /*!< Bit field size in bits for CAN_ESR1_RWRNINT. */
02033 
02034 /*! @brief Read current value of the CAN_ESR1_RWRNINT field. */
02035 #define BR_CAN_ESR1_RWRNINT(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_RWRNINT)))
02036 
02037 /*! @brief Format value for bitfield CAN_ESR1_RWRNINT. */
02038 #define BF_CAN_ESR1_RWRNINT(v) ((uint32_t)((uint32_t)(v) << BP_CAN_ESR1_RWRNINT) & BM_CAN_ESR1_RWRNINT)
02039 
02040 /*! @brief Set the RWRNINT field to a new value. */
02041 #define BW_CAN_ESR1_RWRNINT(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_RWRNINT), v))
02042 /*@}*/
02043 
02044 /*!
02045  * @name Register CAN_ESR1, field TWRNINT[17] (W1C)
02046  *
02047  * If the WRNEN bit in MCR is asserted, the TWRNINT bit is set when the TXWRN
02048  * flag transitions from 0 to 1, meaning that the Tx error counter reached 96. If
02049  * the corresponding mask bit in the Control Register (TWRNMSK) is set, an
02050  * interrupt is generated to the CPU. This bit is cleared by writing it to 1. When WRNEN
02051  * is negated, this flag is masked. CPU must clear this flag before disabling
02052  * the bit. Otherwise it will be set when the WRNEN is set again. Writing 0 has no
02053  * effect. This flag is not generated during Bus Off state. This bit is not
02054  * updated during Freeze mode.
02055  *
02056  * Values:
02057  * - 0 - No such occurrence.
02058  * - 1 - The Tx error counter transitioned from less than 96 to greater than or
02059  *     equal to 96.
02060  */
02061 /*@{*/
02062 #define BP_CAN_ESR1_TWRNINT  (17U)         /*!< Bit position for CAN_ESR1_TWRNINT. */
02063 #define BM_CAN_ESR1_TWRNINT  (0x00020000U) /*!< Bit mask for CAN_ESR1_TWRNINT. */
02064 #define BS_CAN_ESR1_TWRNINT  (1U)          /*!< Bit field size in bits for CAN_ESR1_TWRNINT. */
02065 
02066 /*! @brief Read current value of the CAN_ESR1_TWRNINT field. */
02067 #define BR_CAN_ESR1_TWRNINT(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_TWRNINT)))
02068 
02069 /*! @brief Format value for bitfield CAN_ESR1_TWRNINT. */
02070 #define BF_CAN_ESR1_TWRNINT(v) ((uint32_t)((uint32_t)(v) << BP_CAN_ESR1_TWRNINT) & BM_CAN_ESR1_TWRNINT)
02071 
02072 /*! @brief Set the TWRNINT field to a new value. */
02073 #define BW_CAN_ESR1_TWRNINT(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_TWRNINT), v))
02074 /*@}*/
02075 
02076 /*!
02077  * @name Register CAN_ESR1, field SYNCH[18] (RO)
02078  *
02079  * This read-only flag indicates whether the FlexCAN is synchronized to the CAN
02080  * bus and able to participate in the communication process. It is set and
02081  * cleared by the FlexCAN. See the table in the overall CAN_ESR1 register description.
02082  *
02083  * Values:
02084  * - 0 - FlexCAN is not synchronized to the CAN bus.
02085  * - 1 - FlexCAN is synchronized to the CAN bus.
02086  */
02087 /*@{*/
02088 #define BP_CAN_ESR1_SYNCH    (18U)         /*!< Bit position for CAN_ESR1_SYNCH. */
02089 #define BM_CAN_ESR1_SYNCH    (0x00040000U) /*!< Bit mask for CAN_ESR1_SYNCH. */
02090 #define BS_CAN_ESR1_SYNCH    (1U)          /*!< Bit field size in bits for CAN_ESR1_SYNCH. */
02091 
02092 /*! @brief Read current value of the CAN_ESR1_SYNCH field. */
02093 #define BR_CAN_ESR1_SYNCH(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_SYNCH)))
02094 /*@}*/
02095 
02096 /*******************************************************************************
02097  * HW_CAN_IMASK1 - Interrupt Masks 1 register
02098  ******************************************************************************/
02099 
02100 /*!
02101  * @brief HW_CAN_IMASK1 - Interrupt Masks 1 register (RW)
02102  *
02103  * Reset value: 0x00000000U
02104  *
02105  * This register allows any number of a range of the 32 Message Buffer
02106  * Interrupts to be enabled or disabled for MB31 to MB0. It contains one interrupt mask
02107  * bit per buffer, enabling the CPU to determine which buffer generates an
02108  * interrupt after a successful transmission or reception, that is, when the
02109  * corresponding IFLAG1 bit is set.
02110  */
02111 typedef union _hw_can_imask1
02112 {
02113     uint32_t U;
02114     struct _hw_can_imask1_bitfields
02115     {
02116         uint32_t BUFLM : 32;           /*!< [31:0] Buffer MB i Mask */
02117     } B;
02118 } hw_can_imask1_t;
02119 
02120 /*!
02121  * @name Constants and macros for entire CAN_IMASK1 register
02122  */
02123 /*@{*/
02124 #define HW_CAN_IMASK1_ADDR(x)    ((x) + 0x28U)
02125 
02126 #define HW_CAN_IMASK1(x)         (*(__IO hw_can_imask1_t *) HW_CAN_IMASK1_ADDR(x))
02127 #define HW_CAN_IMASK1_RD(x)      (ADDRESS_READ(hw_can_imask1_t, HW_CAN_IMASK1_ADDR(x)))
02128 #define HW_CAN_IMASK1_WR(x, v)   (ADDRESS_WRITE(hw_can_imask1_t, HW_CAN_IMASK1_ADDR(x), v))
02129 #define HW_CAN_IMASK1_SET(x, v)  (HW_CAN_IMASK1_WR(x, HW_CAN_IMASK1_RD(x) |  (v)))
02130 #define HW_CAN_IMASK1_CLR(x, v)  (HW_CAN_IMASK1_WR(x, HW_CAN_IMASK1_RD(x) & ~(v)))
02131 #define HW_CAN_IMASK1_TOG(x, v)  (HW_CAN_IMASK1_WR(x, HW_CAN_IMASK1_RD(x) ^  (v)))
02132 /*@}*/
02133 
02134 /*
02135  * Constants & macros for individual CAN_IMASK1 bitfields
02136  */
02137 
02138 /*!
02139  * @name Register CAN_IMASK1, field BUFLM[31:0] (RW)
02140  *
02141  * Each bit enables or disables the corresponding FlexCAN Message Buffer
02142  * Interrupt for MB31 to MB0. Setting or clearing a bit in the IMASK1 Register can
02143  * assert or negate an interrupt request, if the corresponding IFLAG1 bit is set.
02144  *
02145  * Values:
02146  * - 0 - The corresponding buffer Interrupt is disabled.
02147  * - 1 - The corresponding buffer Interrupt is enabled.
02148  */
02149 /*@{*/
02150 #define BP_CAN_IMASK1_BUFLM  (0U)          /*!< Bit position for CAN_IMASK1_BUFLM. */
02151 #define BM_CAN_IMASK1_BUFLM  (0xFFFFFFFFU) /*!< Bit mask for CAN_IMASK1_BUFLM. */
02152 #define BS_CAN_IMASK1_BUFLM  (32U)         /*!< Bit field size in bits for CAN_IMASK1_BUFLM. */
02153 
02154 /*! @brief Read current value of the CAN_IMASK1_BUFLM field. */
02155 #define BR_CAN_IMASK1_BUFLM(x) (HW_CAN_IMASK1(x).U)
02156 
02157 /*! @brief Format value for bitfield CAN_IMASK1_BUFLM. */
02158 #define BF_CAN_IMASK1_BUFLM(v) ((uint32_t)((uint32_t)(v) << BP_CAN_IMASK1_BUFLM) & BM_CAN_IMASK1_BUFLM)
02159 
02160 /*! @brief Set the BUFLM field to a new value. */
02161 #define BW_CAN_IMASK1_BUFLM(x, v) (HW_CAN_IMASK1_WR(x, v))
02162 /*@}*/
02163 
02164 /*******************************************************************************
02165  * HW_CAN_IFLAG1 - Interrupt Flags 1 register
02166  ******************************************************************************/
02167 
02168 /*!
02169  * @brief HW_CAN_IFLAG1 - Interrupt Flags 1 register (W1C)
02170  *
02171  * Reset value: 0x00000000U
02172  *
02173  * This register defines the flags for the 32 Message Buffer interrupts for MB31
02174  * to MB0. It contains one interrupt flag bit per buffer. Each successful
02175  * transmission or reception sets the corresponding IFLAG1 bit. If the corresponding
02176  * IMASK1 bit is set, an interrupt will be generated. The interrupt flag must be
02177  * cleared by writing 1 to it. Writing 0 has no effect. The BUF7I to BUF5I flags
02178  * are also used to represent FIFO interrupts when the Rx FIFO is enabled. When the
02179  * bit MCR[RFEN] is set, the function of the 8 least significant interrupt flags
02180  * BUF[7:0]I changes: BUF7I, BUF6I and BUF5I indicate operating conditions of
02181  * the FIFO, and the BUF4TO0I field is reserved. Before enabling the RFEN, the CPU
02182  * must service the IFLAG bits asserted in the Rx FIFO region; see Section "Rx
02183  * FIFO". Otherwise, these IFLAG bits will mistakenly show the related MBs now
02184  * belonging to FIFO as having contents to be serviced. When the RFEN bit is negated,
02185  * the FIFO flags must be cleared. The same care must be taken when an RFFN
02186  * value is selected extending Rx FIFO filters beyond MB7. For example, when RFFN is
02187  * 0x8, the MB0-23 range is occupied by Rx FIFO filters and related IFLAG bits
02188  * must be cleared. Before updating MCR[MAXMB] field, CPU must service the IFLAG1
02189  * bits whose MB value is greater than the MCR[MAXMB] to be updated; otherwise,
02190  * they will remain set and be inconsistent with the number of MBs available.
02191  */
02192 typedef union _hw_can_iflag1
02193 {
02194     uint32_t U;
02195     struct _hw_can_iflag1_bitfields
02196     {
02197         uint32_t BUF0I : 1;            /*!< [0] Buffer MB0 Interrupt Or "reserved" */
02198         uint32_t BUF4TO1I : 4;         /*!< [4:1] Buffer MB i Interrupt Or "reserved"
02199                                         * */
02200         uint32_t BUF5I : 1;            /*!< [5] Buffer MB5 Interrupt Or "Frames
02201                                         * available in Rx FIFO" */
02202         uint32_t BUF6I : 1;            /*!< [6] Buffer MB6 Interrupt Or "Rx FIFO
02203                                         * Warning" */
02204         uint32_t BUF7I : 1;            /*!< [7] Buffer MB7 Interrupt Or "Rx FIFO
02205                                         * Overflow" */
02206         uint32_t BUF31TO8I : 24;       /*!< [31:8] Buffer MBi Interrupt */
02207     } B;
02208 } hw_can_iflag1_t;
02209 
02210 /*!
02211  * @name Constants and macros for entire CAN_IFLAG1 register
02212  */
02213 /*@{*/
02214 #define HW_CAN_IFLAG1_ADDR(x)    ((x) + 0x30U)
02215 
02216 #define HW_CAN_IFLAG1(x)         (*(__IO hw_can_iflag1_t *) HW_CAN_IFLAG1_ADDR(x))
02217 #define HW_CAN_IFLAG1_RD(x)      (ADDRESS_READ(hw_can_iflag1_t, HW_CAN_IFLAG1_ADDR(x)))
02218 #define HW_CAN_IFLAG1_WR(x, v)   (ADDRESS_WRITE(hw_can_iflag1_t, HW_CAN_IFLAG1_ADDR(x), v))
02219 #define HW_CAN_IFLAG1_SET(x, v)  (HW_CAN_IFLAG1_WR(x, HW_CAN_IFLAG1_RD(x) |  (v)))
02220 #define HW_CAN_IFLAG1_CLR(x, v)  (HW_CAN_IFLAG1_WR(x, HW_CAN_IFLAG1_RD(x) & ~(v)))
02221 #define HW_CAN_IFLAG1_TOG(x, v)  (HW_CAN_IFLAG1_WR(x, HW_CAN_IFLAG1_RD(x) ^  (v)))
02222 /*@}*/
02223 
02224 /*
02225  * Constants & macros for individual CAN_IFLAG1 bitfields
02226  */
02227 
02228 /*!
02229  * @name Register CAN_IFLAG1, field BUF0I[0] (W1C)
02230  *
02231  * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
02232  * the interrupt for MB0. This flag is cleared by the FlexCAN whenever the bit
02233  * MCR[RFEN] is changed by CPU writes. The BUF0I flag is reserved when MCR[RFEN] is
02234  * set.
02235  *
02236  * Values:
02237  * - 0 - The corresponding buffer has no occurrence of successfully completed
02238  *     transmission or reception when MCR[RFEN]=0.
02239  * - 1 - The corresponding buffer has successfully completed transmission or
02240  *     reception when MCR[RFEN]=0.
02241  */
02242 /*@{*/
02243 #define BP_CAN_IFLAG1_BUF0I  (0U)          /*!< Bit position for CAN_IFLAG1_BUF0I. */
02244 #define BM_CAN_IFLAG1_BUF0I  (0x00000001U) /*!< Bit mask for CAN_IFLAG1_BUF0I. */
02245 #define BS_CAN_IFLAG1_BUF0I  (1U)          /*!< Bit field size in bits for CAN_IFLAG1_BUF0I. */
02246 
02247 /*! @brief Read current value of the CAN_IFLAG1_BUF0I field. */
02248 #define BR_CAN_IFLAG1_BUF0I(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF0I)))
02249 
02250 /*! @brief Format value for bitfield CAN_IFLAG1_BUF0I. */
02251 #define BF_CAN_IFLAG1_BUF0I(v) ((uint32_t)((uint32_t)(v) << BP_CAN_IFLAG1_BUF0I) & BM_CAN_IFLAG1_BUF0I)
02252 
02253 /*! @brief Set the BUF0I field to a new value. */
02254 #define BW_CAN_IFLAG1_BUF0I(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF0I), v))
02255 /*@}*/
02256 
02257 /*!
02258  * @name Register CAN_IFLAG1, field BUF4TO1I[4:1] (W1C)
02259  *
02260  * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), these bits flag
02261  * the interrupts for MB4 to MB1. These flags are cleared by the FlexCAN whenever
02262  * the bit MCR[RFEN] is changed by CPU writes. The BUF4TO1I flags are reserved
02263  * when MCR[RFEN] is set.
02264  *
02265  * Values:
02266  * - 0 - The corresponding buffer has no occurrence of successfully completed
02267  *     transmission or reception when MCR[RFEN]=0.
02268  * - 1 - The corresponding buffer has successfully completed transmission or
02269  *     reception when MCR[RFEN]=0.
02270  */
02271 /*@{*/
02272 #define BP_CAN_IFLAG1_BUF4TO1I (1U)        /*!< Bit position for CAN_IFLAG1_BUF4TO1I. */
02273 #define BM_CAN_IFLAG1_BUF4TO1I (0x0000001EU) /*!< Bit mask for CAN_IFLAG1_BUF4TO1I. */
02274 #define BS_CAN_IFLAG1_BUF4TO1I (4U)        /*!< Bit field size in bits for CAN_IFLAG1_BUF4TO1I. */
02275 
02276 /*! @brief Read current value of the CAN_IFLAG1_BUF4TO1I field. */
02277 #define BR_CAN_IFLAG1_BUF4TO1I(x) (UNION_READ(hw_can_iflag1_t, HW_CAN_IFLAG1_ADDR(x), U, B.BUF4TO1I))
02278 
02279 /*! @brief Format value for bitfield CAN_IFLAG1_BUF4TO1I. */
02280 #define BF_CAN_IFLAG1_BUF4TO1I(v) ((uint32_t)((uint32_t)(v) << BP_CAN_IFLAG1_BUF4TO1I) & BM_CAN_IFLAG1_BUF4TO1I)
02281 
02282 /*! @brief Set the BUF4TO1I field to a new value. */
02283 #define BW_CAN_IFLAG1_BUF4TO1I(x, v) (HW_CAN_IFLAG1_WR(x, (HW_CAN_IFLAG1_RD(x) & ~BM_CAN_IFLAG1_BUF4TO1I) | BF_CAN_IFLAG1_BUF4TO1I(v)))
02284 /*@}*/
02285 
02286 /*!
02287  * @name Register CAN_IFLAG1, field BUF5I[5] (W1C)
02288  *
02289  * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
02290  * the interrupt for MB5. This flag is cleared by the FlexCAN whenever the bit
02291  * MCR[RFEN] is changed by CPU writes. The BUF5I flag represents "Frames available in
02292  * Rx FIFO" when MCR[RFEN] is set. In this case, the flag indicates that at
02293  * least one frame is available to be read from the Rx FIFO.
02294  *
02295  * Values:
02296  * - 0 - No occurrence of MB5 completing transmission/reception when
02297  *     MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1
02298  * - 1 - MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s)
02299  *     available in the Rx FIFO when MCR[RFEN]=1
02300  */
02301 /*@{*/
02302 #define BP_CAN_IFLAG1_BUF5I  (5U)          /*!< Bit position for CAN_IFLAG1_BUF5I. */
02303 #define BM_CAN_IFLAG1_BUF5I  (0x00000020U) /*!< Bit mask for CAN_IFLAG1_BUF5I. */
02304 #define BS_CAN_IFLAG1_BUF5I  (1U)          /*!< Bit field size in bits for CAN_IFLAG1_BUF5I. */
02305 
02306 /*! @brief Read current value of the CAN_IFLAG1_BUF5I field. */
02307 #define BR_CAN_IFLAG1_BUF5I(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF5I)))
02308 
02309 /*! @brief Format value for bitfield CAN_IFLAG1_BUF5I. */
02310 #define BF_CAN_IFLAG1_BUF5I(v) ((uint32_t)((uint32_t)(v) << BP_CAN_IFLAG1_BUF5I) & BM_CAN_IFLAG1_BUF5I)
02311 
02312 /*! @brief Set the BUF5I field to a new value. */
02313 #define BW_CAN_IFLAG1_BUF5I(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF5I), v))
02314 /*@}*/
02315 
02316 /*!
02317  * @name Register CAN_IFLAG1, field BUF6I[6] (W1C)
02318  *
02319  * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
02320  * the interrupt for MB6. This flag is cleared by the FlexCAN whenever the bit
02321  * MCR[RFEN] is changed by CPU writes. The BUF6I flag represents "Rx FIFO Warning"
02322  * when MCR[RFEN] is set. In this case, the flag indicates when the number of
02323  * unread messages within the Rx FIFO is increased to 5 from 4 due to the reception of
02324  * a new one, meaning that the Rx FIFO is almost full. Note that if the flag is
02325  * cleared while the number of unread messages is greater than 4, it does not
02326  * assert again until the number of unread messages within the Rx FIFO is decreased
02327  * to be equal to or less than 4.
02328  *
02329  * Values:
02330  * - 0 - No occurrence of MB6 completing transmission/reception when
02331  *     MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1
02332  * - 1 - MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO
02333  *     almost full when MCR[RFEN]=1
02334  */
02335 /*@{*/
02336 #define BP_CAN_IFLAG1_BUF6I  (6U)          /*!< Bit position for CAN_IFLAG1_BUF6I. */
02337 #define BM_CAN_IFLAG1_BUF6I  (0x00000040U) /*!< Bit mask for CAN_IFLAG1_BUF6I. */
02338 #define BS_CAN_IFLAG1_BUF6I  (1U)          /*!< Bit field size in bits for CAN_IFLAG1_BUF6I. */
02339 
02340 /*! @brief Read current value of the CAN_IFLAG1_BUF6I field. */
02341 #define BR_CAN_IFLAG1_BUF6I(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF6I)))
02342 
02343 /*! @brief Format value for bitfield CAN_IFLAG1_BUF6I. */
02344 #define BF_CAN_IFLAG1_BUF6I(v) ((uint32_t)((uint32_t)(v) << BP_CAN_IFLAG1_BUF6I) & BM_CAN_IFLAG1_BUF6I)
02345 
02346 /*! @brief Set the BUF6I field to a new value. */
02347 #define BW_CAN_IFLAG1_BUF6I(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF6I), v))
02348 /*@}*/
02349 
02350 /*!
02351  * @name Register CAN_IFLAG1, field BUF7I[7] (W1C)
02352  *
02353  * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
02354  * the interrupt for MB7. This flag is cleared by the FlexCAN whenever the bit
02355  * MCR[RFEN] is changed by CPU writes. The BUF7I flag represents "Rx FIFO Overflow"
02356  * when MCR[RFEN] is set. In this case, the flag indicates that a message was lost
02357  * because the Rx FIFO is full. Note that the flag will not be asserted when the
02358  * Rx FIFO is full and the message was captured by a Mailbox.
02359  *
02360  * Values:
02361  * - 0 - No occurrence of MB7 completing transmission/reception when
02362  *     MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1
02363  * - 1 - MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO
02364  *     overflow when MCR[RFEN]=1
02365  */
02366 /*@{*/
02367 #define BP_CAN_IFLAG1_BUF7I  (7U)          /*!< Bit position for CAN_IFLAG1_BUF7I. */
02368 #define BM_CAN_IFLAG1_BUF7I  (0x00000080U) /*!< Bit mask for CAN_IFLAG1_BUF7I. */
02369 #define BS_CAN_IFLAG1_BUF7I  (1U)          /*!< Bit field size in bits for CAN_IFLAG1_BUF7I. */
02370 
02371 /*! @brief Read current value of the CAN_IFLAG1_BUF7I field. */
02372 #define BR_CAN_IFLAG1_BUF7I(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF7I)))
02373 
02374 /*! @brief Format value for bitfield CAN_IFLAG1_BUF7I. */
02375 #define BF_CAN_IFLAG1_BUF7I(v) ((uint32_t)((uint32_t)(v) << BP_CAN_IFLAG1_BUF7I) & BM_CAN_IFLAG1_BUF7I)
02376 
02377 /*! @brief Set the BUF7I field to a new value. */
02378 #define BW_CAN_IFLAG1_BUF7I(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF7I), v))
02379 /*@}*/
02380 
02381 /*!
02382  * @name Register CAN_IFLAG1, field BUF31TO8I[31:8] (W1C)
02383  *
02384  * Each bit flags the corresponding FlexCAN Message Buffer interrupt for MB31 to
02385  * MB8.
02386  *
02387  * Values:
02388  * - 0 - The corresponding buffer has no occurrence of successfully completed
02389  *     transmission or reception.
02390  * - 1 - The corresponding buffer has successfully completed transmission or
02391  *     reception.
02392  */
02393 /*@{*/
02394 #define BP_CAN_IFLAG1_BUF31TO8I (8U)       /*!< Bit position for CAN_IFLAG1_BUF31TO8I. */
02395 #define BM_CAN_IFLAG1_BUF31TO8I (0xFFFFFF00U) /*!< Bit mask for CAN_IFLAG1_BUF31TO8I. */
02396 #define BS_CAN_IFLAG1_BUF31TO8I (24U)      /*!< Bit field size in bits for CAN_IFLAG1_BUF31TO8I. */
02397 
02398 /*! @brief Read current value of the CAN_IFLAG1_BUF31TO8I field. */
02399 #define BR_CAN_IFLAG1_BUF31TO8I(x) (UNION_READ(hw_can_iflag1_t, HW_CAN_IFLAG1_ADDR(x), U, B.BUF31TO8I))
02400 
02401 /*! @brief Format value for bitfield CAN_IFLAG1_BUF31TO8I. */
02402 #define BF_CAN_IFLAG1_BUF31TO8I(v) ((uint32_t)((uint32_t)(v) << BP_CAN_IFLAG1_BUF31TO8I) & BM_CAN_IFLAG1_BUF31TO8I)
02403 
02404 /*! @brief Set the BUF31TO8I field to a new value. */
02405 #define BW_CAN_IFLAG1_BUF31TO8I(x, v) (HW_CAN_IFLAG1_WR(x, (HW_CAN_IFLAG1_RD(x) & ~BM_CAN_IFLAG1_BUF31TO8I) | BF_CAN_IFLAG1_BUF31TO8I(v)))
02406 /*@}*/
02407 
02408 /*******************************************************************************
02409  * HW_CAN_CTRL2 - Control 2 register
02410  ******************************************************************************/
02411 
02412 /*!
02413  * @brief HW_CAN_CTRL2 - Control 2 register (RW)
02414  *
02415  * Reset value: 0x00B00000U
02416  *
02417  * This register contains control bits for CAN errors, FIFO features, and mode
02418  * selection.
02419  */
02420 typedef union _hw_can_ctrl2
02421 {
02422     uint32_t U;
02423     struct _hw_can_ctrl2_bitfields
02424     {
02425         uint32_t RESERVED0 : 16;       /*!< [15:0]  */
02426         uint32_t EACEN : 1;            /*!< [16] Entire Frame Arbitration Field
02427                                         * Comparison Enable For Rx Mailboxes */
02428         uint32_t RRS : 1;              /*!< [17] Remote Request Storing */
02429         uint32_t MRP : 1;              /*!< [18] Mailboxes Reception Priority */
02430         uint32_t TASD : 5;             /*!< [23:19] Tx Arbitration Start Delay */
02431         uint32_t RFFN : 4;             /*!< [27:24] Number Of Rx FIFO Filters */
02432         uint32_t WRMFRZ : 1;           /*!< [28] Write-Access To Memory In Freeze Mode
02433                                         * */
02434         uint32_t RESERVED1 : 3;        /*!< [31:29]  */
02435     } B;
02436 } hw_can_ctrl2_t;
02437 
02438 /*!
02439  * @name Constants and macros for entire CAN_CTRL2 register
02440  */
02441 /*@{*/
02442 #define HW_CAN_CTRL2_ADDR(x)     ((x) + 0x34U)
02443 
02444 #define HW_CAN_CTRL2(x)          (*(__IO hw_can_ctrl2_t *) HW_CAN_CTRL2_ADDR(x))
02445 #define HW_CAN_CTRL2_RD(x)       (ADDRESS_READ(hw_can_ctrl2_t, HW_CAN_CTRL2_ADDR(x)))
02446 #define HW_CAN_CTRL2_WR(x, v)    (ADDRESS_WRITE(hw_can_ctrl2_t, HW_CAN_CTRL2_ADDR(x), v))
02447 #define HW_CAN_CTRL2_SET(x, v)   (HW_CAN_CTRL2_WR(x, HW_CAN_CTRL2_RD(x) |  (v)))
02448 #define HW_CAN_CTRL2_CLR(x, v)   (HW_CAN_CTRL2_WR(x, HW_CAN_CTRL2_RD(x) & ~(v)))
02449 #define HW_CAN_CTRL2_TOG(x, v)   (HW_CAN_CTRL2_WR(x, HW_CAN_CTRL2_RD(x) ^  (v)))
02450 /*@}*/
02451 
02452 /*
02453  * Constants & macros for individual CAN_CTRL2 bitfields
02454  */
02455 
02456 /*!
02457  * @name Register CAN_CTRL2, field EACEN[16] (RW)
02458  *
02459  * This bit controls the comparison of IDE and RTR bits whithin Rx Mailboxes
02460  * filters with their corresponding bits in the incoming frame by the matching
02461  * process. This bit does not affect matching for Rx FIFO. This bit can be written
02462  * only in Freeze mode because it is blocked by hardware in other modes.
02463  *
02464  * Values:
02465  * - 0 - Rx Mailbox filter's IDE bit is always compared and RTR is never
02466  *     compared despite mask bits.
02467  * - 1 - Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with
02468  *     their corresponding bits within the incoming frame. Mask bits do apply.
02469  */
02470 /*@{*/
02471 #define BP_CAN_CTRL2_EACEN   (16U)         /*!< Bit position for CAN_CTRL2_EACEN. */
02472 #define BM_CAN_CTRL2_EACEN   (0x00010000U) /*!< Bit mask for CAN_CTRL2_EACEN. */
02473 #define BS_CAN_CTRL2_EACEN   (1U)          /*!< Bit field size in bits for CAN_CTRL2_EACEN. */
02474 
02475 /*! @brief Read current value of the CAN_CTRL2_EACEN field. */
02476 #define BR_CAN_CTRL2_EACEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_EACEN)))
02477 
02478 /*! @brief Format value for bitfield CAN_CTRL2_EACEN. */
02479 #define BF_CAN_CTRL2_EACEN(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL2_EACEN) & BM_CAN_CTRL2_EACEN)
02480 
02481 /*! @brief Set the EACEN field to a new value. */
02482 #define BW_CAN_CTRL2_EACEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_EACEN), v))
02483 /*@}*/
02484 
02485 /*!
02486  * @name Register CAN_CTRL2, field RRS[17] (RW)
02487  *
02488  * If this bit is asserted Remote Request Frame is submitted to a matching
02489  * process and stored in the corresponding Message Buffer in the same fashion of a
02490  * Data Frame. No automatic Remote Response Frame will be generated. If this bit is
02491  * negated the Remote Request Frame is submitted to a matching process and an
02492  * automatic Remote Response Frame is generated if a Message Buffer with CODE=0b1010
02493  * is found with the same ID. This bit can be written only in Freeze mode
02494  * because it is blocked by hardware in other modes.
02495  *
02496  * Values:
02497  * - 0 - Remote Response Frame is generated.
02498  * - 1 - Remote Request Frame is stored.
02499  */
02500 /*@{*/
02501 #define BP_CAN_CTRL2_RRS     (17U)         /*!< Bit position for CAN_CTRL2_RRS. */
02502 #define BM_CAN_CTRL2_RRS     (0x00020000U) /*!< Bit mask for CAN_CTRL2_RRS. */
02503 #define BS_CAN_CTRL2_RRS     (1U)          /*!< Bit field size in bits for CAN_CTRL2_RRS. */
02504 
02505 /*! @brief Read current value of the CAN_CTRL2_RRS field. */
02506 #define BR_CAN_CTRL2_RRS(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_RRS)))
02507 
02508 /*! @brief Format value for bitfield CAN_CTRL2_RRS. */
02509 #define BF_CAN_CTRL2_RRS(v)  ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL2_RRS) & BM_CAN_CTRL2_RRS)
02510 
02511 /*! @brief Set the RRS field to a new value. */
02512 #define BW_CAN_CTRL2_RRS(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_RRS), v))
02513 /*@}*/
02514 
02515 /*!
02516  * @name Register CAN_CTRL2, field MRP[18] (RW)
02517  *
02518  * If this bit is set the matching process starts from the Mailboxes and if no
02519  * match occurs the matching continues on the Rx FIFO. This bit can be written
02520  * only in Freeze mode because it is blocked by hardware in other modes.
02521  *
02522  * Values:
02523  * - 0 - Matching starts from Rx FIFO and continues on Mailboxes.
02524  * - 1 - Matching starts from Mailboxes and continues on Rx FIFO.
02525  */
02526 /*@{*/
02527 #define BP_CAN_CTRL2_MRP     (18U)         /*!< Bit position for CAN_CTRL2_MRP. */
02528 #define BM_CAN_CTRL2_MRP     (0x00040000U) /*!< Bit mask for CAN_CTRL2_MRP. */
02529 #define BS_CAN_CTRL2_MRP     (1U)          /*!< Bit field size in bits for CAN_CTRL2_MRP. */
02530 
02531 /*! @brief Read current value of the CAN_CTRL2_MRP field. */
02532 #define BR_CAN_CTRL2_MRP(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_MRP)))
02533 
02534 /*! @brief Format value for bitfield CAN_CTRL2_MRP. */
02535 #define BF_CAN_CTRL2_MRP(v)  ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL2_MRP) & BM_CAN_CTRL2_MRP)
02536 
02537 /*! @brief Set the MRP field to a new value. */
02538 #define BW_CAN_CTRL2_MRP(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_MRP), v))
02539 /*@}*/
02540 
02541 /*!
02542  * @name Register CAN_CTRL2, field TASD[23:19] (RW)
02543  *
02544  * This 5-bit field indicates how many CAN bits the Tx arbitration process start
02545  * point can be delayed from the first bit of CRC field on CAN bus. This field
02546  * can be written only in Freeze mode because it is blocked by hardware in other
02547  * modes. This field is useful to optimize the transmit performance based on
02548  * factors such as: peripheral/serial clock ratio, CAN bit timing and number of MBs.
02549  * The duration of an arbitration process, in terms of CAN bits, is directly
02550  * proportional to the number of available MBs and CAN baud rate and inversely
02551  * proportional to the peripheral clock frequency. The optimal arbitration timing is
02552  * that in which the last MB is scanned right before the first bit of the
02553  * Intermission field of a CAN frame. Therefore, if there are few MBs and the system/serial
02554  * clock ratio is high and the CAN baud rate is low then the arbitration can be
02555  * delayed and vice-versa. If TASD is 0 then the arbitration start is not
02556  * delayed, thus the CPU has less time to configure a Tx MB for the next arbitration,
02557  * but more time is reserved for arbitration. On the other hand, if TASD is 24 then
02558  * the CPU can configure a Tx MB later and less time is reserved for
02559  * arbitration. If too little time is reserved for arbitration the FlexCAN may be not able
02560  * to find winner MBs in time to compete with other nodes for the CAN bus. If the
02561  * arbitration ends too much time before the first bit of Intermission field then
02562  * there is a chance that the CPU reconfigures some Tx MBs and the winner MB is
02563  * not the best to be transmitted. The optimal configuration for TASD can be
02564  * calculated as: TASD = 25 - {f CANCLK * [MAXMB + 3 - (RFEN * 8) - (RFEN * RFFN *
02565  * 2)] * 2} / {f SYS * [1+(PSEG1+1)+(PSEG2+1)+(PROPSEG+1)] * (PRESDIV+1)} where: f
02566  * CANCLK is the Protocol Engine (PE) Clock (see section "Protocol Timing"), in
02567  * Hz f SYS is the peripheral clock, in Hz MAXMB is the value in CTRL1[MAXMB]
02568  * field RFEN is the value in CTRL1[RFEN] bit RFFN is the value in CTRL2[RFFN] field
02569  * PSEG1 is the value in CTRL1[PSEG1] field PSEG2 is the value in CTRL1[PSEG2]
02570  * field PROPSEG is the value in CTRL1[PROPSEG] field PRESDIV is the value in
02571  * CTRL1[PRESDIV] field See Section "Arbitration process" and Section "Protocol
02572  * Timing" for more details.
02573  */
02574 /*@{*/
02575 #define BP_CAN_CTRL2_TASD    (19U)         /*!< Bit position for CAN_CTRL2_TASD. */
02576 #define BM_CAN_CTRL2_TASD    (0x00F80000U) /*!< Bit mask for CAN_CTRL2_TASD. */
02577 #define BS_CAN_CTRL2_TASD    (5U)          /*!< Bit field size in bits for CAN_CTRL2_TASD. */
02578 
02579 /*! @brief Read current value of the CAN_CTRL2_TASD field. */
02580 #define BR_CAN_CTRL2_TASD(x) (UNION_READ(hw_can_ctrl2_t, HW_CAN_CTRL2_ADDR(x), U, B.TASD))
02581 
02582 /*! @brief Format value for bitfield CAN_CTRL2_TASD. */
02583 #define BF_CAN_CTRL2_TASD(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL2_TASD) & BM_CAN_CTRL2_TASD)
02584 
02585 /*! @brief Set the TASD field to a new value. */
02586 #define BW_CAN_CTRL2_TASD(x, v) (HW_CAN_CTRL2_WR(x, (HW_CAN_CTRL2_RD(x) & ~BM_CAN_CTRL2_TASD) | BF_CAN_CTRL2_TASD(v)))
02587 /*@}*/
02588 
02589 /*!
02590  * @name Register CAN_CTRL2, field RFFN[27:24] (RW)
02591  *
02592  * This 4-bit field defines the number of Rx FIFO filters, as shown in the
02593  * following table. The maximum selectable number of filters is determined by the MCU.
02594  * This field can only be written in Freeze mode as it is blocked by hardware in
02595  * other modes. This field must not be programmed with values that make the
02596  * number of Message Buffers occupied by Rx FIFO and ID Filter exceed the number of
02597  * Mailboxes present, defined by MCR[MAXMB]. Each group of eight filters occupies
02598  * a memory space equivalent to two Message Buffers which means that the more
02599  * filters are implemented the less Mailboxes will be available. Considering that
02600  * the Rx FIFO occupies the memory space originally reserved for MB0-5, RFFN should
02601  * be programmed with a value correponding to a number of filters not greater
02602  * than the number of available memory words which can be calculated as follows:
02603  * (SETUP_MB - 6) * 4 where SETUP_MB is the least between NUMBER_OF_MB and MAXMB.
02604  * The number of remaining Mailboxes available will be: (SETUP_MB - 8) - (RFFN *
02605  * 2) If the Number of Rx FIFO Filters programmed through RFFN exceeds the
02606  * SETUP_MB value (memory space available) the exceeding ones will not be functional.
02607  * RFFN[3:0] Number of Rx FIFO filters Message Buffers occupied by Rx FIFO and ID
02608  * Filter Table Remaining Available MailboxesThe number of the last remaining
02609  * available mailboxes is defined by the least value between the parameter
02610  * NUMBER_OF_MB minus 1 and the MCR[MAXMB] field. Rx FIFO ID Filter Table Elements Affected
02611  * by Rx Individual MasksIf Rx Individual Mask Registers are not enabled then
02612  * all Rx FIFO filters are affected by the Rx FIFO Global Mask. Rx FIFO ID Filter
02613  * Table Elements Affected by Rx FIFO Global Mask #rxfgmask-note 0x0 8 MB 0-7 MB
02614  * 8-63 Elements 0-7 none 0x1 16 MB 0-9 MB 10-63 Elements 0-9 Elements 10-15 0x2
02615  * 24 MB 0-11 MB 12-63 Elements 0-11 Elements 12-23 0x3 32 MB 0-13 MB 14-63
02616  * Elements 0-13 Elements 14-31 0x4 40 MB 0-15 MB 16-63 Elements 0-15 Elements 16-39
02617  * 0x5 48 MB 0-17 MB 18-63 Elements 0-17 Elements 18-47 0x6 56 MB 0-19 MB 20-63
02618  * Elements 0-19 Elements 20-55 0x7 64 MB 0-21 MB 22-63 Elements 0-21 Elements 22-63
02619  * 0x8 72 MB 0-23 MB 24-63 Elements 0-23 Elements 24-71 0x9 80 MB 0-25 MB 26-63
02620  * Elements 0-25 Elements 26-79 0xA 88 MB 0-27 MB 28-63 Elements 0-27 Elements
02621  * 28-87 0xB 96 MB 0-29 MB 30-63 Elements 0-29 Elements 30-95 0xC 104 MB 0-31 MB
02622  * 32-63 Elements 0-31 Elements 32-103 0xD 112 MB 0-33 MB 34-63 Elements 0-31
02623  * Elements 32-111 0xE 120 MB 0-35 MB 36-63 Elements 0-31 Elements 32-119 0xF 128 MB
02624  * 0-37 MB 38-63 Elements 0-31 Elements 32-127
02625  */
02626 /*@{*/
02627 #define BP_CAN_CTRL2_RFFN    (24U)         /*!< Bit position for CAN_CTRL2_RFFN. */
02628 #define BM_CAN_CTRL2_RFFN    (0x0F000000U) /*!< Bit mask for CAN_CTRL2_RFFN. */
02629 #define BS_CAN_CTRL2_RFFN    (4U)          /*!< Bit field size in bits for CAN_CTRL2_RFFN. */
02630 
02631 /*! @brief Read current value of the CAN_CTRL2_RFFN field. */
02632 #define BR_CAN_CTRL2_RFFN(x) (UNION_READ(hw_can_ctrl2_t, HW_CAN_CTRL2_ADDR(x), U, B.RFFN))
02633 
02634 /*! @brief Format value for bitfield CAN_CTRL2_RFFN. */
02635 #define BF_CAN_CTRL2_RFFN(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL2_RFFN) & BM_CAN_CTRL2_RFFN)
02636 
02637 /*! @brief Set the RFFN field to a new value. */
02638 #define BW_CAN_CTRL2_RFFN(x, v) (HW_CAN_CTRL2_WR(x, (HW_CAN_CTRL2_RD(x) & ~BM_CAN_CTRL2_RFFN) | BF_CAN_CTRL2_RFFN(v)))
02639 /*@}*/
02640 
02641 /*!
02642  * @name Register CAN_CTRL2, field WRMFRZ[28] (RW)
02643  *
02644  * Enable unrestricted write access to FlexCAN memory in Freeze mode. This bit
02645  * can only be written in Freeze mode and has no effect out of Freeze mode.
02646  *
02647  * Values:
02648  * - 0 - Maintain the write access restrictions.
02649  * - 1 - Enable unrestricted write access to FlexCAN memory.
02650  */
02651 /*@{*/
02652 #define BP_CAN_CTRL2_WRMFRZ  (28U)         /*!< Bit position for CAN_CTRL2_WRMFRZ. */
02653 #define BM_CAN_CTRL2_WRMFRZ  (0x10000000U) /*!< Bit mask for CAN_CTRL2_WRMFRZ. */
02654 #define BS_CAN_CTRL2_WRMFRZ  (1U)          /*!< Bit field size in bits for CAN_CTRL2_WRMFRZ. */
02655 
02656 /*! @brief Read current value of the CAN_CTRL2_WRMFRZ field. */
02657 #define BR_CAN_CTRL2_WRMFRZ(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_WRMFRZ)))
02658 
02659 /*! @brief Format value for bitfield CAN_CTRL2_WRMFRZ. */
02660 #define BF_CAN_CTRL2_WRMFRZ(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL2_WRMFRZ) & BM_CAN_CTRL2_WRMFRZ)
02661 
02662 /*! @brief Set the WRMFRZ field to a new value. */
02663 #define BW_CAN_CTRL2_WRMFRZ(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_WRMFRZ), v))
02664 /*@}*/
02665 
02666 /*******************************************************************************
02667  * HW_CAN_ESR2 - Error and Status 2 register
02668  ******************************************************************************/
02669 
02670 /*!
02671  * @brief HW_CAN_ESR2 - Error and Status 2 register (RO)
02672  *
02673  * Reset value: 0x00000000U
02674  *
02675  * This register reflects various interrupt flags and some general status.
02676  */
02677 typedef union _hw_can_esr2
02678 {
02679     uint32_t U;
02680     struct _hw_can_esr2_bitfields
02681     {
02682         uint32_t RESERVED0 : 13;       /*!< [12:0]  */
02683         uint32_t IMB : 1;              /*!< [13] Inactive Mailbox */
02684         uint32_t VPS : 1;              /*!< [14] Valid Priority Status */
02685         uint32_t RESERVED1 : 1;        /*!< [15]  */
02686         uint32_t LPTM : 7;             /*!< [22:16] Lowest Priority Tx Mailbox */
02687         uint32_t RESERVED2 : 9;        /*!< [31:23]  */
02688     } B;
02689 } hw_can_esr2_t;
02690 
02691 /*!
02692  * @name Constants and macros for entire CAN_ESR2 register
02693  */
02694 /*@{*/
02695 #define HW_CAN_ESR2_ADDR(x)      ((x) + 0x38U)
02696 
02697 #define HW_CAN_ESR2(x)           (*(__I hw_can_esr2_t *) HW_CAN_ESR2_ADDR(x))
02698 #define HW_CAN_ESR2_RD(x)        (ADDRESS_READ(hw_can_esr2_t, HW_CAN_ESR2_ADDR(x)))
02699 /*@}*/
02700 
02701 /*
02702  * Constants & macros for individual CAN_ESR2 bitfields
02703  */
02704 
02705 /*!
02706  * @name Register CAN_ESR2, field IMB[13] (RO)
02707  *
02708  * If ESR2[VPS] is asserted, this bit indicates whether there is any inactive
02709  * Mailbox (CODE field is either 0b1000 or 0b0000). This bit is asserted in the
02710  * following cases: During arbitration, if an LPTM is found and it is inactive. If
02711  * IMB is not asserted and a frame is transmitted successfully. This bit is
02712  * cleared in all start of arbitration (see Section "Arbitration process"). LPTM
02713  * mechanism have the following behavior: if an MB is successfully transmitted and
02714  * ESR2[IMB]=0 (no inactive Mailbox), then ESR2[VPS] and ESR2[IMB] are asserted and
02715  * the index related to the MB just transmitted is loaded into ESR2[LPTM].
02716  *
02717  * Values:
02718  * - 0 - If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox.
02719  * - 1 - If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM
02720  *     content is the number of the first one.
02721  */
02722 /*@{*/
02723 #define BP_CAN_ESR2_IMB      (13U)         /*!< Bit position for CAN_ESR2_IMB. */
02724 #define BM_CAN_ESR2_IMB      (0x00002000U) /*!< Bit mask for CAN_ESR2_IMB. */
02725 #define BS_CAN_ESR2_IMB      (1U)          /*!< Bit field size in bits for CAN_ESR2_IMB. */
02726 
02727 /*! @brief Read current value of the CAN_ESR2_IMB field. */
02728 #define BR_CAN_ESR2_IMB(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_CAN_ESR2_ADDR(x), BP_CAN_ESR2_IMB)))
02729 /*@}*/
02730 
02731 /*!
02732  * @name Register CAN_ESR2, field VPS[14] (RO)
02733  *
02734  * This bit indicates whether IMB and LPTM contents are currently valid or not.
02735  * VPS is asserted upon every complete Tx arbitration process unless the CPU
02736  * writes to Control and Status word of a Mailbox that has already been scanned, that
02737  * is, it is behind Tx Arbitration Pointer, during the Tx arbitration process.
02738  * If there is no inactive Mailbox and only one Tx Mailbox that is being
02739  * transmitted then VPS is not asserted. VPS is negated upon the start of every Tx
02740  * arbitration process or upon a write to Control and Status word of any Mailbox.
02741  * ESR2[VPS] is not affected by any CPU write into Control Status (C/S) of a MB that is
02742  * blocked by abort mechanism. When MCR[AEN] is asserted, the abort code write
02743  * in C/S of a MB that is being transmitted (pending abort), or any write attempt
02744  * into a Tx MB with IFLAG set is blocked.
02745  *
02746  * Values:
02747  * - 0 - Contents of IMB and LPTM are invalid.
02748  * - 1 - Contents of IMB and LPTM are valid.
02749  */
02750 /*@{*/
02751 #define BP_CAN_ESR2_VPS      (14U)         /*!< Bit position for CAN_ESR2_VPS. */
02752 #define BM_CAN_ESR2_VPS      (0x00004000U) /*!< Bit mask for CAN_ESR2_VPS. */
02753 #define BS_CAN_ESR2_VPS      (1U)          /*!< Bit field size in bits for CAN_ESR2_VPS. */
02754 
02755 /*! @brief Read current value of the CAN_ESR2_VPS field. */
02756 #define BR_CAN_ESR2_VPS(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_CAN_ESR2_ADDR(x), BP_CAN_ESR2_VPS)))
02757 /*@}*/
02758 
02759 /*!
02760  * @name Register CAN_ESR2, field LPTM[22:16] (RO)
02761  *
02762  * If ESR2[VPS] is asserted, this field indicates the lowest number inactive
02763  * Mailbox (see the IMB bit description). If there is no inactive Mailbox then the
02764  * Mailbox indicated depends on CTRL1[LBUF] bit value. If CTRL1[LBUF] bit is
02765  * negated then the Mailbox indicated is the one that has the greatest arbitration
02766  * value (see the "Highest priority Mailbox first" section). If CTRL1[LBUF] bit is
02767  * asserted then the Mailbox indicated is the highest number active Tx Mailbox. If
02768  * a Tx Mailbox is being transmitted it is not considered in LPTM calculation.
02769  * If ESR2[IMB] is not asserted and a frame is transmitted successfully, LPTM is
02770  * updated with its Mailbox number.
02771  */
02772 /*@{*/
02773 #define BP_CAN_ESR2_LPTM     (16U)         /*!< Bit position for CAN_ESR2_LPTM. */
02774 #define BM_CAN_ESR2_LPTM     (0x007F0000U) /*!< Bit mask for CAN_ESR2_LPTM. */
02775 #define BS_CAN_ESR2_LPTM     (7U)          /*!< Bit field size in bits for CAN_ESR2_LPTM. */
02776 
02777 /*! @brief Read current value of the CAN_ESR2_LPTM field. */
02778 #define BR_CAN_ESR2_LPTM(x)  (UNION_READ(hw_can_esr2_t, HW_CAN_ESR2_ADDR(x), U, B.LPTM))
02779 /*@}*/
02780 
02781 /*******************************************************************************
02782  * HW_CAN_CRCR - CRC Register
02783  ******************************************************************************/
02784 
02785 /*!
02786  * @brief HW_CAN_CRCR - CRC Register (RO)
02787  *
02788  * Reset value: 0x00000000U
02789  *
02790  * This register provides information about the CRC of transmitted messages.
02791  */
02792 typedef union _hw_can_crcr
02793 {
02794     uint32_t U;
02795     struct _hw_can_crcr_bitfields
02796     {
02797         uint32_t TXCRC : 15;           /*!< [14:0] CRC Transmitted */
02798         uint32_t RESERVED0 : 1;        /*!< [15]  */
02799         uint32_t MBCRC : 7;            /*!< [22:16] CRC Mailbox */
02800         uint32_t RESERVED1 : 9;        /*!< [31:23]  */
02801     } B;
02802 } hw_can_crcr_t;
02803 
02804 /*!
02805  * @name Constants and macros for entire CAN_CRCR register
02806  */
02807 /*@{*/
02808 #define HW_CAN_CRCR_ADDR(x)      ((x) + 0x44U)
02809 
02810 #define HW_CAN_CRCR(x)           (*(__I hw_can_crcr_t *) HW_CAN_CRCR_ADDR(x))
02811 #define HW_CAN_CRCR_RD(x)        (ADDRESS_READ(hw_can_crcr_t, HW_CAN_CRCR_ADDR(x)))
02812 /*@}*/
02813 
02814 /*
02815  * Constants & macros for individual CAN_CRCR bitfields
02816  */
02817 
02818 /*!
02819  * @name Register CAN_CRCR, field TXCRC[14:0] (RO)
02820  *
02821  * This field indicates the CRC value of the last message transmitted. This
02822  * field is updated at the same time the Tx Interrupt Flag is asserted.
02823  */
02824 /*@{*/
02825 #define BP_CAN_CRCR_TXCRC    (0U)          /*!< Bit position for CAN_CRCR_TXCRC. */
02826 #define BM_CAN_CRCR_TXCRC    (0x00007FFFU) /*!< Bit mask for CAN_CRCR_TXCRC. */
02827 #define BS_CAN_CRCR_TXCRC    (15U)         /*!< Bit field size in bits for CAN_CRCR_TXCRC. */
02828 
02829 /*! @brief Read current value of the CAN_CRCR_TXCRC field. */
02830 #define BR_CAN_CRCR_TXCRC(x) (UNION_READ(hw_can_crcr_t, HW_CAN_CRCR_ADDR(x), U, B.TXCRC))
02831 /*@}*/
02832 
02833 /*!
02834  * @name Register CAN_CRCR, field MBCRC[22:16] (RO)
02835  *
02836  * This field indicates the number of the Mailbox corresponding to the value in
02837  * TXCRC field.
02838  */
02839 /*@{*/
02840 #define BP_CAN_CRCR_MBCRC    (16U)         /*!< Bit position for CAN_CRCR_MBCRC. */
02841 #define BM_CAN_CRCR_MBCRC    (0x007F0000U) /*!< Bit mask for CAN_CRCR_MBCRC. */
02842 #define BS_CAN_CRCR_MBCRC    (7U)          /*!< Bit field size in bits for CAN_CRCR_MBCRC. */
02843 
02844 /*! @brief Read current value of the CAN_CRCR_MBCRC field. */
02845 #define BR_CAN_CRCR_MBCRC(x) (UNION_READ(hw_can_crcr_t, HW_CAN_CRCR_ADDR(x), U, B.MBCRC))
02846 /*@}*/
02847 
02848 /*******************************************************************************
02849  * HW_CAN_RXFGMASK - Rx FIFO Global Mask register
02850  ******************************************************************************/
02851 
02852 /*!
02853  * @brief HW_CAN_RXFGMASK - Rx FIFO Global Mask register (RW)
02854  *
02855  * Reset value: 0xFFFFFFFFU
02856  *
02857  * This register is located in RAM. If Rx FIFO is enabled RXFGMASK is used to
02858  * mask the Rx FIFO ID Filter Table elements that do not have a corresponding RXIMR
02859  * according to CTRL2[RFFN] field setting. This register can only be written in
02860  * Freeze mode as it is blocked by hardware in other modes.
02861  */
02862 typedef union _hw_can_rxfgmask
02863 {
02864     uint32_t U;
02865     struct _hw_can_rxfgmask_bitfields
02866     {
02867         uint32_t FGM : 32;             /*!< [31:0] Rx FIFO Global Mask Bits */
02868     } B;
02869 } hw_can_rxfgmask_t;
02870 
02871 /*!
02872  * @name Constants and macros for entire CAN_RXFGMASK register
02873  */
02874 /*@{*/
02875 #define HW_CAN_RXFGMASK_ADDR(x)  ((x) + 0x48U)
02876 
02877 #define HW_CAN_RXFGMASK(x)       (*(__IO hw_can_rxfgmask_t *) HW_CAN_RXFGMASK_ADDR(x))
02878 #define HW_CAN_RXFGMASK_RD(x)    (ADDRESS_READ(hw_can_rxfgmask_t, HW_CAN_RXFGMASK_ADDR(x)))
02879 #define HW_CAN_RXFGMASK_WR(x, v) (ADDRESS_WRITE(hw_can_rxfgmask_t, HW_CAN_RXFGMASK_ADDR(x), v))
02880 #define HW_CAN_RXFGMASK_SET(x, v) (HW_CAN_RXFGMASK_WR(x, HW_CAN_RXFGMASK_RD(x) |  (v)))
02881 #define HW_CAN_RXFGMASK_CLR(x, v) (HW_CAN_RXFGMASK_WR(x, HW_CAN_RXFGMASK_RD(x) & ~(v)))
02882 #define HW_CAN_RXFGMASK_TOG(x, v) (HW_CAN_RXFGMASK_WR(x, HW_CAN_RXFGMASK_RD(x) ^  (v)))
02883 /*@}*/
02884 
02885 /*
02886  * Constants & macros for individual CAN_RXFGMASK bitfields
02887  */
02888 
02889 /*!
02890  * @name Register CAN_RXFGMASK, field FGM[31:0] (RW)
02891  *
02892  * These bits mask the ID Filter Table elements bits in a perfect alignment. The
02893  * following table shows how the FGM bits correspond to each IDAF field. Rx FIFO
02894  * ID Filter Table Elements Format (MCR[IDAM]) Identifier Acceptance Filter
02895  * Fields RTR IDE RXIDA RXIDB If MCR[IDAM] field is equivalent to the format B only
02896  * the fourteen most significant bits of the Identifier of the incoming frame are
02897  * compared with the Rx FIFO filter. RXIDC If MCR[IDAM] field is equivalent to
02898  * the format C only the eight most significant bits of the Identifier of the
02899  * incoming frame are compared with the Rx FIFO filter. Reserved A FGM[31] FGM[30]
02900  * FGM[29:1] - - FGM[0] B FGM[31], FGM[15] FGM[30], FGM[14] - FGM[29:16], FGM[13:0]
02901  * - C - - - FGM[31:24], FGM[23:16], FGM[15:8], FGM[7:0]
02902  *
02903  * Values:
02904  * - 0 - The corresponding bit in the filter is "don't care."
02905  * - 1 - The corresponding bit in the filter is checked.
02906  */
02907 /*@{*/
02908 #define BP_CAN_RXFGMASK_FGM  (0U)          /*!< Bit position for CAN_RXFGMASK_FGM. */
02909 #define BM_CAN_RXFGMASK_FGM  (0xFFFFFFFFU) /*!< Bit mask for CAN_RXFGMASK_FGM. */
02910 #define BS_CAN_RXFGMASK_FGM  (32U)         /*!< Bit field size in bits for CAN_RXFGMASK_FGM. */
02911 
02912 /*! @brief Read current value of the CAN_RXFGMASK_FGM field. */
02913 #define BR_CAN_RXFGMASK_FGM(x) (HW_CAN_RXFGMASK(x).U)
02914 
02915 /*! @brief Format value for bitfield CAN_RXFGMASK_FGM. */
02916 #define BF_CAN_RXFGMASK_FGM(v) ((uint32_t)((uint32_t)(v) << BP_CAN_RXFGMASK_FGM) & BM_CAN_RXFGMASK_FGM)
02917 
02918 /*! @brief Set the FGM field to a new value. */
02919 #define BW_CAN_RXFGMASK_FGM(x, v) (HW_CAN_RXFGMASK_WR(x, v))
02920 /*@}*/
02921 
02922 /*******************************************************************************
02923  * HW_CAN_RXFIR - Rx FIFO Information Register
02924  ******************************************************************************/
02925 
02926 /*!
02927  * @brief HW_CAN_RXFIR - Rx FIFO Information Register (RO)
02928  *
02929  * Reset value: 0x00000000U
02930  *
02931  * RXFIR provides information on Rx FIFO. This register is the port through
02932  * which the CPU accesses the output of the RXFIR FIFO located in RAM. The RXFIR FIFO
02933  * is written by the FlexCAN whenever a new message is moved into the Rx FIFO as
02934  * well as its output is updated whenever the output of the Rx FIFO is updated
02935  * with the next message. See Section "Rx FIFO" for instructions on reading this
02936  * register.
02937  */
02938 typedef union _hw_can_rxfir
02939 {
02940     uint32_t U;
02941     struct _hw_can_rxfir_bitfields
02942     {
02943         uint32_t IDHIT : 9;            /*!< [8:0] Identifier Acceptance Filter Hit
02944                                         * Indicator */
02945         uint32_t RESERVED0 : 23;       /*!< [31:9]  */
02946     } B;
02947 } hw_can_rxfir_t;
02948 
02949 /*!
02950  * @name Constants and macros for entire CAN_RXFIR register
02951  */
02952 /*@{*/
02953 #define HW_CAN_RXFIR_ADDR(x)     ((x) + 0x4CU)
02954 
02955 #define HW_CAN_RXFIR(x)          (*(__I hw_can_rxfir_t *) HW_CAN_RXFIR_ADDR(x))
02956 #define HW_CAN_RXFIR_RD(x)       (ADDRESS_READ(hw_can_rxfir_t, HW_CAN_RXFIR_ADDR(x)))
02957 /*@}*/
02958 
02959 /*
02960  * Constants & macros for individual CAN_RXFIR bitfields
02961  */
02962 
02963 /*!
02964  * @name Register CAN_RXFIR, field IDHIT[8:0] (RO)
02965  *
02966  * This field indicates which Identifier Acceptance Filter was hit by the
02967  * received message that is in the output of the Rx FIFO. If multiple filters match the
02968  * incoming message ID then the first matching IDAF found (lowest number) by the
02969  * matching process is indicated. This field is valid only while the
02970  * IFLAG[BUF5I] is asserted.
02971  */
02972 /*@{*/
02973 #define BP_CAN_RXFIR_IDHIT   (0U)          /*!< Bit position for CAN_RXFIR_IDHIT. */
02974 #define BM_CAN_RXFIR_IDHIT   (0x000001FFU) /*!< Bit mask for CAN_RXFIR_IDHIT. */
02975 #define BS_CAN_RXFIR_IDHIT   (9U)          /*!< Bit field size in bits for CAN_RXFIR_IDHIT. */
02976 
02977 /*! @brief Read current value of the CAN_RXFIR_IDHIT field. */
02978 #define BR_CAN_RXFIR_IDHIT(x) (UNION_READ(hw_can_rxfir_t, HW_CAN_RXFIR_ADDR(x), U, B.IDHIT))
02979 /*@}*/
02980 
02981 /*******************************************************************************
02982  * HW_CAN_CSn - Message Buffer 0 CS Register
02983  ******************************************************************************/
02984 
02985 /*!
02986  * @brief HW_CAN_CSn - Message Buffer 0 CS Register (RW)
02987  *
02988  * Reset value: 0x00000000U
02989  */
02990 typedef union _hw_can_csn
02991 {
02992     uint32_t U;
02993     struct _hw_can_csn_bitfields
02994     {
02995         uint32_t TIME_STAMP : 16;      /*!< [15:0] Free-Running Counter Time
02996                                         * stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx
02997                                         * and Rx frames at the time when the beginning of the Identifier field
02998                                         * appears on the CAN bus. */
02999         uint32_t DLC : 4;              /*!< [19:16] Length of the data to be
03000                                         * stored/transmitted. */
03001         uint32_t RTR : 1;              /*!< [20] Remote Transmission Request. One/zero for
03002                                         * remote/data frame. */
03003         uint32_t IDE : 1;              /*!< [21] ID Extended. One/zero for
03004                                         * extended/standard format frame. */
03005         uint32_t SRR : 1;              /*!< [22] Substitute Remote Request. Contains a
03006                                         * fixed recessive bit. */
03007         uint32_t RESERVED0 : 1;        /*!< [23] Reserved */
03008         uint32_t CODE : 4;             /*!< [27:24] Reserved */
03009         uint32_t RESERVED1 : 4;        /*!< [31:28] Reserved */
03010     } B;
03011 } hw_can_csn_t;
03012 
03013 /*!
03014  * @name Constants and macros for entire CAN_CSn register
03015  */
03016 /*@{*/
03017 #define HW_CAN_CSn_COUNT (16U)
03018 
03019 #define HW_CAN_CSn_ADDR(x, n)    ((x) + 0x80U + (0x10U * (n)))
03020 
03021 #define HW_CAN_CSn(x, n)         (*(__IO hw_can_csn_t *) HW_CAN_CSn_ADDR(x, n))
03022 #define HW_CAN_CSn_RD(x, n)      (ADDRESS_READ(hw_can_csn_t, HW_CAN_CSn_ADDR(x, n)))
03023 #define HW_CAN_CSn_WR(x, n, v)   (ADDRESS_WRITE(hw_can_csn_t, HW_CAN_CSn_ADDR(x, n), v))
03024 #define HW_CAN_CSn_SET(x, n, v)  (HW_CAN_CSn_WR(x, n, HW_CAN_CSn_RD(x, n) |  (v)))
03025 #define HW_CAN_CSn_CLR(x, n, v)  (HW_CAN_CSn_WR(x, n, HW_CAN_CSn_RD(x, n) & ~(v)))
03026 #define HW_CAN_CSn_TOG(x, n, v)  (HW_CAN_CSn_WR(x, n, HW_CAN_CSn_RD(x, n) ^  (v)))
03027 /*@}*/
03028 
03029 /*
03030  * Constants & macros for individual CAN_CSn bitfields
03031  */
03032 
03033 /*!
03034  * @name Register CAN_CSn, field TIME_STAMP[15:0] (RW)
03035  */
03036 /*@{*/
03037 #define BP_CAN_CSn_TIME_STAMP (0U)         /*!< Bit position for CAN_CSn_TIME_STAMP. */
03038 #define BM_CAN_CSn_TIME_STAMP (0x0000FFFFU) /*!< Bit mask for CAN_CSn_TIME_STAMP. */
03039 #define BS_CAN_CSn_TIME_STAMP (16U)        /*!< Bit field size in bits for CAN_CSn_TIME_STAMP. */
03040 
03041 /*! @brief Read current value of the CAN_CSn_TIME_STAMP field. */
03042 #define BR_CAN_CSn_TIME_STAMP(x, n) (UNION_READ(hw_can_csn_t, HW_CAN_CSn_ADDR(x, n), U, B.TIME_STAMP))
03043 
03044 /*! @brief Format value for bitfield CAN_CSn_TIME_STAMP. */
03045 #define BF_CAN_CSn_TIME_STAMP(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CSn_TIME_STAMP) & BM_CAN_CSn_TIME_STAMP)
03046 
03047 /*! @brief Set the TIME_STAMP field to a new value. */
03048 #define BW_CAN_CSn_TIME_STAMP(x, n, v) (HW_CAN_CSn_WR(x, n, (HW_CAN_CSn_RD(x, n) & ~BM_CAN_CSn_TIME_STAMP) | BF_CAN_CSn_TIME_STAMP(v)))
03049 /*@}*/
03050 
03051 /*!
03052  * @name Register CAN_CSn, field DLC[19:16] (RW)
03053  */
03054 /*@{*/
03055 #define BP_CAN_CSn_DLC       (16U)         /*!< Bit position for CAN_CSn_DLC. */
03056 #define BM_CAN_CSn_DLC       (0x000F0000U) /*!< Bit mask for CAN_CSn_DLC. */
03057 #define BS_CAN_CSn_DLC       (4U)          /*!< Bit field size in bits for CAN_CSn_DLC. */
03058 
03059 /*! @brief Read current value of the CAN_CSn_DLC field. */
03060 #define BR_CAN_CSn_DLC(x, n) (UNION_READ(hw_can_csn_t, HW_CAN_CSn_ADDR(x, n), U, B.DLC))
03061 
03062 /*! @brief Format value for bitfield CAN_CSn_DLC. */
03063 #define BF_CAN_CSn_DLC(v)    ((uint32_t)((uint32_t)(v) << BP_CAN_CSn_DLC) & BM_CAN_CSn_DLC)
03064 
03065 /*! @brief Set the DLC field to a new value. */
03066 #define BW_CAN_CSn_DLC(x, n, v) (HW_CAN_CSn_WR(x, n, (HW_CAN_CSn_RD(x, n) & ~BM_CAN_CSn_DLC) | BF_CAN_CSn_DLC(v)))
03067 /*@}*/
03068 
03069 /*!
03070  * @name Register CAN_CSn, field RTR[20] (RW)
03071  */
03072 /*@{*/
03073 #define BP_CAN_CSn_RTR       (20U)         /*!< Bit position for CAN_CSn_RTR. */
03074 #define BM_CAN_CSn_RTR       (0x00100000U) /*!< Bit mask for CAN_CSn_RTR. */
03075 #define BS_CAN_CSn_RTR       (1U)          /*!< Bit field size in bits for CAN_CSn_RTR. */
03076 
03077 /*! @brief Read current value of the CAN_CSn_RTR field. */
03078 #define BR_CAN_CSn_RTR(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_CAN_CSn_ADDR(x, n), BP_CAN_CSn_RTR)))
03079 
03080 /*! @brief Format value for bitfield CAN_CSn_RTR. */
03081 #define BF_CAN_CSn_RTR(v)    ((uint32_t)((uint32_t)(v) << BP_CAN_CSn_RTR) & BM_CAN_CSn_RTR)
03082 
03083 /*! @brief Set the RTR field to a new value. */
03084 #define BW_CAN_CSn_RTR(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_CAN_CSn_ADDR(x, n), BP_CAN_CSn_RTR), v))
03085 /*@}*/
03086 
03087 /*!
03088  * @name Register CAN_CSn, field IDE[21] (RW)
03089  */
03090 /*@{*/
03091 #define BP_CAN_CSn_IDE       (21U)         /*!< Bit position for CAN_CSn_IDE. */
03092 #define BM_CAN_CSn_IDE       (0x00200000U) /*!< Bit mask for CAN_CSn_IDE. */
03093 #define BS_CAN_CSn_IDE       (1U)          /*!< Bit field size in bits for CAN_CSn_IDE. */
03094 
03095 /*! @brief Read current value of the CAN_CSn_IDE field. */
03096 #define BR_CAN_CSn_IDE(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_CAN_CSn_ADDR(x, n), BP_CAN_CSn_IDE)))
03097 
03098 /*! @brief Format value for bitfield CAN_CSn_IDE. */
03099 #define BF_CAN_CSn_IDE(v)    ((uint32_t)((uint32_t)(v) << BP_CAN_CSn_IDE) & BM_CAN_CSn_IDE)
03100 
03101 /*! @brief Set the IDE field to a new value. */
03102 #define BW_CAN_CSn_IDE(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_CAN_CSn_ADDR(x, n), BP_CAN_CSn_IDE), v))
03103 /*@}*/
03104 
03105 /*!
03106  * @name Register CAN_CSn, field SRR[22] (RW)
03107  */
03108 /*@{*/
03109 #define BP_CAN_CSn_SRR       (22U)         /*!< Bit position for CAN_CSn_SRR. */
03110 #define BM_CAN_CSn_SRR       (0x00400000U) /*!< Bit mask for CAN_CSn_SRR. */
03111 #define BS_CAN_CSn_SRR       (1U)          /*!< Bit field size in bits for CAN_CSn_SRR. */
03112 
03113 /*! @brief Read current value of the CAN_CSn_SRR field. */
03114 #define BR_CAN_CSn_SRR(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_CAN_CSn_ADDR(x, n), BP_CAN_CSn_SRR)))
03115 
03116 /*! @brief Format value for bitfield CAN_CSn_SRR. */
03117 #define BF_CAN_CSn_SRR(v)    ((uint32_t)((uint32_t)(v) << BP_CAN_CSn_SRR) & BM_CAN_CSn_SRR)
03118 
03119 /*! @brief Set the SRR field to a new value. */
03120 #define BW_CAN_CSn_SRR(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_CAN_CSn_ADDR(x, n), BP_CAN_CSn_SRR), v))
03121 /*@}*/
03122 
03123 /*!
03124  * @name Register CAN_CSn, field CODE[27:24] (RW)
03125  */
03126 /*@{*/
03127 #define BP_CAN_CSn_CODE      (24U)         /*!< Bit position for CAN_CSn_CODE. */
03128 #define BM_CAN_CSn_CODE      (0x0F000000U) /*!< Bit mask for CAN_CSn_CODE. */
03129 #define BS_CAN_CSn_CODE      (4U)          /*!< Bit field size in bits for CAN_CSn_CODE. */
03130 
03131 /*! @brief Read current value of the CAN_CSn_CODE field. */
03132 #define BR_CAN_CSn_CODE(x, n) (UNION_READ(hw_can_csn_t, HW_CAN_CSn_ADDR(x, n), U, B.CODE))
03133 
03134 /*! @brief Format value for bitfield CAN_CSn_CODE. */
03135 #define BF_CAN_CSn_CODE(v)   ((uint32_t)((uint32_t)(v) << BP_CAN_CSn_CODE) & BM_CAN_CSn_CODE)
03136 
03137 /*! @brief Set the CODE field to a new value. */
03138 #define BW_CAN_CSn_CODE(x, n, v) (HW_CAN_CSn_WR(x, n, (HW_CAN_CSn_RD(x, n) & ~BM_CAN_CSn_CODE) | BF_CAN_CSn_CODE(v)))
03139 /*@}*/
03140 /*******************************************************************************
03141  * HW_CAN_IDn - Message Buffer 0 ID Register
03142  ******************************************************************************/
03143 
03144 /*!
03145  * @brief HW_CAN_IDn - Message Buffer 0 ID Register (RW)
03146  *
03147  * Reset value: 0x00000000U
03148  */
03149 typedef union _hw_can_idn
03150 {
03151     uint32_t U;
03152     struct _hw_can_idn_bitfields
03153     {
03154         uint32_t EXT : 18;             /*!< [17:0] Contains extended (LOW word)
03155                                         * identifier of message buffer. */
03156         uint32_t STD : 11;             /*!< [28:18] Contains standard/extended (HIGH
03157                                         * word) identifier of message buffer. */
03158         uint32_t PRIO : 3;             /*!< [31:29] Local priority. This 3-bit fieldis
03159                                         * only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx
03160                                         * buffers. These bits are not transmitted. They are appended to the regular
03161                                         * ID to define the transmission priority. */
03162     } B;
03163 } hw_can_idn_t;
03164 
03165 /*!
03166  * @name Constants and macros for entire CAN_IDn register
03167  */
03168 /*@{*/
03169 #define HW_CAN_IDn_COUNT (16U)
03170 
03171 #define HW_CAN_IDn_ADDR(x, n)    ((x) + 0x84U + (0x10U * (n)))
03172 
03173 #define HW_CAN_IDn(x, n)         (*(__IO hw_can_idn_t *) HW_CAN_IDn_ADDR(x, n))
03174 #define HW_CAN_IDn_RD(x, n)      (ADDRESS_READ(hw_can_idn_t, HW_CAN_IDn_ADDR(x, n)))
03175 #define HW_CAN_IDn_WR(x, n, v)   (ADDRESS_WRITE(hw_can_idn_t, HW_CAN_IDn_ADDR(x, n), v))
03176 #define HW_CAN_IDn_SET(x, n, v)  (HW_CAN_IDn_WR(x, n, HW_CAN_IDn_RD(x, n) |  (v)))
03177 #define HW_CAN_IDn_CLR(x, n, v)  (HW_CAN_IDn_WR(x, n, HW_CAN_IDn_RD(x, n) & ~(v)))
03178 #define HW_CAN_IDn_TOG(x, n, v)  (HW_CAN_IDn_WR(x, n, HW_CAN_IDn_RD(x, n) ^  (v)))
03179 /*@}*/
03180 
03181 /*
03182  * Constants & macros for individual CAN_IDn bitfields
03183  */
03184 
03185 /*!
03186  * @name Register CAN_IDn, field EXT[17:0] (RW)
03187  */
03188 /*@{*/
03189 #define BP_CAN_IDn_EXT       (0U)          /*!< Bit position for CAN_IDn_EXT. */
03190 #define BM_CAN_IDn_EXT       (0x0003FFFFU) /*!< Bit mask for CAN_IDn_EXT. */
03191 #define BS_CAN_IDn_EXT       (18U)         /*!< Bit field size in bits for CAN_IDn_EXT. */
03192 
03193 /*! @brief Read current value of the CAN_IDn_EXT field. */
03194 #define BR_CAN_IDn_EXT(x, n) (UNION_READ(hw_can_idn_t, HW_CAN_IDn_ADDR(x, n), U, B.EXT))
03195 
03196 /*! @brief Format value for bitfield CAN_IDn_EXT. */
03197 #define BF_CAN_IDn_EXT(v)    ((uint32_t)((uint32_t)(v) << BP_CAN_IDn_EXT) & BM_CAN_IDn_EXT)
03198 
03199 /*! @brief Set the EXT field to a new value. */
03200 #define BW_CAN_IDn_EXT(x, n, v) (HW_CAN_IDn_WR(x, n, (HW_CAN_IDn_RD(x, n) & ~BM_CAN_IDn_EXT) | BF_CAN_IDn_EXT(v)))
03201 /*@}*/
03202 
03203 /*!
03204  * @name Register CAN_IDn, field STD[28:18] (RW)
03205  */
03206 /*@{*/
03207 #define BP_CAN_IDn_STD       (18U)         /*!< Bit position for CAN_IDn_STD. */
03208 #define BM_CAN_IDn_STD       (0x1FFC0000U) /*!< Bit mask for CAN_IDn_STD. */
03209 #define BS_CAN_IDn_STD       (11U)         /*!< Bit field size in bits for CAN_IDn_STD. */
03210 
03211 /*! @brief Read current value of the CAN_IDn_STD field. */
03212 #define BR_CAN_IDn_STD(x, n) (UNION_READ(hw_can_idn_t, HW_CAN_IDn_ADDR(x, n), U, B.STD))
03213 
03214 /*! @brief Format value for bitfield CAN_IDn_STD. */
03215 #define BF_CAN_IDn_STD(v)    ((uint32_t)((uint32_t)(v) << BP_CAN_IDn_STD) & BM_CAN_IDn_STD)
03216 
03217 /*! @brief Set the STD field to a new value. */
03218 #define BW_CAN_IDn_STD(x, n, v) (HW_CAN_IDn_WR(x, n, (HW_CAN_IDn_RD(x, n) & ~BM_CAN_IDn_STD) | BF_CAN_IDn_STD(v)))
03219 /*@}*/
03220 
03221 /*!
03222  * @name Register CAN_IDn, field PRIO[31:29] (RW)
03223  */
03224 /*@{*/
03225 #define BP_CAN_IDn_PRIO      (29U)         /*!< Bit position for CAN_IDn_PRIO. */
03226 #define BM_CAN_IDn_PRIO      (0xE0000000U) /*!< Bit mask for CAN_IDn_PRIO. */
03227 #define BS_CAN_IDn_PRIO      (3U)          /*!< Bit field size in bits for CAN_IDn_PRIO. */
03228 
03229 /*! @brief Read current value of the CAN_IDn_PRIO field. */
03230 #define BR_CAN_IDn_PRIO(x, n) (UNION_READ(hw_can_idn_t, HW_CAN_IDn_ADDR(x, n), U, B.PRIO))
03231 
03232 /*! @brief Format value for bitfield CAN_IDn_PRIO. */
03233 #define BF_CAN_IDn_PRIO(v)   ((uint32_t)((uint32_t)(v) << BP_CAN_IDn_PRIO) & BM_CAN_IDn_PRIO)
03234 
03235 /*! @brief Set the PRIO field to a new value. */
03236 #define BW_CAN_IDn_PRIO(x, n, v) (HW_CAN_IDn_WR(x, n, (HW_CAN_IDn_RD(x, n) & ~BM_CAN_IDn_PRIO) | BF_CAN_IDn_PRIO(v)))
03237 /*@}*/
03238 /*******************************************************************************
03239  * HW_CAN_WORD0n - Message Buffer 0 WORD0 Register
03240  ******************************************************************************/
03241 
03242 /*!
03243  * @brief HW_CAN_WORD0n - Message Buffer 0 WORD0 Register (RW)
03244  *
03245  * Reset value: 0x00000000U
03246  */
03247 typedef union _hw_can_word0n
03248 {
03249     uint32_t U;
03250     struct _hw_can_word0n_bitfields
03251     {
03252         uint32_t DATA_BYTE_3 : 8;      /*!< [7:0] Data byte 3 of Rx/Tx frame. */
03253         uint32_t DATA_BYTE_2 : 8;      /*!< [15:8] Data byte 2 of Rx/Tx frame. */
03254         uint32_t DATA_BYTE_1 : 8;      /*!< [23:16] Data byte 1 of Rx/Tx frame. */
03255         uint32_t DATA_BYTE_0 : 8;      /*!< [31:24] Data byte 0 of Rx/Tx frame. */
03256     } B;
03257 } hw_can_word0n_t;
03258 
03259 /*!
03260  * @name Constants and macros for entire CAN_WORD0n register
03261  */
03262 /*@{*/
03263 #define HW_CAN_WORD0n_COUNT (16U)
03264 
03265 #define HW_CAN_WORD0n_ADDR(x, n) ((x) + 0x88U + (0x10U * (n)))
03266 
03267 #define HW_CAN_WORD0n(x, n)      (*(__IO hw_can_word0n_t *) HW_CAN_WORD0n_ADDR(x, n))
03268 #define HW_CAN_WORD0n_RD(x, n)   (ADDRESS_READ(hw_can_word0n_t, HW_CAN_WORD0n_ADDR(x, n)))
03269 #define HW_CAN_WORD0n_WR(x, n, v) (ADDRESS_WRITE(hw_can_word0n_t, HW_CAN_WORD0n_ADDR(x, n), v))
03270 #define HW_CAN_WORD0n_SET(x, n, v) (HW_CAN_WORD0n_WR(x, n, HW_CAN_WORD0n_RD(x, n) |  (v)))
03271 #define HW_CAN_WORD0n_CLR(x, n, v) (HW_CAN_WORD0n_WR(x, n, HW_CAN_WORD0n_RD(x, n) & ~(v)))
03272 #define HW_CAN_WORD0n_TOG(x, n, v) (HW_CAN_WORD0n_WR(x, n, HW_CAN_WORD0n_RD(x, n) ^  (v)))
03273 /*@}*/
03274 
03275 /*
03276  * Constants & macros for individual CAN_WORD0n bitfields
03277  */
03278 
03279 /*!
03280  * @name Register CAN_WORD0n, field DATA_BYTE_3[7:0] (RW)
03281  */
03282 /*@{*/
03283 #define BP_CAN_WORD0n_DATA_BYTE_3 (0U)     /*!< Bit position for CAN_WORD0n_DATA_BYTE_3. */
03284 #define BM_CAN_WORD0n_DATA_BYTE_3 (0x000000FFU) /*!< Bit mask for CAN_WORD0n_DATA_BYTE_3. */
03285 #define BS_CAN_WORD0n_DATA_BYTE_3 (8U)     /*!< Bit field size in bits for CAN_WORD0n_DATA_BYTE_3. */
03286 
03287 /*! @brief Read current value of the CAN_WORD0n_DATA_BYTE_3 field. */
03288 #define BR_CAN_WORD0n_DATA_BYTE_3(x, n) (UNION_READ(hw_can_word0n_t, HW_CAN_WORD0n_ADDR(x, n), U, B.DATA_BYTE_3))
03289 
03290 /*! @brief Format value for bitfield CAN_WORD0n_DATA_BYTE_3. */
03291 #define BF_CAN_WORD0n_DATA_BYTE_3(v) ((uint32_t)((uint32_t)(v) << BP_CAN_WORD0n_DATA_BYTE_3) & BM_CAN_WORD0n_DATA_BYTE_3)
03292 
03293 /*! @brief Set the DATA_BYTE_3 field to a new value. */
03294 #define BW_CAN_WORD0n_DATA_BYTE_3(x, n, v) (HW_CAN_WORD0n_WR(x, n, (HW_CAN_WORD0n_RD(x, n) & ~BM_CAN_WORD0n_DATA_BYTE_3) | BF_CAN_WORD0n_DATA_BYTE_3(v)))
03295 /*@}*/
03296 
03297 /*!
03298  * @name Register CAN_WORD0n, field DATA_BYTE_2[15:8] (RW)
03299  */
03300 /*@{*/
03301 #define BP_CAN_WORD0n_DATA_BYTE_2 (8U)     /*!< Bit position for CAN_WORD0n_DATA_BYTE_2. */
03302 #define BM_CAN_WORD0n_DATA_BYTE_2 (0x0000FF00U) /*!< Bit mask for CAN_WORD0n_DATA_BYTE_2. */
03303 #define BS_CAN_WORD0n_DATA_BYTE_2 (8U)     /*!< Bit field size in bits for CAN_WORD0n_DATA_BYTE_2. */
03304 
03305 /*! @brief Read current value of the CAN_WORD0n_DATA_BYTE_2 field. */
03306 #define BR_CAN_WORD0n_DATA_BYTE_2(x, n) (UNION_READ(hw_can_word0n_t, HW_CAN_WORD0n_ADDR(x, n), U, B.DATA_BYTE_2))
03307 
03308 /*! @brief Format value for bitfield CAN_WORD0n_DATA_BYTE_2. */
03309 #define BF_CAN_WORD0n_DATA_BYTE_2(v) ((uint32_t)((uint32_t)(v) << BP_CAN_WORD0n_DATA_BYTE_2) & BM_CAN_WORD0n_DATA_BYTE_2)
03310 
03311 /*! @brief Set the DATA_BYTE_2 field to a new value. */
03312 #define BW_CAN_WORD0n_DATA_BYTE_2(x, n, v) (HW_CAN_WORD0n_WR(x, n, (HW_CAN_WORD0n_RD(x, n) & ~BM_CAN_WORD0n_DATA_BYTE_2) | BF_CAN_WORD0n_DATA_BYTE_2(v)))
03313 /*@}*/
03314 
03315 /*!
03316  * @name Register CAN_WORD0n, field DATA_BYTE_1[23:16] (RW)
03317  */
03318 /*@{*/
03319 #define BP_CAN_WORD0n_DATA_BYTE_1 (16U)    /*!< Bit position for CAN_WORD0n_DATA_BYTE_1. */
03320 #define BM_CAN_WORD0n_DATA_BYTE_1 (0x00FF0000U) /*!< Bit mask for CAN_WORD0n_DATA_BYTE_1. */
03321 #define BS_CAN_WORD0n_DATA_BYTE_1 (8U)     /*!< Bit field size in bits for CAN_WORD0n_DATA_BYTE_1. */
03322 
03323 /*! @brief Read current value of the CAN_WORD0n_DATA_BYTE_1 field. */
03324 #define BR_CAN_WORD0n_DATA_BYTE_1(x, n) (UNION_READ(hw_can_word0n_t, HW_CAN_WORD0n_ADDR(x, n), U, B.DATA_BYTE_1))
03325 
03326 /*! @brief Format value for bitfield CAN_WORD0n_DATA_BYTE_1. */
03327 #define BF_CAN_WORD0n_DATA_BYTE_1(v) ((uint32_t)((uint32_t)(v) << BP_CAN_WORD0n_DATA_BYTE_1) & BM_CAN_WORD0n_DATA_BYTE_1)
03328 
03329 /*! @brief Set the DATA_BYTE_1 field to a new value. */
03330 #define BW_CAN_WORD0n_DATA_BYTE_1(x, n, v) (HW_CAN_WORD0n_WR(x, n, (HW_CAN_WORD0n_RD(x, n) & ~BM_CAN_WORD0n_DATA_BYTE_1) | BF_CAN_WORD0n_DATA_BYTE_1(v)))
03331 /*@}*/
03332 
03333 /*!
03334  * @name Register CAN_WORD0n, field DATA_BYTE_0[31:24] (RW)
03335  */
03336 /*@{*/
03337 #define BP_CAN_WORD0n_DATA_BYTE_0 (24U)    /*!< Bit position for CAN_WORD0n_DATA_BYTE_0. */
03338 #define BM_CAN_WORD0n_DATA_BYTE_0 (0xFF000000U) /*!< Bit mask for CAN_WORD0n_DATA_BYTE_0. */
03339 #define BS_CAN_WORD0n_DATA_BYTE_0 (8U)     /*!< Bit field size in bits for CAN_WORD0n_DATA_BYTE_0. */
03340 
03341 /*! @brief Read current value of the CAN_WORD0n_DATA_BYTE_0 field. */
03342 #define BR_CAN_WORD0n_DATA_BYTE_0(x, n) (UNION_READ(hw_can_word0n_t, HW_CAN_WORD0n_ADDR(x, n), U, B.DATA_BYTE_0))
03343 
03344 /*! @brief Format value for bitfield CAN_WORD0n_DATA_BYTE_0. */
03345 #define BF_CAN_WORD0n_DATA_BYTE_0(v) ((uint32_t)((uint32_t)(v) << BP_CAN_WORD0n_DATA_BYTE_0) & BM_CAN_WORD0n_DATA_BYTE_0)
03346 
03347 /*! @brief Set the DATA_BYTE_0 field to a new value. */
03348 #define BW_CAN_WORD0n_DATA_BYTE_0(x, n, v) (HW_CAN_WORD0n_WR(x, n, (HW_CAN_WORD0n_RD(x, n) & ~BM_CAN_WORD0n_DATA_BYTE_0) | BF_CAN_WORD0n_DATA_BYTE_0(v)))
03349 /*@}*/
03350 /*******************************************************************************
03351  * HW_CAN_WORD1n - Message Buffer 0 WORD1 Register
03352  ******************************************************************************/
03353 
03354 /*!
03355  * @brief HW_CAN_WORD1n - Message Buffer 0 WORD1 Register (RW)
03356  *
03357  * Reset value: 0x00000000U
03358  */
03359 typedef union _hw_can_word1n
03360 {
03361     uint32_t U;
03362     struct _hw_can_word1n_bitfields
03363     {
03364         uint32_t DATA_BYTE_7 : 8;      /*!< [7:0] Data byte 7 of Rx/Tx frame. */
03365         uint32_t DATA_BYTE_6 : 8;      /*!< [15:8] Data byte 6 of Rx/Tx frame. */
03366         uint32_t DATA_BYTE_5 : 8;      /*!< [23:16] Data byte 5 of Rx/Tx frame. */
03367         uint32_t DATA_BYTE_4 : 8;      /*!< [31:24] Data byte 4 of Rx/Tx frame. */
03368     } B;
03369 } hw_can_word1n_t;
03370 
03371 /*!
03372  * @name Constants and macros for entire CAN_WORD1n register
03373  */
03374 /*@{*/
03375 #define HW_CAN_WORD1n_COUNT (16U)
03376 
03377 #define HW_CAN_WORD1n_ADDR(x, n) ((x) + 0x8CU + (0x10U * (n)))
03378 
03379 #define HW_CAN_WORD1n(x, n)      (*(__IO hw_can_word1n_t *) HW_CAN_WORD1n_ADDR(x, n))
03380 #define HW_CAN_WORD1n_RD(x, n)   (ADDRESS_READ(hw_can_word1n_t, HW_CAN_WORD1n_ADDR(x, n)))
03381 #define HW_CAN_WORD1n_WR(x, n, v) (ADDRESS_WRITE(hw_can_word1n_t, HW_CAN_WORD1n_ADDR(x, n), v))
03382 #define HW_CAN_WORD1n_SET(x, n, v) (HW_CAN_WORD1n_WR(x, n, HW_CAN_WORD1n_RD(x, n) |  (v)))
03383 #define HW_CAN_WORD1n_CLR(x, n, v) (HW_CAN_WORD1n_WR(x, n, HW_CAN_WORD1n_RD(x, n) & ~(v)))
03384 #define HW_CAN_WORD1n_TOG(x, n, v) (HW_CAN_WORD1n_WR(x, n, HW_CAN_WORD1n_RD(x, n) ^  (v)))
03385 /*@}*/
03386 
03387 /*
03388  * Constants & macros for individual CAN_WORD1n bitfields
03389  */
03390 
03391 /*!
03392  * @name Register CAN_WORD1n, field DATA_BYTE_7[7:0] (RW)
03393  */
03394 /*@{*/
03395 #define BP_CAN_WORD1n_DATA_BYTE_7 (0U)     /*!< Bit position for CAN_WORD1n_DATA_BYTE_7. */
03396 #define BM_CAN_WORD1n_DATA_BYTE_7 (0x000000FFU) /*!< Bit mask for CAN_WORD1n_DATA_BYTE_7. */
03397 #define BS_CAN_WORD1n_DATA_BYTE_7 (8U)     /*!< Bit field size in bits for CAN_WORD1n_DATA_BYTE_7. */
03398 
03399 /*! @brief Read current value of the CAN_WORD1n_DATA_BYTE_7 field. */
03400 #define BR_CAN_WORD1n_DATA_BYTE_7(x, n) (UNION_READ(hw_can_word1n_t, HW_CAN_WORD1n_ADDR(x, n), U, B.DATA_BYTE_7))
03401 
03402 /*! @brief Format value for bitfield CAN_WORD1n_DATA_BYTE_7. */
03403 #define BF_CAN_WORD1n_DATA_BYTE_7(v) ((uint32_t)((uint32_t)(v) << BP_CAN_WORD1n_DATA_BYTE_7) & BM_CAN_WORD1n_DATA_BYTE_7)
03404 
03405 /*! @brief Set the DATA_BYTE_7 field to a new value. */
03406 #define BW_CAN_WORD1n_DATA_BYTE_7(x, n, v) (HW_CAN_WORD1n_WR(x, n, (HW_CAN_WORD1n_RD(x, n) & ~BM_CAN_WORD1n_DATA_BYTE_7) | BF_CAN_WORD1n_DATA_BYTE_7(v)))
03407 /*@}*/
03408 
03409 /*!
03410  * @name Register CAN_WORD1n, field DATA_BYTE_6[15:8] (RW)
03411  */
03412 /*@{*/
03413 #define BP_CAN_WORD1n_DATA_BYTE_6 (8U)     /*!< Bit position for CAN_WORD1n_DATA_BYTE_6. */
03414 #define BM_CAN_WORD1n_DATA_BYTE_6 (0x0000FF00U) /*!< Bit mask for CAN_WORD1n_DATA_BYTE_6. */
03415 #define BS_CAN_WORD1n_DATA_BYTE_6 (8U)     /*!< Bit field size in bits for CAN_WORD1n_DATA_BYTE_6. */
03416 
03417 /*! @brief Read current value of the CAN_WORD1n_DATA_BYTE_6 field. */
03418 #define BR_CAN_WORD1n_DATA_BYTE_6(x, n) (UNION_READ(hw_can_word1n_t, HW_CAN_WORD1n_ADDR(x, n), U, B.DATA_BYTE_6))
03419 
03420 /*! @brief Format value for bitfield CAN_WORD1n_DATA_BYTE_6. */
03421 #define BF_CAN_WORD1n_DATA_BYTE_6(v) ((uint32_t)((uint32_t)(v) << BP_CAN_WORD1n_DATA_BYTE_6) & BM_CAN_WORD1n_DATA_BYTE_6)
03422 
03423 /*! @brief Set the DATA_BYTE_6 field to a new value. */
03424 #define BW_CAN_WORD1n_DATA_BYTE_6(x, n, v) (HW_CAN_WORD1n_WR(x, n, (HW_CAN_WORD1n_RD(x, n) & ~BM_CAN_WORD1n_DATA_BYTE_6) | BF_CAN_WORD1n_DATA_BYTE_6(v)))
03425 /*@}*/
03426 
03427 /*!
03428  * @name Register CAN_WORD1n, field DATA_BYTE_5[23:16] (RW)
03429  */
03430 /*@{*/
03431 #define BP_CAN_WORD1n_DATA_BYTE_5 (16U)    /*!< Bit position for CAN_WORD1n_DATA_BYTE_5. */
03432 #define BM_CAN_WORD1n_DATA_BYTE_5 (0x00FF0000U) /*!< Bit mask for CAN_WORD1n_DATA_BYTE_5. */
03433 #define BS_CAN_WORD1n_DATA_BYTE_5 (8U)     /*!< Bit field size in bits for CAN_WORD1n_DATA_BYTE_5. */
03434 
03435 /*! @brief Read current value of the CAN_WORD1n_DATA_BYTE_5 field. */
03436 #define BR_CAN_WORD1n_DATA_BYTE_5(x, n) (UNION_READ(hw_can_word1n_t, HW_CAN_WORD1n_ADDR(x, n), U, B.DATA_BYTE_5))
03437 
03438 /*! @brief Format value for bitfield CAN_WORD1n_DATA_BYTE_5. */
03439 #define BF_CAN_WORD1n_DATA_BYTE_5(v) ((uint32_t)((uint32_t)(v) << BP_CAN_WORD1n_DATA_BYTE_5) & BM_CAN_WORD1n_DATA_BYTE_5)
03440 
03441 /*! @brief Set the DATA_BYTE_5 field to a new value. */
03442 #define BW_CAN_WORD1n_DATA_BYTE_5(x, n, v) (HW_CAN_WORD1n_WR(x, n, (HW_CAN_WORD1n_RD(x, n) & ~BM_CAN_WORD1n_DATA_BYTE_5) | BF_CAN_WORD1n_DATA_BYTE_5(v)))
03443 /*@}*/
03444 
03445 /*!
03446  * @name Register CAN_WORD1n, field DATA_BYTE_4[31:24] (RW)
03447  */
03448 /*@{*/
03449 #define BP_CAN_WORD1n_DATA_BYTE_4 (24U)    /*!< Bit position for CAN_WORD1n_DATA_BYTE_4. */
03450 #define BM_CAN_WORD1n_DATA_BYTE_4 (0xFF000000U) /*!< Bit mask for CAN_WORD1n_DATA_BYTE_4. */
03451 #define BS_CAN_WORD1n_DATA_BYTE_4 (8U)     /*!< Bit field size in bits for CAN_WORD1n_DATA_BYTE_4. */
03452 
03453 /*! @brief Read current value of the CAN_WORD1n_DATA_BYTE_4 field. */
03454 #define BR_CAN_WORD1n_DATA_BYTE_4(x, n) (UNION_READ(hw_can_word1n_t, HW_CAN_WORD1n_ADDR(x, n), U, B.DATA_BYTE_4))
03455 
03456 /*! @brief Format value for bitfield CAN_WORD1n_DATA_BYTE_4. */
03457 #define BF_CAN_WORD1n_DATA_BYTE_4(v) ((uint32_t)((uint32_t)(v) << BP_CAN_WORD1n_DATA_BYTE_4) & BM_CAN_WORD1n_DATA_BYTE_4)
03458 
03459 /*! @brief Set the DATA_BYTE_4 field to a new value. */
03460 #define BW_CAN_WORD1n_DATA_BYTE_4(x, n, v) (HW_CAN_WORD1n_WR(x, n, (HW_CAN_WORD1n_RD(x, n) & ~BM_CAN_WORD1n_DATA_BYTE_4) | BF_CAN_WORD1n_DATA_BYTE_4(v)))
03461 /*@}*/
03462 
03463 /*******************************************************************************
03464  * HW_CAN_RXIMRn - Rx Individual Mask Registers
03465  ******************************************************************************/
03466 
03467 /*!
03468  * @brief HW_CAN_RXIMRn - Rx Individual Mask Registers (RW)
03469  *
03470  * Reset value: 0x00000000U
03471  *
03472  * These registers are located in RAM. RXIMR are used as acceptance masks for ID
03473  * filtering in Rx MBs and the Rx FIFO. If the Rx FIFO is not enabled, one mask
03474  * register is provided for each available Mailbox, providing ID masking
03475  * capability on a per Mailbox basis. When the Rx FIFO is enabled (MCR[RFEN] bit is
03476  * asserted), up to 32 Rx Individual Mask Registers can apply to the Rx FIFO ID Filter
03477  * Table elements on a one-to-one correspondence depending on the setting of
03478  * CTRL2[RFFN]. RXIMR can only be written by the CPU while the module is in Freeze
03479  * mode; otherwise, they are blocked by hardware. The Individual Rx Mask Registers
03480  * are not affected by reset and must be explicitly initialized prior to any
03481  * reception.
03482  */
03483 typedef union _hw_can_rximrn
03484 {
03485     uint32_t U;
03486     struct _hw_can_rximrn_bitfields
03487     {
03488         uint32_t MI : 32;              /*!< [31:0] Individual Mask Bits */
03489     } B;
03490 } hw_can_rximrn_t;
03491 
03492 /*!
03493  * @name Constants and macros for entire CAN_RXIMRn register
03494  */
03495 /*@{*/
03496 #define HW_CAN_RXIMRn_COUNT (16U)
03497 
03498 #define HW_CAN_RXIMRn_ADDR(x, n) ((x) + 0x880U + (0x4U * (n)))
03499 
03500 #define HW_CAN_RXIMRn(x, n)      (*(__IO hw_can_rximrn_t *) HW_CAN_RXIMRn_ADDR(x, n))
03501 #define HW_CAN_RXIMRn_RD(x, n)   (ADDRESS_READ(hw_can_rximrn_t, HW_CAN_RXIMRn_ADDR(x, n)))
03502 #define HW_CAN_RXIMRn_WR(x, n, v) (ADDRESS_WRITE(hw_can_rximrn_t, HW_CAN_RXIMRn_ADDR(x, n), v))
03503 #define HW_CAN_RXIMRn_SET(x, n, v) (HW_CAN_RXIMRn_WR(x, n, HW_CAN_RXIMRn_RD(x, n) |  (v)))
03504 #define HW_CAN_RXIMRn_CLR(x, n, v) (HW_CAN_RXIMRn_WR(x, n, HW_CAN_RXIMRn_RD(x, n) & ~(v)))
03505 #define HW_CAN_RXIMRn_TOG(x, n, v) (HW_CAN_RXIMRn_WR(x, n, HW_CAN_RXIMRn_RD(x, n) ^  (v)))
03506 /*@}*/
03507 
03508 /*
03509  * Constants & macros for individual CAN_RXIMRn bitfields
03510  */
03511 
03512 /*!
03513  * @name Register CAN_RXIMRn, field MI[31:0] (RW)
03514  *
03515  * Each Individual Mask Bit masks the corresponding bit in both the Mailbox
03516  * filter and Rx FIFO ID Filter Table element in distinct ways. For Mailbox filters,
03517  * see the RXMGMASK register description. For Rx FIFO ID Filter Table elements,
03518  * see the RXFGMASK register description.
03519  *
03520  * Values:
03521  * - 0 - The corresponding bit in the filter is "don't care."
03522  * - 1 - The corresponding bit in the filter is checked.
03523  */
03524 /*@{*/
03525 #define BP_CAN_RXIMRn_MI     (0U)          /*!< Bit position for CAN_RXIMRn_MI. */
03526 #define BM_CAN_RXIMRn_MI     (0xFFFFFFFFU) /*!< Bit mask for CAN_RXIMRn_MI. */
03527 #define BS_CAN_RXIMRn_MI     (32U)         /*!< Bit field size in bits for CAN_RXIMRn_MI. */
03528 
03529 /*! @brief Read current value of the CAN_RXIMRn_MI field. */
03530 #define BR_CAN_RXIMRn_MI(x, n) (HW_CAN_RXIMRn(x, n).U)
03531 
03532 /*! @brief Format value for bitfield CAN_RXIMRn_MI. */
03533 #define BF_CAN_RXIMRn_MI(v)  ((uint32_t)((uint32_t)(v) << BP_CAN_RXIMRn_MI) & BM_CAN_RXIMRn_MI)
03534 
03535 /*! @brief Set the MI field to a new value. */
03536 #define BW_CAN_RXIMRn_MI(x, n, v) (HW_CAN_RXIMRn_WR(x, n, v))
03537 /*@}*/
03538 
03539 /*******************************************************************************
03540  * hw_can_t - module struct
03541  ******************************************************************************/
03542 /*!
03543  * @brief All CAN module registers.
03544  */
03545 #pragma pack(1)
03546 typedef struct _hw_can
03547 {
03548     __IO hw_can_mcr_t MCR ;                 /*!< [0x0] Module Configuration Register */
03549     __IO hw_can_ctrl1_t CTRL1 ;             /*!< [0x4] Control 1 register */
03550     __IO hw_can_timer_t TIMER ;             /*!< [0x8] Free Running Timer */
03551     uint8_t _reserved0[4];
03552     __IO hw_can_rxmgmask_t RXMGMASK ;       /*!< [0x10] Rx Mailboxes Global Mask Register */
03553     __IO hw_can_rx14mask_t RX14MASK ;       /*!< [0x14] Rx 14 Mask register */
03554     __IO hw_can_rx15mask_t RX15MASK ;       /*!< [0x18] Rx 15 Mask register */
03555     __IO hw_can_ecr_t ECR ;                 /*!< [0x1C] Error Counter */
03556     __IO hw_can_esr1_t ESR1 ;               /*!< [0x20] Error and Status 1 register */
03557     uint8_t _reserved1[4];
03558     __IO hw_can_imask1_t IMASK1 ;           /*!< [0x28] Interrupt Masks 1 register */
03559     uint8_t _reserved2[4];
03560     __IO hw_can_iflag1_t IFLAG1 ;           /*!< [0x30] Interrupt Flags 1 register */
03561     __IO hw_can_ctrl2_t CTRL2 ;             /*!< [0x34] Control 2 register */
03562     __I hw_can_esr2_t ESR2 ;                /*!< [0x38] Error and Status 2 register */
03563     uint8_t _reserved3[8];
03564     __I hw_can_crcr_t CRCR ;                /*!< [0x44] CRC Register */
03565     __IO hw_can_rxfgmask_t RXFGMASK ;       /*!< [0x48] Rx FIFO Global Mask register */
03566     __I hw_can_rxfir_t RXFIR ;              /*!< [0x4C] Rx FIFO Information Register */
03567     uint8_t _reserved4[48];
03568     struct {
03569         __IO hw_can_csn_t CSn ;             /*!< [0x80] Message Buffer 0 CS Register */
03570         __IO hw_can_idn_t IDn ;             /*!< [0x84] Message Buffer 0 ID Register */
03571         __IO hw_can_word0n_t WORD0n ;       /*!< [0x88] Message Buffer 0 WORD0 Register */
03572         __IO hw_can_word1n_t WORD1n ;       /*!< [0x8C] Message Buffer 0 WORD1 Register */
03573     } MB[16];
03574     uint8_t _reserved5[1792];
03575     __IO hw_can_rximrn_t RXIMRn [16];       /*!< [0x880] Rx Individual Mask Registers */
03576 } hw_can_t;
03577 #pragma pack()
03578 
03579 /*! @brief Macro to access all CAN registers. */
03580 /*! @param x CAN module instance base address. */
03581 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
03582  *     use the '&' operator, like <code>&HW_CAN(CAN0_BASE)</code>. */
03583 #define HW_CAN(x)      (*(hw_can_t *)(x))
03584 
03585 #endif /* __HW_CAN_REGISTERS_H__ */
03586 /* EOF */