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Morpheus
_hw_can_esr1 Union Reference
HW_CAN_ESR1 - Error and Status 1 register (RW) More...
#include <MK64F12_can.h>
Detailed Description
HW_CAN_ESR1 - Error and Status 1 register (RW)
Reset value: 0x00000000U
This register reflects various error conditions, some general status of the device and it is the source of interrupts to the CPU. The CPU read action clears bits 15-10. Therefore the reported error conditions (bits 15-10) are those that occurred since the last time the CPU read this register. Bits 9-3 are status bits. The following table shows the FlexCAN state variables and their meanings. Other combinations not shown in the table are reserved. SYNCH IDLE TX RX FlexCAN State 0 0 0 0 Not synchronized to CAN bus 1 1 x x Idle 1 0 1 0 Transmitting 1 0 0 1 Receiving
Definition at line 1651 of file MK64F12_can.h.
Generated on Sat Aug 27 2022 17:09:01 by
1.7.2