MK64F12_adc.h

00001 /*
00002 ** ###################################################################
00003 **     Compilers:           Keil ARM C/C++ Compiler
00004 **                          Freescale C/C++ for Embedded ARM
00005 **                          GNU C Compiler
00006 **                          IAR ANSI C/C++ Compiler for ARM
00007 **
00008 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
00009 **     Version:             rev. 2.5, 2014-02-10
00010 **     Build:               b140604
00011 **
00012 **     Abstract:
00013 **         Extension to the CMSIS register access layer header.
00014 **
00015 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
00016 **     All rights reserved.
00017 **
00018 **     (C) COPYRIGHT 2015-2015 ARM Limited
00019 **     ALL RIGHTS RESERVED
00020 **
00021 **     Redistribution and use in source and binary forms, with or without modification,
00022 **     are permitted provided that the following conditions are met:
00023 **
00024 **     o Redistributions of source code must retain the above copyright notice, this list
00025 **       of conditions and the following disclaimer.
00026 **
00027 **     o Redistributions in binary form must reproduce the above copyright notice, this
00028 **       list of conditions and the following disclaimer in the documentation and/or
00029 **       other materials provided with the distribution.
00030 **
00031 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00032 **       contributors may be used to endorse or promote products derived from this
00033 **       software without specific prior written permission.
00034 **
00035 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00036 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00037 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00038 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00039 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00040 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00041 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00042 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00043 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00044 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00045 **
00046 **     http:                 www.freescale.com
00047 **     mail:                 support@freescale.com
00048 **
00049 **     Revisions:
00050 **     - rev. 1.0 (2013-08-12)
00051 **         Initial version.
00052 **     - rev. 2.0 (2013-10-29)
00053 **         Register accessor macros added to the memory map.
00054 **         Symbols for Processor Expert memory map compatibility added to the memory map.
00055 **         Startup file for gcc has been updated according to CMSIS 3.2.
00056 **         System initialization updated.
00057 **         MCG - registers updated.
00058 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
00059 **     - rev. 2.1 (2013-10-30)
00060 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
00061 **     - rev. 2.2 (2013-12-09)
00062 **         DMA - EARS register removed.
00063 **         AIPS0, AIPS1 - MPRA register updated.
00064 **     - rev. 2.3 (2014-01-24)
00065 **         Update according to reference manual rev. 2
00066 **         ENET, MCG, MCM, SIM, USB - registers updated
00067 **     - rev. 2.4 (2014-02-10)
00068 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00069 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00070 **     - rev. 2.5 (2014-02-10)
00071 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00072 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00073 **         Module access macro module_BASES replaced by module_BASE_PTRS.
00074 **     - rev. 2.6 (2015-08-03) (ARM)
00075 **         All accesses to memory are replaced by equivalent macros; this allows
00076 **         memory read/write operations to be re-defined if needed (for example,
00077 **         to implement new security features
00078 **
00079 ** ###################################################################
00080 */
00081 
00082 /*
00083  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
00084  *
00085  * This file was generated automatically and any changes may be lost.
00086  */
00087 #ifndef __HW_ADC_REGISTERS_H__
00088 #define __HW_ADC_REGISTERS_H__
00089 
00090 #include "MK64F12.h"
00091 #include "fsl_bitaccess.h"
00092 
00093 /*
00094  * MK64F12 ADC
00095  *
00096  * Analog-to-Digital Converter
00097  *
00098  * Registers defined in this header file:
00099  * - HW_ADC_SC1n - ADC Status and Control Registers 1
00100  * - HW_ADC_CFG1 - ADC Configuration Register 1
00101  * - HW_ADC_CFG2 - ADC Configuration Register 2
00102  * - HW_ADC_Rn - ADC Data Result Register
00103  * - HW_ADC_CV1 - Compare Value Registers
00104  * - HW_ADC_CV2 - Compare Value Registers
00105  * - HW_ADC_SC2 - Status and Control Register 2
00106  * - HW_ADC_SC3 - Status and Control Register 3
00107  * - HW_ADC_OFS - ADC Offset Correction Register
00108  * - HW_ADC_PG - ADC Plus-Side Gain Register
00109  * - HW_ADC_MG - ADC Minus-Side Gain Register
00110  * - HW_ADC_CLPD - ADC Plus-Side General Calibration Value Register
00111  * - HW_ADC_CLPS - ADC Plus-Side General Calibration Value Register
00112  * - HW_ADC_CLP4 - ADC Plus-Side General Calibration Value Register
00113  * - HW_ADC_CLP3 - ADC Plus-Side General Calibration Value Register
00114  * - HW_ADC_CLP2 - ADC Plus-Side General Calibration Value Register
00115  * - HW_ADC_CLP1 - ADC Plus-Side General Calibration Value Register
00116  * - HW_ADC_CLP0 - ADC Plus-Side General Calibration Value Register
00117  * - HW_ADC_CLMD - ADC Minus-Side General Calibration Value Register
00118  * - HW_ADC_CLMS - ADC Minus-Side General Calibration Value Register
00119  * - HW_ADC_CLM4 - ADC Minus-Side General Calibration Value Register
00120  * - HW_ADC_CLM3 - ADC Minus-Side General Calibration Value Register
00121  * - HW_ADC_CLM2 - ADC Minus-Side General Calibration Value Register
00122  * - HW_ADC_CLM1 - ADC Minus-Side General Calibration Value Register
00123  * - HW_ADC_CLM0 - ADC Minus-Side General Calibration Value Register
00124  *
00125  * - hw_adc_t - Struct containing all module registers.
00126  */
00127 
00128 #define HW_ADC_INSTANCE_COUNT (2U) /*!< Number of instances of the ADC module. */
00129 #define HW_ADC0 (0U) /*!< Instance number for ADC0. */
00130 #define HW_ADC1 (1U) /*!< Instance number for ADC1. */
00131 
00132 /*******************************************************************************
00133  * HW_ADC_SC1n - ADC Status and Control Registers 1
00134  ******************************************************************************/
00135 
00136 /*!
00137  * @brief HW_ADC_SC1n - ADC Status and Control Registers 1 (RW)
00138  *
00139  * Reset value: 0x0000001FU
00140  *
00141  * SC1A is used for both software and hardware trigger modes of operation. To
00142  * allow sequential conversions of the ADC to be triggered by internal peripherals,
00143  * the ADC can have more than one status and control register: one for each
00144  * conversion. The SC1B-SC1n registers indicate potentially multiple SC1 registers
00145  * for use only in hardware trigger mode. See the chip configuration information
00146  * about the number of SC1n registers specific to this device. The SC1n registers
00147  * have identical fields, and are used in a "ping-pong" approach to control ADC
00148  * operation. At any one point in time, only one of the SC1n registers is actively
00149  * controlling ADC conversions. Updating SC1A while SC1n is actively controlling
00150  * a conversion is allowed, and vice-versa for any of the SC1n registers specific
00151  * to this MCU. Writing SC1A while SC1A is actively controlling a conversion
00152  * aborts the current conversion. In Software Trigger mode, when SC2[ADTRG]=0,
00153  * writes to SC1A subsequently initiate a new conversion, if SC1[ADCH] contains a
00154  * value other than all 1s. Writing any of the SC1n registers while that specific
00155  * SC1n register is actively controlling a conversion aborts the current conversion.
00156  * None of the SC1B-SC1n registers are used for software trigger operation and
00157  * therefore writes to the SC1B-SC1n registers do not initiate a new conversion.
00158  */
00159 typedef union _hw_adc_sc1n
00160 {
00161     uint32_t U;
00162     struct _hw_adc_sc1n_bitfields
00163     {
00164         uint32_t ADCH : 5;             /*!< [4:0] Input channel select */
00165         uint32_t DIFF : 1;             /*!< [5] Differential Mode Enable */
00166         uint32_t AIEN : 1;             /*!< [6] Interrupt Enable */
00167         uint32_t COCO : 1;             /*!< [7] Conversion Complete Flag */
00168         uint32_t RESERVED0 : 24;       /*!< [31:8]  */
00169     } B;
00170 } hw_adc_sc1n_t;
00171 
00172 /*!
00173  * @name Constants and macros for entire ADC_SC1n register
00174  */
00175 /*@{*/
00176 #define HW_ADC_SC1n_COUNT (2U)
00177 
00178 #define HW_ADC_SC1n_ADDR(x, n)   ((x) + 0x0U + (0x4U * (n)))
00179 
00180 #define HW_ADC_SC1n(x, n)        (*(__IO hw_adc_sc1n_t *) HW_ADC_SC1n_ADDR(x, n))
00181 #define HW_ADC_SC1n_RD(x, n)     (ADDRESS_READ(hw_adc_sc1n_t, HW_ADC_SC1n_ADDR(x, n)))
00182 #define HW_ADC_SC1n_WR(x, n, v)  (ADDRESS_WRITE(hw_adc_sc1n_t, HW_ADC_SC1n_ADDR(x, n), v))
00183 #define HW_ADC_SC1n_SET(x, n, v) (HW_ADC_SC1n_WR(x, n, HW_ADC_SC1n_RD(x, n) |  (v)))
00184 #define HW_ADC_SC1n_CLR(x, n, v) (HW_ADC_SC1n_WR(x, n, HW_ADC_SC1n_RD(x, n) & ~(v)))
00185 #define HW_ADC_SC1n_TOG(x, n, v) (HW_ADC_SC1n_WR(x, n, HW_ADC_SC1n_RD(x, n) ^  (v)))
00186 /*@}*/
00187 
00188 /*
00189  * Constants & macros for individual ADC_SC1n bitfields
00190  */
00191 
00192 /*!
00193  * @name Register ADC_SC1n, field ADCH[4:0] (RW)
00194  *
00195  * Selects one of the input channels. The input channel decode depends on the
00196  * value of DIFF. DAD0-DAD3 are associated with the input pin pairs DADPx and
00197  * DADMx. Some of the input channel options in the bitfield-setting descriptions might
00198  * not be available for your device. For the actual ADC channel assignments for
00199  * your device, see the Chip Configuration details. The successive approximation
00200  * converter subsystem is turned off when the channel select bits are all set,
00201  * that is, ADCH = 11111. This feature allows explicit disabling of the ADC and
00202  * isolation of the input channel from all sources. Terminating continuous
00203  * conversions this way prevents an additional single conversion from being performed. It
00204  * is not necessary to set ADCH to all 1s to place the ADC in a low-power state
00205  * when continuous conversions are not enabled because the module automatically
00206  * enters a low-power state when a conversion completes.
00207  *
00208  * Values:
00209  * - 00000 - When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is
00210  *     selected as input.
00211  * - 00001 - When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is
00212  *     selected as input.
00213  * - 00010 - When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is
00214  *     selected as input.
00215  * - 00011 - When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is
00216  *     selected as input.
00217  * - 00100 - When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved.
00218  * - 00101 - When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved.
00219  * - 00110 - When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved.
00220  * - 00111 - When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved.
00221  * - 01000 - When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved.
00222  * - 01001 - When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved.
00223  * - 01010 - When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved.
00224  * - 01011 - When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved.
00225  * - 01100 - When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved.
00226  * - 01101 - When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved.
00227  * - 01110 - When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved.
00228  * - 01111 - When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved.
00229  * - 10000 - When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved.
00230  * - 10001 - When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved.
00231  * - 10010 - When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved.
00232  * - 10011 - When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved.
00233  * - 10100 - When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved.
00234  * - 10101 - When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved.
00235  * - 10110 - When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved.
00236  * - 10111 - When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved.
00237  * - 11000 - Reserved.
00238  * - 11001 - Reserved.
00239  * - 11010 - When DIFF=0, Temp Sensor (single-ended) is selected as input; when
00240  *     DIFF=1, Temp Sensor (differential) is selected as input.
00241  * - 11011 - When DIFF=0, Bandgap (single-ended) is selected as input; when
00242  *     DIFF=1, Bandgap (differential) is selected as input.
00243  * - 11100 - Reserved.
00244  * - 11101 - When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH
00245  *     (differential) is selected as input. Voltage reference selected is determined
00246  *     by SC2[REFSEL].
00247  * - 11110 - When DIFF=0,VREFSL is selected as input; when DIFF=1, it is
00248  *     reserved. Voltage reference selected is determined by SC2[REFSEL].
00249  * - 11111 - Module is disabled.
00250  */
00251 /*@{*/
00252 #define BP_ADC_SC1n_ADCH     (0U)          /*!< Bit position for ADC_SC1n_ADCH. */
00253 #define BM_ADC_SC1n_ADCH     (0x0000001FU) /*!< Bit mask for ADC_SC1n_ADCH. */
00254 #define BS_ADC_SC1n_ADCH     (5U)          /*!< Bit field size in bits for ADC_SC1n_ADCH. */
00255 
00256 /*! @brief Read current value of the ADC_SC1n_ADCH field. */
00257 #define BR_ADC_SC1n_ADCH(x, n) (UNION_READ(hw_adc_sc1n_t, HW_ADC_SC1n_ADDR(x, n), U, B.ADCH))
00258 
00259 /*! @brief Format value for bitfield ADC_SC1n_ADCH. */
00260 #define BF_ADC_SC1n_ADCH(v)  ((uint32_t)((uint32_t)(v) << BP_ADC_SC1n_ADCH) & BM_ADC_SC1n_ADCH)
00261 
00262 /*! @brief Set the ADCH field to a new value. */
00263 #define BW_ADC_SC1n_ADCH(x, n, v) (HW_ADC_SC1n_WR(x, n, (HW_ADC_SC1n_RD(x, n) & ~BM_ADC_SC1n_ADCH) | BF_ADC_SC1n_ADCH(v)))
00264 /*@}*/
00265 
00266 /*!
00267  * @name Register ADC_SC1n, field DIFF[5] (RW)
00268  *
00269  * Configures the ADC to operate in differential mode. When enabled, this mode
00270  * automatically selects from the differential channels, and changes the
00271  * conversion algorithm and the number of cycles to complete a conversion.
00272  *
00273  * Values:
00274  * - 0 - Single-ended conversions and input channels are selected.
00275  * - 1 - Differential conversions and input channels are selected.
00276  */
00277 /*@{*/
00278 #define BP_ADC_SC1n_DIFF     (5U)          /*!< Bit position for ADC_SC1n_DIFF. */
00279 #define BM_ADC_SC1n_DIFF     (0x00000020U) /*!< Bit mask for ADC_SC1n_DIFF. */
00280 #define BS_ADC_SC1n_DIFF     (1U)          /*!< Bit field size in bits for ADC_SC1n_DIFF. */
00281 
00282 /*! @brief Read current value of the ADC_SC1n_DIFF field. */
00283 #define BR_ADC_SC1n_DIFF(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ADC_SC1n_ADDR(x, n), BP_ADC_SC1n_DIFF)))
00284 
00285 /*! @brief Format value for bitfield ADC_SC1n_DIFF. */
00286 #define BF_ADC_SC1n_DIFF(v)  ((uint32_t)((uint32_t)(v) << BP_ADC_SC1n_DIFF) & BM_ADC_SC1n_DIFF)
00287 
00288 /*! @brief Set the DIFF field to a new value. */
00289 #define BW_ADC_SC1n_DIFF(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ADC_SC1n_ADDR(x, n), BP_ADC_SC1n_DIFF), v))
00290 /*@}*/
00291 
00292 /*!
00293  * @name Register ADC_SC1n, field AIEN[6] (RW)
00294  *
00295  * Enables conversion complete interrupts. When COCO becomes set while the
00296  * respective AIEN is high, an interrupt is asserted.
00297  *
00298  * Values:
00299  * - 0 - Conversion complete interrupt is disabled.
00300  * - 1 - Conversion complete interrupt is enabled.
00301  */
00302 /*@{*/
00303 #define BP_ADC_SC1n_AIEN     (6U)          /*!< Bit position for ADC_SC1n_AIEN. */
00304 #define BM_ADC_SC1n_AIEN     (0x00000040U) /*!< Bit mask for ADC_SC1n_AIEN. */
00305 #define BS_ADC_SC1n_AIEN     (1U)          /*!< Bit field size in bits for ADC_SC1n_AIEN. */
00306 
00307 /*! @brief Read current value of the ADC_SC1n_AIEN field. */
00308 #define BR_ADC_SC1n_AIEN(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ADC_SC1n_ADDR(x, n), BP_ADC_SC1n_AIEN)))
00309 
00310 /*! @brief Format value for bitfield ADC_SC1n_AIEN. */
00311 #define BF_ADC_SC1n_AIEN(v)  ((uint32_t)((uint32_t)(v) << BP_ADC_SC1n_AIEN) & BM_ADC_SC1n_AIEN)
00312 
00313 /*! @brief Set the AIEN field to a new value. */
00314 #define BW_ADC_SC1n_AIEN(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ADC_SC1n_ADDR(x, n), BP_ADC_SC1n_AIEN), v))
00315 /*@}*/
00316 
00317 /*!
00318  * @name Register ADC_SC1n, field COCO[7] (RO)
00319  *
00320  * This is a read-only field that is set each time a conversion is completed
00321  * when the compare function is disabled, or SC2[ACFE]=0 and the hardware average
00322  * function is disabled, or SC3[AVGE]=0. When the compare function is enabled, or
00323  * SC2[ACFE]=1, COCO is set upon completion of a conversion only if the compare
00324  * result is true. When the hardware average function is enabled, or SC3[AVGE]=1,
00325  * COCO is set upon completion of the selected number of conversions (determined
00326  * by AVGS). COCO in SC1A is also set at the completion of a calibration sequence.
00327  * COCO is cleared when the respective SC1n register is written or when the
00328  * respective Rn register is read.
00329  *
00330  * Values:
00331  * - 0 - Conversion is not completed.
00332  * - 1 - Conversion is completed.
00333  */
00334 /*@{*/
00335 #define BP_ADC_SC1n_COCO     (7U)          /*!< Bit position for ADC_SC1n_COCO. */
00336 #define BM_ADC_SC1n_COCO     (0x00000080U) /*!< Bit mask for ADC_SC1n_COCO. */
00337 #define BS_ADC_SC1n_COCO     (1U)          /*!< Bit field size in bits for ADC_SC1n_COCO. */
00338 
00339 /*! @brief Read current value of the ADC_SC1n_COCO field. */
00340 #define BR_ADC_SC1n_COCO(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ADC_SC1n_ADDR(x, n), BP_ADC_SC1n_COCO)))
00341 /*@}*/
00342 
00343 /*******************************************************************************
00344  * HW_ADC_CFG1 - ADC Configuration Register 1
00345  ******************************************************************************/
00346 
00347 /*!
00348  * @brief HW_ADC_CFG1 - ADC Configuration Register 1 (RW)
00349  *
00350  * Reset value: 0x00000000U
00351  *
00352  * The configuration Register 1 (CFG1) selects the mode of operation, clock
00353  * source, clock divide, and configuration for low power or long sample time.
00354  */
00355 typedef union _hw_adc_cfg1
00356 {
00357     uint32_t U;
00358     struct _hw_adc_cfg1_bitfields
00359     {
00360         uint32_t ADICLK : 2;           /*!< [1:0] Input Clock Select */
00361         uint32_t MODE : 2;             /*!< [3:2] Conversion mode selection */
00362         uint32_t ADLSMP : 1;           /*!< [4] Sample Time Configuration */
00363         uint32_t ADIV : 2;             /*!< [6:5] Clock Divide Select */
00364         uint32_t ADLPC : 1;            /*!< [7] Low-Power Configuration */
00365         uint32_t RESERVED0 : 24;       /*!< [31:8]  */
00366     } B;
00367 } hw_adc_cfg1_t;
00368 
00369 /*!
00370  * @name Constants and macros for entire ADC_CFG1 register
00371  */
00372 /*@{*/
00373 #define HW_ADC_CFG1_ADDR(x)      ((x) + 0x8U)
00374 
00375 #define HW_ADC_CFG1(x)           (*(__IO hw_adc_cfg1_t *) HW_ADC_CFG1_ADDR(x))
00376 #define HW_ADC_CFG1_RD(x)        (ADDRESS_READ(hw_adc_cfg1_t, HW_ADC_CFG1_ADDR(x)))
00377 #define HW_ADC_CFG1_WR(x, v)     (ADDRESS_WRITE(hw_adc_cfg1_t, HW_ADC_CFG1_ADDR(x), v))
00378 #define HW_ADC_CFG1_SET(x, v)    (HW_ADC_CFG1_WR(x, HW_ADC_CFG1_RD(x) |  (v)))
00379 #define HW_ADC_CFG1_CLR(x, v)    (HW_ADC_CFG1_WR(x, HW_ADC_CFG1_RD(x) & ~(v)))
00380 #define HW_ADC_CFG1_TOG(x, v)    (HW_ADC_CFG1_WR(x, HW_ADC_CFG1_RD(x) ^  (v)))
00381 /*@}*/
00382 
00383 /*
00384  * Constants & macros for individual ADC_CFG1 bitfields
00385  */
00386 
00387 /*!
00388  * @name Register ADC_CFG1, field ADICLK[1:0] (RW)
00389  *
00390  * Selects the input clock source to generate the internal clock, ADCK. Note
00391  * that when the ADACK clock source is selected, it is not required to be active
00392  * prior to conversion start. When it is selected and it is not active prior to a
00393  * conversion start, when CFG2[ADACKEN]=0, the asynchronous clock is activated at
00394  * the start of a conversion and deactivated when conversions are terminated. In
00395  * this case, there is an associated clock startup delay each time the clock
00396  * source is re-activated.
00397  *
00398  * Values:
00399  * - 00 - Bus clock
00400  * - 01 - Alternate clock 2 (ALTCLK2)
00401  * - 10 - Alternate clock (ALTCLK)
00402  * - 11 - Asynchronous clock (ADACK)
00403  */
00404 /*@{*/
00405 #define BP_ADC_CFG1_ADICLK   (0U)          /*!< Bit position for ADC_CFG1_ADICLK. */
00406 #define BM_ADC_CFG1_ADICLK   (0x00000003U) /*!< Bit mask for ADC_CFG1_ADICLK. */
00407 #define BS_ADC_CFG1_ADICLK   (2U)          /*!< Bit field size in bits for ADC_CFG1_ADICLK. */
00408 
00409 /*! @brief Read current value of the ADC_CFG1_ADICLK field. */
00410 #define BR_ADC_CFG1_ADICLK(x) (UNION_READ(hw_adc_cfg1_t, HW_ADC_CFG1_ADDR(x), U, B.ADICLK))
00411 
00412 /*! @brief Format value for bitfield ADC_CFG1_ADICLK. */
00413 #define BF_ADC_CFG1_ADICLK(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CFG1_ADICLK) & BM_ADC_CFG1_ADICLK)
00414 
00415 /*! @brief Set the ADICLK field to a new value. */
00416 #define BW_ADC_CFG1_ADICLK(x, v) (HW_ADC_CFG1_WR(x, (HW_ADC_CFG1_RD(x) & ~BM_ADC_CFG1_ADICLK) | BF_ADC_CFG1_ADICLK(v)))
00417 /*@}*/
00418 
00419 /*!
00420  * @name Register ADC_CFG1, field MODE[3:2] (RW)
00421  *
00422  * Selects the ADC resolution mode.
00423  *
00424  * Values:
00425  * - 00 - When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is
00426  *     differential 9-bit conversion with 2's complement output.
00427  * - 01 - When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it is
00428  *     differential 13-bit conversion with 2's complement output.
00429  * - 10 - When DIFF=0:It is single-ended 10-bit conversion. ; when DIFF=1, it is
00430  *     differential 11-bit conversion with 2's complement output
00431  * - 11 - When DIFF=0:It is single-ended 16-bit conversion..; when DIFF=1, it is
00432  *     differential 16-bit conversion with 2's complement output
00433  */
00434 /*@{*/
00435 #define BP_ADC_CFG1_MODE     (2U)          /*!< Bit position for ADC_CFG1_MODE. */
00436 #define BM_ADC_CFG1_MODE     (0x0000000CU) /*!< Bit mask for ADC_CFG1_MODE. */
00437 #define BS_ADC_CFG1_MODE     (2U)          /*!< Bit field size in bits for ADC_CFG1_MODE. */
00438 
00439 /*! @brief Read current value of the ADC_CFG1_MODE field. */
00440 #define BR_ADC_CFG1_MODE(x)  (UNION_READ(hw_adc_cfg1_t, HW_ADC_CFG1_ADDR(x), U, B.MODE))
00441 
00442 /*! @brief Format value for bitfield ADC_CFG1_MODE. */
00443 #define BF_ADC_CFG1_MODE(v)  ((uint32_t)((uint32_t)(v) << BP_ADC_CFG1_MODE) & BM_ADC_CFG1_MODE)
00444 
00445 /*! @brief Set the MODE field to a new value. */
00446 #define BW_ADC_CFG1_MODE(x, v) (HW_ADC_CFG1_WR(x, (HW_ADC_CFG1_RD(x) & ~BM_ADC_CFG1_MODE) | BF_ADC_CFG1_MODE(v)))
00447 /*@}*/
00448 
00449 /*!
00450  * @name Register ADC_CFG1, field ADLSMP[4] (RW)
00451  *
00452  * Selects between different sample times based on the conversion mode selected.
00453  * This field adjusts the sample period to allow higher impedance inputs to be
00454  * accurately sampled or to maximize conversion speed for lower impedance inputs.
00455  * Longer sample times can also be used to lower overall power consumption if
00456  * continuous conversions are enabled and high conversion rates are not required.
00457  * When ADLSMP=1, the long sample time select bits, (ADLSTS[1:0]), can select the
00458  * extent of the long sample time.
00459  *
00460  * Values:
00461  * - 0 - Short sample time.
00462  * - 1 - Long sample time.
00463  */
00464 /*@{*/
00465 #define BP_ADC_CFG1_ADLSMP   (4U)          /*!< Bit position for ADC_CFG1_ADLSMP. */
00466 #define BM_ADC_CFG1_ADLSMP   (0x00000010U) /*!< Bit mask for ADC_CFG1_ADLSMP. */
00467 #define BS_ADC_CFG1_ADLSMP   (1U)          /*!< Bit field size in bits for ADC_CFG1_ADLSMP. */
00468 
00469 /*! @brief Read current value of the ADC_CFG1_ADLSMP field. */
00470 #define BR_ADC_CFG1_ADLSMP(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ADC_CFG1_ADDR(x), BP_ADC_CFG1_ADLSMP)))
00471 
00472 /*! @brief Format value for bitfield ADC_CFG1_ADLSMP. */
00473 #define BF_ADC_CFG1_ADLSMP(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CFG1_ADLSMP) & BM_ADC_CFG1_ADLSMP)
00474 
00475 /*! @brief Set the ADLSMP field to a new value. */
00476 #define BW_ADC_CFG1_ADLSMP(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ADC_CFG1_ADDR(x), BP_ADC_CFG1_ADLSMP), v))
00477 /*@}*/
00478 
00479 /*!
00480  * @name Register ADC_CFG1, field ADIV[6:5] (RW)
00481  *
00482  * Selects the divide ratio used by the ADC to generate the internal clock ADCK.
00483  *
00484  * Values:
00485  * - 00 - The divide ratio is 1 and the clock rate is input clock.
00486  * - 01 - The divide ratio is 2 and the clock rate is (input clock)/2.
00487  * - 10 - The divide ratio is 4 and the clock rate is (input clock)/4.
00488  * - 11 - The divide ratio is 8 and the clock rate is (input clock)/8.
00489  */
00490 /*@{*/
00491 #define BP_ADC_CFG1_ADIV     (5U)          /*!< Bit position for ADC_CFG1_ADIV. */
00492 #define BM_ADC_CFG1_ADIV     (0x00000060U) /*!< Bit mask for ADC_CFG1_ADIV. */
00493 #define BS_ADC_CFG1_ADIV     (2U)          /*!< Bit field size in bits for ADC_CFG1_ADIV. */
00494 
00495 /*! @brief Read current value of the ADC_CFG1_ADIV field. */
00496 #define BR_ADC_CFG1_ADIV(x)  (UNION_READ(hw_adc_cfg1_t, HW_ADC_CFG1_ADDR(x), U, B.ADIV))
00497 
00498 /*! @brief Format value for bitfield ADC_CFG1_ADIV. */
00499 #define BF_ADC_CFG1_ADIV(v)  ((uint32_t)((uint32_t)(v) << BP_ADC_CFG1_ADIV) & BM_ADC_CFG1_ADIV)
00500 
00501 /*! @brief Set the ADIV field to a new value. */
00502 #define BW_ADC_CFG1_ADIV(x, v) (HW_ADC_CFG1_WR(x, (HW_ADC_CFG1_RD(x) & ~BM_ADC_CFG1_ADIV) | BF_ADC_CFG1_ADIV(v)))
00503 /*@}*/
00504 
00505 /*!
00506  * @name Register ADC_CFG1, field ADLPC[7] (RW)
00507  *
00508  * Controls the power configuration of the successive approximation converter.
00509  * This optimizes power consumption when higher sample rates are not required.
00510  *
00511  * Values:
00512  * - 0 - Normal power configuration.
00513  * - 1 - Low-power configuration. The power is reduced at the expense of maximum
00514  *     clock speed.
00515  */
00516 /*@{*/
00517 #define BP_ADC_CFG1_ADLPC    (7U)          /*!< Bit position for ADC_CFG1_ADLPC. */
00518 #define BM_ADC_CFG1_ADLPC    (0x00000080U) /*!< Bit mask for ADC_CFG1_ADLPC. */
00519 #define BS_ADC_CFG1_ADLPC    (1U)          /*!< Bit field size in bits for ADC_CFG1_ADLPC. */
00520 
00521 /*! @brief Read current value of the ADC_CFG1_ADLPC field. */
00522 #define BR_ADC_CFG1_ADLPC(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ADC_CFG1_ADDR(x), BP_ADC_CFG1_ADLPC)))
00523 
00524 /*! @brief Format value for bitfield ADC_CFG1_ADLPC. */
00525 #define BF_ADC_CFG1_ADLPC(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CFG1_ADLPC) & BM_ADC_CFG1_ADLPC)
00526 
00527 /*! @brief Set the ADLPC field to a new value. */
00528 #define BW_ADC_CFG1_ADLPC(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ADC_CFG1_ADDR(x), BP_ADC_CFG1_ADLPC), v))
00529 /*@}*/
00530 
00531 /*******************************************************************************
00532  * HW_ADC_CFG2 - ADC Configuration Register 2
00533  ******************************************************************************/
00534 
00535 /*!
00536  * @brief HW_ADC_CFG2 - ADC Configuration Register 2 (RW)
00537  *
00538  * Reset value: 0x00000000U
00539  *
00540  * Configuration Register 2 (CFG2) selects the special high-speed configuration
00541  * for very high speed conversions and selects the long sample time duration
00542  * during long sample mode.
00543  */
00544 typedef union _hw_adc_cfg2
00545 {
00546     uint32_t U;
00547     struct _hw_adc_cfg2_bitfields
00548     {
00549         uint32_t ADLSTS : 2;           /*!< [1:0] Long Sample Time Select */
00550         uint32_t ADHSC : 1;            /*!< [2] High-Speed Configuration */
00551         uint32_t ADACKEN : 1;          /*!< [3] Asynchronous Clock Output Enable */
00552         uint32_t MUXSEL : 1;           /*!< [4] ADC Mux Select */
00553         uint32_t RESERVED0 : 27;       /*!< [31:5]  */
00554     } B;
00555 } hw_adc_cfg2_t;
00556 
00557 /*!
00558  * @name Constants and macros for entire ADC_CFG2 register
00559  */
00560 /*@{*/
00561 #define HW_ADC_CFG2_ADDR(x)      ((x) + 0xCU)
00562 
00563 #define HW_ADC_CFG2(x)           (*(__IO hw_adc_cfg2_t *) HW_ADC_CFG2_ADDR(x))
00564 #define HW_ADC_CFG2_RD(x)        (ADDRESS_READ(hw_adc_cfg2_t, HW_ADC_CFG2_ADDR(x)))
00565 #define HW_ADC_CFG2_WR(x, v)     (ADDRESS_WRITE(hw_adc_cfg2_t, HW_ADC_CFG2_ADDR(x), v))
00566 #define HW_ADC_CFG2_SET(x, v)    (HW_ADC_CFG2_WR(x, HW_ADC_CFG2_RD(x) |  (v)))
00567 #define HW_ADC_CFG2_CLR(x, v)    (HW_ADC_CFG2_WR(x, HW_ADC_CFG2_RD(x) & ~(v)))
00568 #define HW_ADC_CFG2_TOG(x, v)    (HW_ADC_CFG2_WR(x, HW_ADC_CFG2_RD(x) ^  (v)))
00569 /*@}*/
00570 
00571 /*
00572  * Constants & macros for individual ADC_CFG2 bitfields
00573  */
00574 
00575 /*!
00576  * @name Register ADC_CFG2, field ADLSTS[1:0] (RW)
00577  *
00578  * Selects between the extended sample times when long sample time is selected,
00579  * that is, when CFG1[ADLSMP]=1. This allows higher impedance inputs to be
00580  * accurately sampled or to maximize conversion speed for lower impedance inputs.
00581  * Longer sample times can also be used to lower overall power consumption when
00582  * continuous conversions are enabled if high conversion rates are not required.
00583  *
00584  * Values:
00585  * - 00 - Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles
00586  *     total.
00587  * - 01 - 12 extra ADCK cycles; 16 ADCK cycles total sample time.
00588  * - 10 - 6 extra ADCK cycles; 10 ADCK cycles total sample time.
00589  * - 11 - 2 extra ADCK cycles; 6 ADCK cycles total sample time.
00590  */
00591 /*@{*/
00592 #define BP_ADC_CFG2_ADLSTS   (0U)          /*!< Bit position for ADC_CFG2_ADLSTS. */
00593 #define BM_ADC_CFG2_ADLSTS   (0x00000003U) /*!< Bit mask for ADC_CFG2_ADLSTS. */
00594 #define BS_ADC_CFG2_ADLSTS   (2U)          /*!< Bit field size in bits for ADC_CFG2_ADLSTS. */
00595 
00596 /*! @brief Read current value of the ADC_CFG2_ADLSTS field. */
00597 #define BR_ADC_CFG2_ADLSTS(x) (UNION_READ(hw_adc_cfg2_t, HW_ADC_CFG2_ADDR(x), U, B.ADLSTS))
00598 
00599 /*! @brief Format value for bitfield ADC_CFG2_ADLSTS. */
00600 #define BF_ADC_CFG2_ADLSTS(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CFG2_ADLSTS) & BM_ADC_CFG2_ADLSTS)
00601 
00602 /*! @brief Set the ADLSTS field to a new value. */
00603 #define BW_ADC_CFG2_ADLSTS(x, v) (HW_ADC_CFG2_WR(x, (HW_ADC_CFG2_RD(x) & ~BM_ADC_CFG2_ADLSTS) | BF_ADC_CFG2_ADLSTS(v)))
00604 /*@}*/
00605 
00606 /*!
00607  * @name Register ADC_CFG2, field ADHSC[2] (RW)
00608  *
00609  * Configures the ADC for very high-speed operation. The conversion sequence is
00610  * altered with 2 ADCK cycles added to the conversion time to allow higher speed
00611  * conversion clocks.
00612  *
00613  * Values:
00614  * - 0 - Normal conversion sequence selected.
00615  * - 1 - High-speed conversion sequence selected with 2 additional ADCK cycles
00616  *     to total conversion time.
00617  */
00618 /*@{*/
00619 #define BP_ADC_CFG2_ADHSC    (2U)          /*!< Bit position for ADC_CFG2_ADHSC. */
00620 #define BM_ADC_CFG2_ADHSC    (0x00000004U) /*!< Bit mask for ADC_CFG2_ADHSC. */
00621 #define BS_ADC_CFG2_ADHSC    (1U)          /*!< Bit field size in bits for ADC_CFG2_ADHSC. */
00622 
00623 /*! @brief Read current value of the ADC_CFG2_ADHSC field. */
00624 #define BR_ADC_CFG2_ADHSC(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_ADHSC)))
00625 
00626 /*! @brief Format value for bitfield ADC_CFG2_ADHSC. */
00627 #define BF_ADC_CFG2_ADHSC(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CFG2_ADHSC) & BM_ADC_CFG2_ADHSC)
00628 
00629 /*! @brief Set the ADHSC field to a new value. */
00630 #define BW_ADC_CFG2_ADHSC(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_ADHSC), v))
00631 /*@}*/
00632 
00633 /*!
00634  * @name Register ADC_CFG2, field ADACKEN[3] (RW)
00635  *
00636  * Enables the asynchronous clock source and the clock source output regardless
00637  * of the conversion and status of CFG1[ADICLK]. Based on MCU configuration, the
00638  * asynchronous clock may be used by other modules. See chip configuration
00639  * information. Setting this field allows the clock to be used even while the ADC is
00640  * idle or operating from a different clock source. Also, latency of initiating a
00641  * single or first-continuous conversion with the asynchronous clock selected is
00642  * reduced because the ADACK clock is already operational.
00643  *
00644  * Values:
00645  * - 0 - Asynchronous clock output disabled; Asynchronous clock is enabled only
00646  *     if selected by ADICLK and a conversion is active.
00647  * - 1 - Asynchronous clock and clock output is enabled regardless of the state
00648  *     of the ADC.
00649  */
00650 /*@{*/
00651 #define BP_ADC_CFG2_ADACKEN  (3U)          /*!< Bit position for ADC_CFG2_ADACKEN. */
00652 #define BM_ADC_CFG2_ADACKEN  (0x00000008U) /*!< Bit mask for ADC_CFG2_ADACKEN. */
00653 #define BS_ADC_CFG2_ADACKEN  (1U)          /*!< Bit field size in bits for ADC_CFG2_ADACKEN. */
00654 
00655 /*! @brief Read current value of the ADC_CFG2_ADACKEN field. */
00656 #define BR_ADC_CFG2_ADACKEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_ADACKEN)))
00657 
00658 /*! @brief Format value for bitfield ADC_CFG2_ADACKEN. */
00659 #define BF_ADC_CFG2_ADACKEN(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CFG2_ADACKEN) & BM_ADC_CFG2_ADACKEN)
00660 
00661 /*! @brief Set the ADACKEN field to a new value. */
00662 #define BW_ADC_CFG2_ADACKEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_ADACKEN), v))
00663 /*@}*/
00664 
00665 /*!
00666  * @name Register ADC_CFG2, field MUXSEL[4] (RW)
00667  *
00668  * Changes the ADC mux setting to select between alternate sets of ADC channels.
00669  *
00670  * Values:
00671  * - 0 - ADxxa channels are selected.
00672  * - 1 - ADxxb channels are selected.
00673  */
00674 /*@{*/
00675 #define BP_ADC_CFG2_MUXSEL   (4U)          /*!< Bit position for ADC_CFG2_MUXSEL. */
00676 #define BM_ADC_CFG2_MUXSEL   (0x00000010U) /*!< Bit mask for ADC_CFG2_MUXSEL. */
00677 #define BS_ADC_CFG2_MUXSEL   (1U)          /*!< Bit field size in bits for ADC_CFG2_MUXSEL. */
00678 
00679 /*! @brief Read current value of the ADC_CFG2_MUXSEL field. */
00680 #define BR_ADC_CFG2_MUXSEL(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_MUXSEL)))
00681 
00682 /*! @brief Format value for bitfield ADC_CFG2_MUXSEL. */
00683 #define BF_ADC_CFG2_MUXSEL(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CFG2_MUXSEL) & BM_ADC_CFG2_MUXSEL)
00684 
00685 /*! @brief Set the MUXSEL field to a new value. */
00686 #define BW_ADC_CFG2_MUXSEL(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_MUXSEL), v))
00687 /*@}*/
00688 
00689 /*******************************************************************************
00690  * HW_ADC_Rn - ADC Data Result Register
00691  ******************************************************************************/
00692 
00693 /*!
00694  * @brief HW_ADC_Rn - ADC Data Result Register (RO)
00695  *
00696  * Reset value: 0x00000000U
00697  *
00698  * The data result registers (Rn) contain the result of an ADC conversion of the
00699  * channel selected by the corresponding status and channel control register
00700  * (SC1A:SC1n). For every status and channel control register, there is a
00701  * corresponding data result register. Unused bits in R n are cleared in unsigned
00702  * right-aligned modes and carry the sign bit (MSB) in sign-extended 2's complement modes.
00703  * For example, when configured for 10-bit single-ended mode, D[15:10] are
00704  * cleared. When configured for 11-bit differential mode, D[15:10] carry the sign bit,
00705  * that is, bit 10 extended through bit 15. The following table describes the
00706  * behavior of the data result registers in the different modes of operation. Data
00707  * result register description Conversion mode D15 D14 D13 D12 D11 D10 D9 D8 D7
00708  * D6 D5 D4 D3 D2 D1 D0 Format 16-bit differential S D D D D D D D D D D D D D D D
00709  * Signed 2's complement 16-bit single-ended D D D D D D D D D D D D D D D D
00710  * Unsigned right justified 13-bit differential S S S S D D D D D D D D D D D D
00711  * Sign-extended 2's complement 12-bit single-ended 0 0 0 0 D D D D D D D D D D D D
00712  * Unsigned right-justified 11-bit differential S S S S S S D D D D D D D D D D
00713  * Sign-extended 2's complement 10-bit single-ended 0 0 0 0 0 0 D D D D D D D D D D
00714  * Unsigned right-justified 9-bit differential S S S S S S S S D D D D D D D D
00715  * Sign-extended 2's complement 8-bit single-ended 0 0 0 0 0 0 0 0 D D D D D D D D
00716  * Unsigned right-justified S: Sign bit or sign bit extension; D: Data, which is
00717  * 2's complement data if indicated
00718  */
00719 typedef union _hw_adc_rn
00720 {
00721     uint32_t U;
00722     struct _hw_adc_rn_bitfields
00723     {
00724         uint32_t D : 16;               /*!< [15:0] Data result */
00725         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
00726     } B;
00727 } hw_adc_rn_t;
00728 
00729 /*!
00730  * @name Constants and macros for entire ADC_Rn register
00731  */
00732 /*@{*/
00733 #define HW_ADC_Rn_COUNT (2U)
00734 
00735 #define HW_ADC_Rn_ADDR(x, n)     ((x) + 0x10U + (0x4U * (n)))
00736 
00737 #define HW_ADC_Rn(x, n)          (*(__I hw_adc_rn_t *) HW_ADC_Rn_ADDR(x, n))
00738 #define HW_ADC_Rn_RD(x, n)       (ADDRESS_READ(hw_adc_rn_t, HW_ADC_Rn_ADDR(x, n)))
00739 /*@}*/
00740 
00741 /*
00742  * Constants & macros for individual ADC_Rn bitfields
00743  */
00744 
00745 /*!
00746  * @name Register ADC_Rn, field D[15:0] (RO)
00747  */
00748 /*@{*/
00749 #define BP_ADC_Rn_D          (0U)          /*!< Bit position for ADC_Rn_D. */
00750 #define BM_ADC_Rn_D          (0x0000FFFFU) /*!< Bit mask for ADC_Rn_D. */
00751 #define BS_ADC_Rn_D          (16U)         /*!< Bit field size in bits for ADC_Rn_D. */
00752 
00753 /*! @brief Read current value of the ADC_Rn_D field. */
00754 #define BR_ADC_Rn_D(x, n)    (UNION_READ(hw_adc_rn_t, HW_ADC_Rn_ADDR(x, n), U, B.D))
00755 /*@}*/
00756 
00757 /*******************************************************************************
00758  * HW_ADC_CV1 - Compare Value Registers
00759  ******************************************************************************/
00760 
00761 /*!
00762  * @brief HW_ADC_CV1 - Compare Value Registers (RW)
00763  *
00764  * Reset value: 0x00000000U
00765  *
00766  * The Compare Value Registers (CV1 and CV2) contain a compare value used to
00767  * compare the conversion result when the compare function is enabled, that is,
00768  * SC2[ACFE]=1. This register is formatted in the same way as the Rn registers in
00769  * different modes of operation for both bit position definition and value format
00770  * using unsigned or sign-extended 2's complement. Therefore, the compare function
00771  * uses only the CVn fields that are related to the ADC mode of operation. The
00772  * compare value 2 register (CV2) is used only when the compare range function is
00773  * enabled, that is, SC2[ACREN]=1.
00774  */
00775 typedef union _hw_adc_cv1
00776 {
00777     uint32_t U;
00778     struct _hw_adc_cv1_bitfields
00779     {
00780         uint32_t CV : 16;              /*!< [15:0] Compare Value. */
00781         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
00782     } B;
00783 } hw_adc_cv1_t;
00784 
00785 /*!
00786  * @name Constants and macros for entire ADC_CV1 register
00787  */
00788 /*@{*/
00789 #define HW_ADC_CV1_ADDR(x)       ((x) + 0x18U)
00790 
00791 #define HW_ADC_CV1(x)            (*(__IO hw_adc_cv1_t *) HW_ADC_CV1_ADDR(x))
00792 #define HW_ADC_CV1_RD(x)         (ADDRESS_READ(hw_adc_cv1_t, HW_ADC_CV1_ADDR(x)))
00793 #define HW_ADC_CV1_WR(x, v)      (ADDRESS_WRITE(hw_adc_cv1_t, HW_ADC_CV1_ADDR(x), v))
00794 #define HW_ADC_CV1_SET(x, v)     (HW_ADC_CV1_WR(x, HW_ADC_CV1_RD(x) |  (v)))
00795 #define HW_ADC_CV1_CLR(x, v)     (HW_ADC_CV1_WR(x, HW_ADC_CV1_RD(x) & ~(v)))
00796 #define HW_ADC_CV1_TOG(x, v)     (HW_ADC_CV1_WR(x, HW_ADC_CV1_RD(x) ^  (v)))
00797 /*@}*/
00798 
00799 /*
00800  * Constants & macros for individual ADC_CV1 bitfields
00801  */
00802 
00803 /*!
00804  * @name Register ADC_CV1, field CV[15:0] (RW)
00805  */
00806 /*@{*/
00807 #define BP_ADC_CV1_CV        (0U)          /*!< Bit position for ADC_CV1_CV. */
00808 #define BM_ADC_CV1_CV        (0x0000FFFFU) /*!< Bit mask for ADC_CV1_CV. */
00809 #define BS_ADC_CV1_CV        (16U)         /*!< Bit field size in bits for ADC_CV1_CV. */
00810 
00811 /*! @brief Read current value of the ADC_CV1_CV field. */
00812 #define BR_ADC_CV1_CV(x)     (UNION_READ(hw_adc_cv1_t, HW_ADC_CV1_ADDR(x), U, B.CV))
00813 
00814 /*! @brief Format value for bitfield ADC_CV1_CV. */
00815 #define BF_ADC_CV1_CV(v)     ((uint32_t)((uint32_t)(v) << BP_ADC_CV1_CV) & BM_ADC_CV1_CV)
00816 
00817 /*! @brief Set the CV field to a new value. */
00818 #define BW_ADC_CV1_CV(x, v)  (HW_ADC_CV1_WR(x, (HW_ADC_CV1_RD(x) & ~BM_ADC_CV1_CV) | BF_ADC_CV1_CV(v)))
00819 /*@}*/
00820 
00821 /*******************************************************************************
00822  * HW_ADC_CV2 - Compare Value Registers
00823  ******************************************************************************/
00824 
00825 /*!
00826  * @brief HW_ADC_CV2 - Compare Value Registers (RW)
00827  *
00828  * Reset value: 0x00000000U
00829  *
00830  * The Compare Value Registers (CV1 and CV2) contain a compare value used to
00831  * compare the conversion result when the compare function is enabled, that is,
00832  * SC2[ACFE]=1. This register is formatted in the same way as the Rn registers in
00833  * different modes of operation for both bit position definition and value format
00834  * using unsigned or sign-extended 2's complement. Therefore, the compare function
00835  * uses only the CVn fields that are related to the ADC mode of operation. The
00836  * compare value 2 register (CV2) is used only when the compare range function is
00837  * enabled, that is, SC2[ACREN]=1.
00838  */
00839 typedef union _hw_adc_cv2
00840 {
00841     uint32_t U;
00842     struct _hw_adc_cv2_bitfields
00843     {
00844         uint32_t CV : 16;              /*!< [15:0] Compare Value. */
00845         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
00846     } B;
00847 } hw_adc_cv2_t;
00848 
00849 /*!
00850  * @name Constants and macros for entire ADC_CV2 register
00851  */
00852 /*@{*/
00853 #define HW_ADC_CV2_ADDR(x)       ((x) + 0x1CU)
00854 
00855 #define HW_ADC_CV2(x)            (*(__IO hw_adc_cv2_t *) HW_ADC_CV2_ADDR(x))
00856 #define HW_ADC_CV2_RD(x)         (ADDRESS_READ(hw_adc_cv2_t, HW_ADC_CV2_ADDR(x)))
00857 #define HW_ADC_CV2_WR(x, v)      (ADDRESS_WRITE(hw_adc_cv2_t, HW_ADC_CV2_ADDR(x), v))
00858 #define HW_ADC_CV2_SET(x, v)     (HW_ADC_CV2_WR(x, HW_ADC_CV2_RD(x) |  (v)))
00859 #define HW_ADC_CV2_CLR(x, v)     (HW_ADC_CV2_WR(x, HW_ADC_CV2_RD(x) & ~(v)))
00860 #define HW_ADC_CV2_TOG(x, v)     (HW_ADC_CV2_WR(x, HW_ADC_CV2_RD(x) ^  (v)))
00861 /*@}*/
00862 
00863 /*
00864  * Constants & macros for individual ADC_CV2 bitfields
00865  */
00866 
00867 /*!
00868  * @name Register ADC_CV2, field CV[15:0] (RW)
00869  */
00870 /*@{*/
00871 #define BP_ADC_CV2_CV        (0U)          /*!< Bit position for ADC_CV2_CV. */
00872 #define BM_ADC_CV2_CV        (0x0000FFFFU) /*!< Bit mask for ADC_CV2_CV. */
00873 #define BS_ADC_CV2_CV        (16U)         /*!< Bit field size in bits for ADC_CV2_CV. */
00874 
00875 /*! @brief Read current value of the ADC_CV2_CV field. */
00876 #define BR_ADC_CV2_CV(x)     (UNION_READ(hw_adc_cv2_t, HW_ADC_CV2_ADDR(x), U, B.CV))
00877 
00878 /*! @brief Format value for bitfield ADC_CV2_CV. */
00879 #define BF_ADC_CV2_CV(v)     ((uint32_t)((uint32_t)(v) << BP_ADC_CV2_CV) & BM_ADC_CV2_CV)
00880 
00881 /*! @brief Set the CV field to a new value. */
00882 #define BW_ADC_CV2_CV(x, v)  (HW_ADC_CV2_WR(x, (HW_ADC_CV2_RD(x) & ~BM_ADC_CV2_CV) | BF_ADC_CV2_CV(v)))
00883 /*@}*/
00884 
00885 /*******************************************************************************
00886  * HW_ADC_SC2 - Status and Control Register 2
00887  ******************************************************************************/
00888 
00889 /*!
00890  * @brief HW_ADC_SC2 - Status and Control Register 2 (RW)
00891  *
00892  * Reset value: 0x00000000U
00893  *
00894  * The status and control register 2 (SC2) contains the conversion active,
00895  * hardware/software trigger select, compare function, and voltage reference select of
00896  * the ADC module.
00897  */
00898 typedef union _hw_adc_sc2
00899 {
00900     uint32_t U;
00901     struct _hw_adc_sc2_bitfields
00902     {
00903         uint32_t REFSEL : 2;           /*!< [1:0] Voltage Reference Selection */
00904         uint32_t DMAEN : 1;            /*!< [2] DMA Enable */
00905         uint32_t ACREN : 1;            /*!< [3] Compare Function Range Enable */
00906         uint32_t ACFGT : 1;            /*!< [4] Compare Function Greater Than Enable */
00907         uint32_t ACFE : 1;             /*!< [5] Compare Function Enable */
00908         uint32_t ADTRG : 1;            /*!< [6] Conversion Trigger Select */
00909         uint32_t ADACT : 1;            /*!< [7] Conversion Active */
00910         uint32_t RESERVED0 : 24;       /*!< [31:8]  */
00911     } B;
00912 } hw_adc_sc2_t;
00913 
00914 /*!
00915  * @name Constants and macros for entire ADC_SC2 register
00916  */
00917 /*@{*/
00918 #define HW_ADC_SC2_ADDR(x)       ((x) + 0x20U)
00919 
00920 #define HW_ADC_SC2(x)            (*(__IO hw_adc_sc2_t *) HW_ADC_SC2_ADDR(x))
00921 #define HW_ADC_SC2_RD(x)         (ADDRESS_READ(hw_adc_sc2_t, HW_ADC_SC2_ADDR(x)))
00922 #define HW_ADC_SC2_WR(x, v)      (ADDRESS_WRITE(hw_adc_sc2_t, HW_ADC_SC2_ADDR(x), v))
00923 #define HW_ADC_SC2_SET(x, v)     (HW_ADC_SC2_WR(x, HW_ADC_SC2_RD(x) |  (v)))
00924 #define HW_ADC_SC2_CLR(x, v)     (HW_ADC_SC2_WR(x, HW_ADC_SC2_RD(x) & ~(v)))
00925 #define HW_ADC_SC2_TOG(x, v)     (HW_ADC_SC2_WR(x, HW_ADC_SC2_RD(x) ^  (v)))
00926 /*@}*/
00927 
00928 /*
00929  * Constants & macros for individual ADC_SC2 bitfields
00930  */
00931 
00932 /*!
00933  * @name Register ADC_SC2, field REFSEL[1:0] (RW)
00934  *
00935  * Selects the voltage reference source used for conversions.
00936  *
00937  * Values:
00938  * - 00 - Default voltage reference pin pair, that is, external pins VREFH and
00939  *     VREFL
00940  * - 01 - Alternate reference pair, that is, VALTH and VALTL . This pair may be
00941  *     additional external pins or internal sources depending on the MCU
00942  *     configuration. See the chip configuration information for details specific to this
00943  *     MCU
00944  * - 10 - Reserved
00945  * - 11 - Reserved
00946  */
00947 /*@{*/
00948 #define BP_ADC_SC2_REFSEL    (0U)          /*!< Bit position for ADC_SC2_REFSEL. */
00949 #define BM_ADC_SC2_REFSEL    (0x00000003U) /*!< Bit mask for ADC_SC2_REFSEL. */
00950 #define BS_ADC_SC2_REFSEL    (2U)          /*!< Bit field size in bits for ADC_SC2_REFSEL. */
00951 
00952 /*! @brief Read current value of the ADC_SC2_REFSEL field. */
00953 #define BR_ADC_SC2_REFSEL(x) (UNION_READ(hw_adc_sc2_t, HW_ADC_SC2_ADDR(x), U, B.REFSEL))
00954 
00955 /*! @brief Format value for bitfield ADC_SC2_REFSEL. */
00956 #define BF_ADC_SC2_REFSEL(v) ((uint32_t)((uint32_t)(v) << BP_ADC_SC2_REFSEL) & BM_ADC_SC2_REFSEL)
00957 
00958 /*! @brief Set the REFSEL field to a new value. */
00959 #define BW_ADC_SC2_REFSEL(x, v) (HW_ADC_SC2_WR(x, (HW_ADC_SC2_RD(x) & ~BM_ADC_SC2_REFSEL) | BF_ADC_SC2_REFSEL(v)))
00960 /*@}*/
00961 
00962 /*!
00963  * @name Register ADC_SC2, field DMAEN[2] (RW)
00964  *
00965  * Values:
00966  * - 0 - DMA is disabled.
00967  * - 1 - DMA is enabled and will assert the ADC DMA request during an ADC
00968  *     conversion complete event noted when any of the SC1n[COCO] flags is asserted.
00969  */
00970 /*@{*/
00971 #define BP_ADC_SC2_DMAEN     (2U)          /*!< Bit position for ADC_SC2_DMAEN. */
00972 #define BM_ADC_SC2_DMAEN     (0x00000004U) /*!< Bit mask for ADC_SC2_DMAEN. */
00973 #define BS_ADC_SC2_DMAEN     (1U)          /*!< Bit field size in bits for ADC_SC2_DMAEN. */
00974 
00975 /*! @brief Read current value of the ADC_SC2_DMAEN field. */
00976 #define BR_ADC_SC2_DMAEN(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_DMAEN)))
00977 
00978 /*! @brief Format value for bitfield ADC_SC2_DMAEN. */
00979 #define BF_ADC_SC2_DMAEN(v)  ((uint32_t)((uint32_t)(v) << BP_ADC_SC2_DMAEN) & BM_ADC_SC2_DMAEN)
00980 
00981 /*! @brief Set the DMAEN field to a new value. */
00982 #define BW_ADC_SC2_DMAEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_DMAEN), v))
00983 /*@}*/
00984 
00985 /*!
00986  * @name Register ADC_SC2, field ACREN[3] (RW)
00987  *
00988  * Configures the compare function to check if the conversion result of the
00989  * input being monitored is either between or outside the range formed by CV1 and CV2
00990  * determined by the value of ACFGT. ACFE must be set for ACFGT to have any
00991  * effect.
00992  *
00993  * Values:
00994  * - 0 - Range function disabled. Only CV1 is compared.
00995  * - 1 - Range function enabled. Both CV1 and CV2 are compared.
00996  */
00997 /*@{*/
00998 #define BP_ADC_SC2_ACREN     (3U)          /*!< Bit position for ADC_SC2_ACREN. */
00999 #define BM_ADC_SC2_ACREN     (0x00000008U) /*!< Bit mask for ADC_SC2_ACREN. */
01000 #define BS_ADC_SC2_ACREN     (1U)          /*!< Bit field size in bits for ADC_SC2_ACREN. */
01001 
01002 /*! @brief Read current value of the ADC_SC2_ACREN field. */
01003 #define BR_ADC_SC2_ACREN(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACREN)))
01004 
01005 /*! @brief Format value for bitfield ADC_SC2_ACREN. */
01006 #define BF_ADC_SC2_ACREN(v)  ((uint32_t)((uint32_t)(v) << BP_ADC_SC2_ACREN) & BM_ADC_SC2_ACREN)
01007 
01008 /*! @brief Set the ACREN field to a new value. */
01009 #define BW_ADC_SC2_ACREN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACREN), v))
01010 /*@}*/
01011 
01012 /*!
01013  * @name Register ADC_SC2, field ACFGT[4] (RW)
01014  *
01015  * Configures the compare function to check the conversion result relative to
01016  * the CV1 and CV2 based upon the value of ACREN. ACFE must be set for ACFGT to
01017  * have any effect.
01018  *
01019  * Values:
01020  * - 0 - Configures less than threshold, outside range not inclusive and inside
01021  *     range not inclusive; functionality based on the values placed in CV1 and
01022  *     CV2.
01023  * - 1 - Configures greater than or equal to threshold, outside and inside
01024  *     ranges inclusive; functionality based on the values placed in CV1 and CV2.
01025  */
01026 /*@{*/
01027 #define BP_ADC_SC2_ACFGT     (4U)          /*!< Bit position for ADC_SC2_ACFGT. */
01028 #define BM_ADC_SC2_ACFGT     (0x00000010U) /*!< Bit mask for ADC_SC2_ACFGT. */
01029 #define BS_ADC_SC2_ACFGT     (1U)          /*!< Bit field size in bits for ADC_SC2_ACFGT. */
01030 
01031 /*! @brief Read current value of the ADC_SC2_ACFGT field. */
01032 #define BR_ADC_SC2_ACFGT(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACFGT)))
01033 
01034 /*! @brief Format value for bitfield ADC_SC2_ACFGT. */
01035 #define BF_ADC_SC2_ACFGT(v)  ((uint32_t)((uint32_t)(v) << BP_ADC_SC2_ACFGT) & BM_ADC_SC2_ACFGT)
01036 
01037 /*! @brief Set the ACFGT field to a new value. */
01038 #define BW_ADC_SC2_ACFGT(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACFGT), v))
01039 /*@}*/
01040 
01041 /*!
01042  * @name Register ADC_SC2, field ACFE[5] (RW)
01043  *
01044  * Enables the compare function.
01045  *
01046  * Values:
01047  * - 0 - Compare function disabled.
01048  * - 1 - Compare function enabled.
01049  */
01050 /*@{*/
01051 #define BP_ADC_SC2_ACFE      (5U)          /*!< Bit position for ADC_SC2_ACFE. */
01052 #define BM_ADC_SC2_ACFE      (0x00000020U) /*!< Bit mask for ADC_SC2_ACFE. */
01053 #define BS_ADC_SC2_ACFE      (1U)          /*!< Bit field size in bits for ADC_SC2_ACFE. */
01054 
01055 /*! @brief Read current value of the ADC_SC2_ACFE field. */
01056 #define BR_ADC_SC2_ACFE(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACFE)))
01057 
01058 /*! @brief Format value for bitfield ADC_SC2_ACFE. */
01059 #define BF_ADC_SC2_ACFE(v)   ((uint32_t)((uint32_t)(v) << BP_ADC_SC2_ACFE) & BM_ADC_SC2_ACFE)
01060 
01061 /*! @brief Set the ACFE field to a new value. */
01062 #define BW_ADC_SC2_ACFE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACFE), v))
01063 /*@}*/
01064 
01065 /*!
01066  * @name Register ADC_SC2, field ADTRG[6] (RW)
01067  *
01068  * Selects the type of trigger used for initiating a conversion. Two types of
01069  * trigger are selectable: Software trigger: When software trigger is selected, a
01070  * conversion is initiated following a write to SC1A. Hardware trigger: When
01071  * hardware trigger is selected, a conversion is initiated following the assertion of
01072  * the ADHWT input after a pulse of the ADHWTSn input.
01073  *
01074  * Values:
01075  * - 0 - Software trigger selected.
01076  * - 1 - Hardware trigger selected.
01077  */
01078 /*@{*/
01079 #define BP_ADC_SC2_ADTRG     (6U)          /*!< Bit position for ADC_SC2_ADTRG. */
01080 #define BM_ADC_SC2_ADTRG     (0x00000040U) /*!< Bit mask for ADC_SC2_ADTRG. */
01081 #define BS_ADC_SC2_ADTRG     (1U)          /*!< Bit field size in bits for ADC_SC2_ADTRG. */
01082 
01083 /*! @brief Read current value of the ADC_SC2_ADTRG field. */
01084 #define BR_ADC_SC2_ADTRG(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ADTRG)))
01085 
01086 /*! @brief Format value for bitfield ADC_SC2_ADTRG. */
01087 #define BF_ADC_SC2_ADTRG(v)  ((uint32_t)((uint32_t)(v) << BP_ADC_SC2_ADTRG) & BM_ADC_SC2_ADTRG)
01088 
01089 /*! @brief Set the ADTRG field to a new value. */
01090 #define BW_ADC_SC2_ADTRG(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ADTRG), v))
01091 /*@}*/
01092 
01093 /*!
01094  * @name Register ADC_SC2, field ADACT[7] (RO)
01095  *
01096  * Indicates that a conversion or hardware averaging is in progress. ADACT is
01097  * set when a conversion is initiated and cleared when a conversion is completed or
01098  * aborted.
01099  *
01100  * Values:
01101  * - 0 - Conversion not in progress.
01102  * - 1 - Conversion in progress.
01103  */
01104 /*@{*/
01105 #define BP_ADC_SC2_ADACT     (7U)          /*!< Bit position for ADC_SC2_ADACT. */
01106 #define BM_ADC_SC2_ADACT     (0x00000080U) /*!< Bit mask for ADC_SC2_ADACT. */
01107 #define BS_ADC_SC2_ADACT     (1U)          /*!< Bit field size in bits for ADC_SC2_ADACT. */
01108 
01109 /*! @brief Read current value of the ADC_SC2_ADACT field. */
01110 #define BR_ADC_SC2_ADACT(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ADACT)))
01111 /*@}*/
01112 
01113 /*******************************************************************************
01114  * HW_ADC_SC3 - Status and Control Register 3
01115  ******************************************************************************/
01116 
01117 /*!
01118  * @brief HW_ADC_SC3 - Status and Control Register 3 (RW)
01119  *
01120  * Reset value: 0x00000000U
01121  *
01122  * The Status and Control Register 3 (SC3) controls the calibration, continuous
01123  * convert, and hardware averaging functions of the ADC module.
01124  */
01125 typedef union _hw_adc_sc3
01126 {
01127     uint32_t U;
01128     struct _hw_adc_sc3_bitfields
01129     {
01130         uint32_t AVGS : 2;             /*!< [1:0] Hardware Average Select */
01131         uint32_t AVGE : 1;             /*!< [2] Hardware Average Enable */
01132         uint32_t ADCO : 1;             /*!< [3] Continuous Conversion Enable */
01133         uint32_t RESERVED0 : 2;        /*!< [5:4]  */
01134         uint32_t CALF : 1;             /*!< [6] Calibration Failed Flag */
01135         uint32_t CAL : 1;              /*!< [7] Calibration */
01136         uint32_t RESERVED1 : 24;       /*!< [31:8]  */
01137     } B;
01138 } hw_adc_sc3_t;
01139 
01140 /*!
01141  * @name Constants and macros for entire ADC_SC3 register
01142  */
01143 /*@{*/
01144 #define HW_ADC_SC3_ADDR(x)       ((x) + 0x24U)
01145 
01146 #define HW_ADC_SC3(x)            (*(__IO hw_adc_sc3_t *) HW_ADC_SC3_ADDR(x))
01147 #define HW_ADC_SC3_RD(x)         (ADDRESS_READ(hw_adc_sc3_t, HW_ADC_SC3_ADDR(x)))
01148 #define HW_ADC_SC3_WR(x, v)      (ADDRESS_WRITE(hw_adc_sc3_t, HW_ADC_SC3_ADDR(x), v))
01149 #define HW_ADC_SC3_SET(x, v)     (HW_ADC_SC3_WR(x, HW_ADC_SC3_RD(x) |  (v)))
01150 #define HW_ADC_SC3_CLR(x, v)     (HW_ADC_SC3_WR(x, HW_ADC_SC3_RD(x) & ~(v)))
01151 #define HW_ADC_SC3_TOG(x, v)     (HW_ADC_SC3_WR(x, HW_ADC_SC3_RD(x) ^  (v)))
01152 /*@}*/
01153 
01154 /*
01155  * Constants & macros for individual ADC_SC3 bitfields
01156  */
01157 
01158 /*!
01159  * @name Register ADC_SC3, field AVGS[1:0] (RW)
01160  *
01161  * Determines how many ADC conversions will be averaged to create the ADC
01162  * average result.
01163  *
01164  * Values:
01165  * - 00 - 4 samples averaged.
01166  * - 01 - 8 samples averaged.
01167  * - 10 - 16 samples averaged.
01168  * - 11 - 32 samples averaged.
01169  */
01170 /*@{*/
01171 #define BP_ADC_SC3_AVGS      (0U)          /*!< Bit position for ADC_SC3_AVGS. */
01172 #define BM_ADC_SC3_AVGS      (0x00000003U) /*!< Bit mask for ADC_SC3_AVGS. */
01173 #define BS_ADC_SC3_AVGS      (2U)          /*!< Bit field size in bits for ADC_SC3_AVGS. */
01174 
01175 /*! @brief Read current value of the ADC_SC3_AVGS field. */
01176 #define BR_ADC_SC3_AVGS(x)   (UNION_READ(hw_adc_sc3_t, HW_ADC_SC3_ADDR(x), U, B.AVGS))
01177 
01178 /*! @brief Format value for bitfield ADC_SC3_AVGS. */
01179 #define BF_ADC_SC3_AVGS(v)   ((uint32_t)((uint32_t)(v) << BP_ADC_SC3_AVGS) & BM_ADC_SC3_AVGS)
01180 
01181 /*! @brief Set the AVGS field to a new value. */
01182 #define BW_ADC_SC3_AVGS(x, v) (HW_ADC_SC3_WR(x, (HW_ADC_SC3_RD(x) & ~BM_ADC_SC3_AVGS) | BF_ADC_SC3_AVGS(v)))
01183 /*@}*/
01184 
01185 /*!
01186  * @name Register ADC_SC3, field AVGE[2] (RW)
01187  *
01188  * Enables the hardware average function of the ADC.
01189  *
01190  * Values:
01191  * - 0 - Hardware average function disabled.
01192  * - 1 - Hardware average function enabled.
01193  */
01194 /*@{*/
01195 #define BP_ADC_SC3_AVGE      (2U)          /*!< Bit position for ADC_SC3_AVGE. */
01196 #define BM_ADC_SC3_AVGE      (0x00000004U) /*!< Bit mask for ADC_SC3_AVGE. */
01197 #define BS_ADC_SC3_AVGE      (1U)          /*!< Bit field size in bits for ADC_SC3_AVGE. */
01198 
01199 /*! @brief Read current value of the ADC_SC3_AVGE field. */
01200 #define BR_ADC_SC3_AVGE(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_AVGE)))
01201 
01202 /*! @brief Format value for bitfield ADC_SC3_AVGE. */
01203 #define BF_ADC_SC3_AVGE(v)   ((uint32_t)((uint32_t)(v) << BP_ADC_SC3_AVGE) & BM_ADC_SC3_AVGE)
01204 
01205 /*! @brief Set the AVGE field to a new value. */
01206 #define BW_ADC_SC3_AVGE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_AVGE), v))
01207 /*@}*/
01208 
01209 /*!
01210  * @name Register ADC_SC3, field ADCO[3] (RW)
01211  *
01212  * Enables continuous conversions.
01213  *
01214  * Values:
01215  * - 0 - One conversion or one set of conversions if the hardware average
01216  *     function is enabled, that is, AVGE=1, after initiating a conversion.
01217  * - 1 - Continuous conversions or sets of conversions if the hardware average
01218  *     function is enabled, that is, AVGE=1, after initiating a conversion.
01219  */
01220 /*@{*/
01221 #define BP_ADC_SC3_ADCO      (3U)          /*!< Bit position for ADC_SC3_ADCO. */
01222 #define BM_ADC_SC3_ADCO      (0x00000008U) /*!< Bit mask for ADC_SC3_ADCO. */
01223 #define BS_ADC_SC3_ADCO      (1U)          /*!< Bit field size in bits for ADC_SC3_ADCO. */
01224 
01225 /*! @brief Read current value of the ADC_SC3_ADCO field. */
01226 #define BR_ADC_SC3_ADCO(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_ADCO)))
01227 
01228 /*! @brief Format value for bitfield ADC_SC3_ADCO. */
01229 #define BF_ADC_SC3_ADCO(v)   ((uint32_t)((uint32_t)(v) << BP_ADC_SC3_ADCO) & BM_ADC_SC3_ADCO)
01230 
01231 /*! @brief Set the ADCO field to a new value. */
01232 #define BW_ADC_SC3_ADCO(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_ADCO), v))
01233 /*@}*/
01234 
01235 /*!
01236  * @name Register ADC_SC3, field CALF[6] (RO)
01237  *
01238  * Displays the result of the calibration sequence. The calibration sequence
01239  * will fail if SC2[ADTRG] = 1, any ADC register is written, or any stop mode is
01240  * entered before the calibration sequence completes. Writing 1 to CALF clears it.
01241  *
01242  * Values:
01243  * - 0 - Calibration completed normally.
01244  * - 1 - Calibration failed. ADC accuracy specifications are not guaranteed.
01245  */
01246 /*@{*/
01247 #define BP_ADC_SC3_CALF      (6U)          /*!< Bit position for ADC_SC3_CALF. */
01248 #define BM_ADC_SC3_CALF      (0x00000040U) /*!< Bit mask for ADC_SC3_CALF. */
01249 #define BS_ADC_SC3_CALF      (1U)          /*!< Bit field size in bits for ADC_SC3_CALF. */
01250 
01251 /*! @brief Read current value of the ADC_SC3_CALF field. */
01252 #define BR_ADC_SC3_CALF(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_CALF)))
01253 /*@}*/
01254 
01255 /*!
01256  * @name Register ADC_SC3, field CAL[7] (RW)
01257  *
01258  * Begins the calibration sequence when set. This field stays set while the
01259  * calibration is in progress and is cleared when the calibration sequence is
01260  * completed. CALF must be checked to determine the result of the calibration sequence.
01261  * Once started, the calibration routine cannot be interrupted by writes to the
01262  * ADC registers or the results will be invalid and CALF will set. Setting CAL
01263  * will abort any current conversion.
01264  */
01265 /*@{*/
01266 #define BP_ADC_SC3_CAL       (7U)          /*!< Bit position for ADC_SC3_CAL. */
01267 #define BM_ADC_SC3_CAL       (0x00000080U) /*!< Bit mask for ADC_SC3_CAL. */
01268 #define BS_ADC_SC3_CAL       (1U)          /*!< Bit field size in bits for ADC_SC3_CAL. */
01269 
01270 /*! @brief Read current value of the ADC_SC3_CAL field. */
01271 #define BR_ADC_SC3_CAL(x)    (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_CAL)))
01272 
01273 /*! @brief Format value for bitfield ADC_SC3_CAL. */
01274 #define BF_ADC_SC3_CAL(v)    ((uint32_t)((uint32_t)(v) << BP_ADC_SC3_CAL) & BM_ADC_SC3_CAL)
01275 
01276 /*! @brief Set the CAL field to a new value. */
01277 #define BW_ADC_SC3_CAL(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_CAL), v))
01278 /*@}*/
01279 
01280 /*******************************************************************************
01281  * HW_ADC_OFS - ADC Offset Correction Register
01282  ******************************************************************************/
01283 
01284 /*!
01285  * @brief HW_ADC_OFS - ADC Offset Correction Register (RW)
01286  *
01287  * Reset value: 0x00000004U
01288  *
01289  * The ADC Offset Correction Register (OFS) contains the user-selected or
01290  * calibration-generated offset error correction value. This register is a 2's
01291  * complement, left-justified, 16-bit value . The value in OFS is subtracted from the
01292  * conversion and the result is transferred into the result registers, Rn. If the
01293  * result is greater than the maximum or less than the minimum result value, it is
01294  * forced to the appropriate limit for the current mode of operation.
01295  */
01296 typedef union _hw_adc_ofs
01297 {
01298     uint32_t U;
01299     struct _hw_adc_ofs_bitfields
01300     {
01301         uint32_t OFS : 16;             /*!< [15:0] Offset Error Correction Value */
01302         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
01303     } B;
01304 } hw_adc_ofs_t;
01305 
01306 /*!
01307  * @name Constants and macros for entire ADC_OFS register
01308  */
01309 /*@{*/
01310 #define HW_ADC_OFS_ADDR(x)       ((x) + 0x28U)
01311 
01312 #define HW_ADC_OFS(x)            (*(__IO hw_adc_ofs_t *) HW_ADC_OFS_ADDR(x))
01313 #define HW_ADC_OFS_RD(x)         (ADDRESS_READ(hw_adc_ofs_t, HW_ADC_OFS_ADDR(x)))
01314 #define HW_ADC_OFS_WR(x, v)      (ADDRESS_WRITE(hw_adc_ofs_t, HW_ADC_OFS_ADDR(x), v))
01315 #define HW_ADC_OFS_SET(x, v)     (HW_ADC_OFS_WR(x, HW_ADC_OFS_RD(x) |  (v)))
01316 #define HW_ADC_OFS_CLR(x, v)     (HW_ADC_OFS_WR(x, HW_ADC_OFS_RD(x) & ~(v)))
01317 #define HW_ADC_OFS_TOG(x, v)     (HW_ADC_OFS_WR(x, HW_ADC_OFS_RD(x) ^  (v)))
01318 /*@}*/
01319 
01320 /*
01321  * Constants & macros for individual ADC_OFS bitfields
01322  */
01323 
01324 /*!
01325  * @name Register ADC_OFS, field OFS[15:0] (RW)
01326  */
01327 /*@{*/
01328 #define BP_ADC_OFS_OFS       (0U)          /*!< Bit position for ADC_OFS_OFS. */
01329 #define BM_ADC_OFS_OFS       (0x0000FFFFU) /*!< Bit mask for ADC_OFS_OFS. */
01330 #define BS_ADC_OFS_OFS       (16U)         /*!< Bit field size in bits for ADC_OFS_OFS. */
01331 
01332 /*! @brief Read current value of the ADC_OFS_OFS field. */
01333 #define BR_ADC_OFS_OFS(x)    (UNION_READ(hw_adc_ofs_t, HW_ADC_OFS_ADDR(x), U, B.OFS))
01334 
01335 /*! @brief Format value for bitfield ADC_OFS_OFS. */
01336 #define BF_ADC_OFS_OFS(v)    ((uint32_t)((uint32_t)(v) << BP_ADC_OFS_OFS) & BM_ADC_OFS_OFS)
01337 
01338 /*! @brief Set the OFS field to a new value. */
01339 #define BW_ADC_OFS_OFS(x, v) (HW_ADC_OFS_WR(x, (HW_ADC_OFS_RD(x) & ~BM_ADC_OFS_OFS) | BF_ADC_OFS_OFS(v)))
01340 /*@}*/
01341 
01342 /*******************************************************************************
01343  * HW_ADC_PG - ADC Plus-Side Gain Register
01344  ******************************************************************************/
01345 
01346 /*!
01347  * @brief HW_ADC_PG - ADC Plus-Side Gain Register (RW)
01348  *
01349  * Reset value: 0x00008200U
01350  *
01351  * The Plus-Side Gain Register (PG) contains the gain error correction for the
01352  * plus-side input in differential mode or the overall conversion in single-ended
01353  * mode. PG, a 16-bit real number in binary format, is the gain adjustment
01354  * factor, with the radix point fixed between ADPG15 and ADPG14. This register must be
01355  * written by the user with the value described in the calibration procedure.
01356  * Otherwise, the gain error specifications may not be met.
01357  */
01358 typedef union _hw_adc_pg
01359 {
01360     uint32_t U;
01361     struct _hw_adc_pg_bitfields
01362     {
01363         uint32_t PG : 16;              /*!< [15:0] Plus-Side Gain */
01364         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
01365     } B;
01366 } hw_adc_pg_t;
01367 
01368 /*!
01369  * @name Constants and macros for entire ADC_PG register
01370  */
01371 /*@{*/
01372 #define HW_ADC_PG_ADDR(x)        ((x) + 0x2CU)
01373 
01374 #define HW_ADC_PG(x)             (*(__IO hw_adc_pg_t *) HW_ADC_PG_ADDR(x))
01375 #define HW_ADC_PG_RD(x)          (ADDRESS_READ(hw_adc_pg_t, HW_ADC_PG_ADDR(x)))
01376 #define HW_ADC_PG_WR(x, v)       (ADDRESS_WRITE(hw_adc_pg_t, HW_ADC_PG_ADDR(x), v))
01377 #define HW_ADC_PG_SET(x, v)      (HW_ADC_PG_WR(x, HW_ADC_PG_RD(x) |  (v)))
01378 #define HW_ADC_PG_CLR(x, v)      (HW_ADC_PG_WR(x, HW_ADC_PG_RD(x) & ~(v)))
01379 #define HW_ADC_PG_TOG(x, v)      (HW_ADC_PG_WR(x, HW_ADC_PG_RD(x) ^  (v)))
01380 /*@}*/
01381 
01382 /*
01383  * Constants & macros for individual ADC_PG bitfields
01384  */
01385 
01386 /*!
01387  * @name Register ADC_PG, field PG[15:0] (RW)
01388  */
01389 /*@{*/
01390 #define BP_ADC_PG_PG         (0U)          /*!< Bit position for ADC_PG_PG. */
01391 #define BM_ADC_PG_PG         (0x0000FFFFU) /*!< Bit mask for ADC_PG_PG. */
01392 #define BS_ADC_PG_PG         (16U)         /*!< Bit field size in bits for ADC_PG_PG. */
01393 
01394 /*! @brief Read current value of the ADC_PG_PG field. */
01395 #define BR_ADC_PG_PG(x)      (UNION_READ(hw_adc_pg_t, HW_ADC_PG_ADDR(x), U, B.PG))
01396 
01397 /*! @brief Format value for bitfield ADC_PG_PG. */
01398 #define BF_ADC_PG_PG(v)      ((uint32_t)((uint32_t)(v) << BP_ADC_PG_PG) & BM_ADC_PG_PG)
01399 
01400 /*! @brief Set the PG field to a new value. */
01401 #define BW_ADC_PG_PG(x, v)   (HW_ADC_PG_WR(x, (HW_ADC_PG_RD(x) & ~BM_ADC_PG_PG) | BF_ADC_PG_PG(v)))
01402 /*@}*/
01403 
01404 /*******************************************************************************
01405  * HW_ADC_MG - ADC Minus-Side Gain Register
01406  ******************************************************************************/
01407 
01408 /*!
01409  * @brief HW_ADC_MG - ADC Minus-Side Gain Register (RW)
01410  *
01411  * Reset value: 0x00008200U
01412  *
01413  * The Minus-Side Gain Register (MG) contains the gain error correction for the
01414  * minus-side input in differential mode. This register is ignored in
01415  * single-ended mode. MG, a 16-bit real number in binary format, is the gain adjustment
01416  * factor, with the radix point fixed between ADMG15 and ADMG14. This register must
01417  * be written by the user with the value described in the calibration procedure.
01418  * Otherwise, the gain error specifications may not be met.
01419  */
01420 typedef union _hw_adc_mg
01421 {
01422     uint32_t U;
01423     struct _hw_adc_mg_bitfields
01424     {
01425         uint32_t MG : 16;              /*!< [15:0] Minus-Side Gain */
01426         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
01427     } B;
01428 } hw_adc_mg_t;
01429 
01430 /*!
01431  * @name Constants and macros for entire ADC_MG register
01432  */
01433 /*@{*/
01434 #define HW_ADC_MG_ADDR(x)        ((x) + 0x30U)
01435 
01436 #define HW_ADC_MG(x)             (*(__IO hw_adc_mg_t *) HW_ADC_MG_ADDR(x))
01437 #define HW_ADC_MG_RD(x)          (ADDRESS_READ(hw_adc_mg_t, HW_ADC_MG_ADDR(x)))
01438 #define HW_ADC_MG_WR(x, v)       (ADDRESS_WRITE(hw_adc_mg_t, HW_ADC_MG_ADDR(x), v))
01439 #define HW_ADC_MG_SET(x, v)      (HW_ADC_MG_WR(x, HW_ADC_MG_RD(x) |  (v)))
01440 #define HW_ADC_MG_CLR(x, v)      (HW_ADC_MG_WR(x, HW_ADC_MG_RD(x) & ~(v)))
01441 #define HW_ADC_MG_TOG(x, v)      (HW_ADC_MG_WR(x, HW_ADC_MG_RD(x) ^  (v)))
01442 /*@}*/
01443 
01444 /*
01445  * Constants & macros for individual ADC_MG bitfields
01446  */
01447 
01448 /*!
01449  * @name Register ADC_MG, field MG[15:0] (RW)
01450  */
01451 /*@{*/
01452 #define BP_ADC_MG_MG         (0U)          /*!< Bit position for ADC_MG_MG. */
01453 #define BM_ADC_MG_MG         (0x0000FFFFU) /*!< Bit mask for ADC_MG_MG. */
01454 #define BS_ADC_MG_MG         (16U)         /*!< Bit field size in bits for ADC_MG_MG. */
01455 
01456 /*! @brief Read current value of the ADC_MG_MG field. */
01457 #define BR_ADC_MG_MG(x)      (UNION_READ(hw_adc_mg_t, HW_ADC_MG_ADDR(x), U, B.MG))
01458 
01459 /*! @brief Format value for bitfield ADC_MG_MG. */
01460 #define BF_ADC_MG_MG(v)      ((uint32_t)((uint32_t)(v) << BP_ADC_MG_MG) & BM_ADC_MG_MG)
01461 
01462 /*! @brief Set the MG field to a new value. */
01463 #define BW_ADC_MG_MG(x, v)   (HW_ADC_MG_WR(x, (HW_ADC_MG_RD(x) & ~BM_ADC_MG_MG) | BF_ADC_MG_MG(v)))
01464 /*@}*/
01465 
01466 /*******************************************************************************
01467  * HW_ADC_CLPD - ADC Plus-Side General Calibration Value Register
01468  ******************************************************************************/
01469 
01470 /*!
01471  * @brief HW_ADC_CLPD - ADC Plus-Side General Calibration Value Register (RW)
01472  *
01473  * Reset value: 0x0000000AU
01474  *
01475  * The Plus-Side General Calibration Value Registers (CLPx) contain calibration
01476  * information that is generated by the calibration function. These registers
01477  * contain seven calibration values of varying widths: CLP0[5:0], CLP1[6:0],
01478  * CLP2[7:0], CLP3[8:0], CLP4[9:0], CLPS[5:0], and CLPD[5:0]. CLPx are automatically set
01479  * when the self-calibration sequence is done, that is, CAL is cleared. If these
01480  * registers are written by the user after calibration, the linearity error
01481  * specifications may not be met.
01482  */
01483 typedef union _hw_adc_clpd
01484 {
01485     uint32_t U;
01486     struct _hw_adc_clpd_bitfields
01487     {
01488         uint32_t CLPD : 6;             /*!< [5:0]  */
01489         uint32_t RESERVED0 : 26;       /*!< [31:6]  */
01490     } B;
01491 } hw_adc_clpd_t;
01492 
01493 /*!
01494  * @name Constants and macros for entire ADC_CLPD register
01495  */
01496 /*@{*/
01497 #define HW_ADC_CLPD_ADDR(x)      ((x) + 0x34U)
01498 
01499 #define HW_ADC_CLPD(x)           (*(__IO hw_adc_clpd_t *) HW_ADC_CLPD_ADDR(x))
01500 #define HW_ADC_CLPD_RD(x)        (ADDRESS_READ(hw_adc_clpd_t, HW_ADC_CLPD_ADDR(x)))
01501 #define HW_ADC_CLPD_WR(x, v)     (ADDRESS_WRITE(hw_adc_clpd_t, HW_ADC_CLPD_ADDR(x), v))
01502 #define HW_ADC_CLPD_SET(x, v)    (HW_ADC_CLPD_WR(x, HW_ADC_CLPD_RD(x) |  (v)))
01503 #define HW_ADC_CLPD_CLR(x, v)    (HW_ADC_CLPD_WR(x, HW_ADC_CLPD_RD(x) & ~(v)))
01504 #define HW_ADC_CLPD_TOG(x, v)    (HW_ADC_CLPD_WR(x, HW_ADC_CLPD_RD(x) ^  (v)))
01505 /*@}*/
01506 
01507 /*
01508  * Constants & macros for individual ADC_CLPD bitfields
01509  */
01510 
01511 /*!
01512  * @name Register ADC_CLPD, field CLPD[5:0] (RW)
01513  *
01514  * Calibration Value
01515  */
01516 /*@{*/
01517 #define BP_ADC_CLPD_CLPD     (0U)          /*!< Bit position for ADC_CLPD_CLPD. */
01518 #define BM_ADC_CLPD_CLPD     (0x0000003FU) /*!< Bit mask for ADC_CLPD_CLPD. */
01519 #define BS_ADC_CLPD_CLPD     (6U)          /*!< Bit field size in bits for ADC_CLPD_CLPD. */
01520 
01521 /*! @brief Read current value of the ADC_CLPD_CLPD field. */
01522 #define BR_ADC_CLPD_CLPD(x)  (UNION_READ(hw_adc_clpd_t, HW_ADC_CLPD_ADDR(x), U, B.CLPD))
01523 
01524 /*! @brief Format value for bitfield ADC_CLPD_CLPD. */
01525 #define BF_ADC_CLPD_CLPD(v)  ((uint32_t)((uint32_t)(v) << BP_ADC_CLPD_CLPD) & BM_ADC_CLPD_CLPD)
01526 
01527 /*! @brief Set the CLPD field to a new value. */
01528 #define BW_ADC_CLPD_CLPD(x, v) (HW_ADC_CLPD_WR(x, (HW_ADC_CLPD_RD(x) & ~BM_ADC_CLPD_CLPD) | BF_ADC_CLPD_CLPD(v)))
01529 /*@}*/
01530 
01531 /*******************************************************************************
01532  * HW_ADC_CLPS - ADC Plus-Side General Calibration Value Register
01533  ******************************************************************************/
01534 
01535 /*!
01536  * @brief HW_ADC_CLPS - ADC Plus-Side General Calibration Value Register (RW)
01537  *
01538  * Reset value: 0x00000020U
01539  *
01540  * For more information, see CLPD register description.
01541  */
01542 typedef union _hw_adc_clps
01543 {
01544     uint32_t U;
01545     struct _hw_adc_clps_bitfields
01546     {
01547         uint32_t CLPS : 6;             /*!< [5:0]  */
01548         uint32_t RESERVED0 : 26;       /*!< [31:6]  */
01549     } B;
01550 } hw_adc_clps_t;
01551 
01552 /*!
01553  * @name Constants and macros for entire ADC_CLPS register
01554  */
01555 /*@{*/
01556 #define HW_ADC_CLPS_ADDR(x)      ((x) + 0x38U)
01557 
01558 #define HW_ADC_CLPS(x)           (*(__IO hw_adc_clps_t *) HW_ADC_CLPS_ADDR(x))
01559 #define HW_ADC_CLPS_RD(x)        (ADDRESS_READ(hw_adc_clps_t, HW_ADC_CLPS_ADDR(x)))
01560 #define HW_ADC_CLPS_WR(x, v)     (ADDRESS_WRITE(hw_adc_clps_t, HW_ADC_CLPS_ADDR(x), v))
01561 #define HW_ADC_CLPS_SET(x, v)    (HW_ADC_CLPS_WR(x, HW_ADC_CLPS_RD(x) |  (v)))
01562 #define HW_ADC_CLPS_CLR(x, v)    (HW_ADC_CLPS_WR(x, HW_ADC_CLPS_RD(x) & ~(v)))
01563 #define HW_ADC_CLPS_TOG(x, v)    (HW_ADC_CLPS_WR(x, HW_ADC_CLPS_RD(x) ^  (v)))
01564 /*@}*/
01565 
01566 /*
01567  * Constants & macros for individual ADC_CLPS bitfields
01568  */
01569 
01570 /*!
01571  * @name Register ADC_CLPS, field CLPS[5:0] (RW)
01572  *
01573  * Calibration Value
01574  */
01575 /*@{*/
01576 #define BP_ADC_CLPS_CLPS     (0U)          /*!< Bit position for ADC_CLPS_CLPS. */
01577 #define BM_ADC_CLPS_CLPS     (0x0000003FU) /*!< Bit mask for ADC_CLPS_CLPS. */
01578 #define BS_ADC_CLPS_CLPS     (6U)          /*!< Bit field size in bits for ADC_CLPS_CLPS. */
01579 
01580 /*! @brief Read current value of the ADC_CLPS_CLPS field. */
01581 #define BR_ADC_CLPS_CLPS(x)  (UNION_READ(hw_adc_clps_t, HW_ADC_CLPS_ADDR(x), U, B.CLPS))
01582 
01583 /*! @brief Format value for bitfield ADC_CLPS_CLPS. */
01584 #define BF_ADC_CLPS_CLPS(v)  ((uint32_t)((uint32_t)(v) << BP_ADC_CLPS_CLPS) & BM_ADC_CLPS_CLPS)
01585 
01586 /*! @brief Set the CLPS field to a new value. */
01587 #define BW_ADC_CLPS_CLPS(x, v) (HW_ADC_CLPS_WR(x, (HW_ADC_CLPS_RD(x) & ~BM_ADC_CLPS_CLPS) | BF_ADC_CLPS_CLPS(v)))
01588 /*@}*/
01589 
01590 /*******************************************************************************
01591  * HW_ADC_CLP4 - ADC Plus-Side General Calibration Value Register
01592  ******************************************************************************/
01593 
01594 /*!
01595  * @brief HW_ADC_CLP4 - ADC Plus-Side General Calibration Value Register (RW)
01596  *
01597  * Reset value: 0x00000200U
01598  *
01599  * For more information, see CLPD register description.
01600  */
01601 typedef union _hw_adc_clp4
01602 {
01603     uint32_t U;
01604     struct _hw_adc_clp4_bitfields
01605     {
01606         uint32_t CLP4 : 10;            /*!< [9:0]  */
01607         uint32_t RESERVED0 : 22;       /*!< [31:10]  */
01608     } B;
01609 } hw_adc_clp4_t;
01610 
01611 /*!
01612  * @name Constants and macros for entire ADC_CLP4 register
01613  */
01614 /*@{*/
01615 #define HW_ADC_CLP4_ADDR(x)      ((x) + 0x3CU)
01616 
01617 #define HW_ADC_CLP4(x)           (*(__IO hw_adc_clp4_t *) HW_ADC_CLP4_ADDR(x))
01618 #define HW_ADC_CLP4_RD(x)        (ADDRESS_READ(hw_adc_clp4_t, HW_ADC_CLP4_ADDR(x)))
01619 #define HW_ADC_CLP4_WR(x, v)     (ADDRESS_WRITE(hw_adc_clp4_t, HW_ADC_CLP4_ADDR(x), v))
01620 #define HW_ADC_CLP4_SET(x, v)    (HW_ADC_CLP4_WR(x, HW_ADC_CLP4_RD(x) |  (v)))
01621 #define HW_ADC_CLP4_CLR(x, v)    (HW_ADC_CLP4_WR(x, HW_ADC_CLP4_RD(x) & ~(v)))
01622 #define HW_ADC_CLP4_TOG(x, v)    (HW_ADC_CLP4_WR(x, HW_ADC_CLP4_RD(x) ^  (v)))
01623 /*@}*/
01624 
01625 /*
01626  * Constants & macros for individual ADC_CLP4 bitfields
01627  */
01628 
01629 /*!
01630  * @name Register ADC_CLP4, field CLP4[9:0] (RW)
01631  *
01632  * Calibration Value
01633  */
01634 /*@{*/
01635 #define BP_ADC_CLP4_CLP4     (0U)          /*!< Bit position for ADC_CLP4_CLP4. */
01636 #define BM_ADC_CLP4_CLP4     (0x000003FFU) /*!< Bit mask for ADC_CLP4_CLP4. */
01637 #define BS_ADC_CLP4_CLP4     (10U)         /*!< Bit field size in bits for ADC_CLP4_CLP4. */
01638 
01639 /*! @brief Read current value of the ADC_CLP4_CLP4 field. */
01640 #define BR_ADC_CLP4_CLP4(x)  (UNION_READ(hw_adc_clp4_t, HW_ADC_CLP4_ADDR(x), U, B.CLP4))
01641 
01642 /*! @brief Format value for bitfield ADC_CLP4_CLP4. */
01643 #define BF_ADC_CLP4_CLP4(v)  ((uint32_t)((uint32_t)(v) << BP_ADC_CLP4_CLP4) & BM_ADC_CLP4_CLP4)
01644 
01645 /*! @brief Set the CLP4 field to a new value. */
01646 #define BW_ADC_CLP4_CLP4(x, v) (HW_ADC_CLP4_WR(x, (HW_ADC_CLP4_RD(x) & ~BM_ADC_CLP4_CLP4) | BF_ADC_CLP4_CLP4(v)))
01647 /*@}*/
01648 
01649 /*******************************************************************************
01650  * HW_ADC_CLP3 - ADC Plus-Side General Calibration Value Register
01651  ******************************************************************************/
01652 
01653 /*!
01654  * @brief HW_ADC_CLP3 - ADC Plus-Side General Calibration Value Register (RW)
01655  *
01656  * Reset value: 0x00000100U
01657  *
01658  * For more information, see CLPD register description.
01659  */
01660 typedef union _hw_adc_clp3
01661 {
01662     uint32_t U;
01663     struct _hw_adc_clp3_bitfields
01664     {
01665         uint32_t CLP3 : 9;             /*!< [8:0]  */
01666         uint32_t RESERVED0 : 23;       /*!< [31:9]  */
01667     } B;
01668 } hw_adc_clp3_t;
01669 
01670 /*!
01671  * @name Constants and macros for entire ADC_CLP3 register
01672  */
01673 /*@{*/
01674 #define HW_ADC_CLP3_ADDR(x)      ((x) + 0x40U)
01675 
01676 #define HW_ADC_CLP3(x)           (*(__IO hw_adc_clp3_t *) HW_ADC_CLP3_ADDR(x))
01677 #define HW_ADC_CLP3_RD(x)        (ADDRESS_READ(hw_adc_clp3_t, HW_ADC_CLP3_ADDR(x)))
01678 #define HW_ADC_CLP3_WR(x, v)     (ADDRESS_WRITE(hw_adc_clp3_t, HW_ADC_CLP3_ADDR(x), v))
01679 #define HW_ADC_CLP3_SET(x, v)    (HW_ADC_CLP3_WR(x, HW_ADC_CLP3_RD(x) |  (v)))
01680 #define HW_ADC_CLP3_CLR(x, v)    (HW_ADC_CLP3_WR(x, HW_ADC_CLP3_RD(x) & ~(v)))
01681 #define HW_ADC_CLP3_TOG(x, v)    (HW_ADC_CLP3_WR(x, HW_ADC_CLP3_RD(x) ^  (v)))
01682 /*@}*/
01683 
01684 /*
01685  * Constants & macros for individual ADC_CLP3 bitfields
01686  */
01687 
01688 /*!
01689  * @name Register ADC_CLP3, field CLP3[8:0] (RW)
01690  *
01691  * Calibration Value
01692  */
01693 /*@{*/
01694 #define BP_ADC_CLP3_CLP3     (0U)          /*!< Bit position for ADC_CLP3_CLP3. */
01695 #define BM_ADC_CLP3_CLP3     (0x000001FFU) /*!< Bit mask for ADC_CLP3_CLP3. */
01696 #define BS_ADC_CLP3_CLP3     (9U)          /*!< Bit field size in bits for ADC_CLP3_CLP3. */
01697 
01698 /*! @brief Read current value of the ADC_CLP3_CLP3 field. */
01699 #define BR_ADC_CLP3_CLP3(x)  (UNION_READ(hw_adc_clp3_t, HW_ADC_CLP3_ADDR(x), U, B.CLP3))
01700 
01701 /*! @brief Format value for bitfield ADC_CLP3_CLP3. */
01702 #define BF_ADC_CLP3_CLP3(v)  ((uint32_t)((uint32_t)(v) << BP_ADC_CLP3_CLP3) & BM_ADC_CLP3_CLP3)
01703 
01704 /*! @brief Set the CLP3 field to a new value. */
01705 #define BW_ADC_CLP3_CLP3(x, v) (HW_ADC_CLP3_WR(x, (HW_ADC_CLP3_RD(x) & ~BM_ADC_CLP3_CLP3) | BF_ADC_CLP3_CLP3(v)))
01706 /*@}*/
01707 
01708 /*******************************************************************************
01709  * HW_ADC_CLP2 - ADC Plus-Side General Calibration Value Register
01710  ******************************************************************************/
01711 
01712 /*!
01713  * @brief HW_ADC_CLP2 - ADC Plus-Side General Calibration Value Register (RW)
01714  *
01715  * Reset value: 0x00000080U
01716  *
01717  * For more information, see CLPD register description.
01718  */
01719 typedef union _hw_adc_clp2
01720 {
01721     uint32_t U;
01722     struct _hw_adc_clp2_bitfields
01723     {
01724         uint32_t CLP2 : 8;             /*!< [7:0]  */
01725         uint32_t RESERVED0 : 24;       /*!< [31:8]  */
01726     } B;
01727 } hw_adc_clp2_t;
01728 
01729 /*!
01730  * @name Constants and macros for entire ADC_CLP2 register
01731  */
01732 /*@{*/
01733 #define HW_ADC_CLP2_ADDR(x)      ((x) + 0x44U)
01734 
01735 #define HW_ADC_CLP2(x)           (*(__IO hw_adc_clp2_t *) HW_ADC_CLP2_ADDR(x))
01736 #define HW_ADC_CLP2_RD(x)        (ADDRESS_READ(hw_adc_clp2_t, HW_ADC_CLP2_ADDR(x)))
01737 #define HW_ADC_CLP2_WR(x, v)     (ADDRESS_WRITE(hw_adc_clp2_t, HW_ADC_CLP2_ADDR(x), v))
01738 #define HW_ADC_CLP2_SET(x, v)    (HW_ADC_CLP2_WR(x, HW_ADC_CLP2_RD(x) |  (v)))
01739 #define HW_ADC_CLP2_CLR(x, v)    (HW_ADC_CLP2_WR(x, HW_ADC_CLP2_RD(x) & ~(v)))
01740 #define HW_ADC_CLP2_TOG(x, v)    (HW_ADC_CLP2_WR(x, HW_ADC_CLP2_RD(x) ^  (v)))
01741 /*@}*/
01742 
01743 /*
01744  * Constants & macros for individual ADC_CLP2 bitfields
01745  */
01746 
01747 /*!
01748  * @name Register ADC_CLP2, field CLP2[7:0] (RW)
01749  *
01750  * Calibration Value
01751  */
01752 /*@{*/
01753 #define BP_ADC_CLP2_CLP2     (0U)          /*!< Bit position for ADC_CLP2_CLP2. */
01754 #define BM_ADC_CLP2_CLP2     (0x000000FFU) /*!< Bit mask for ADC_CLP2_CLP2. */
01755 #define BS_ADC_CLP2_CLP2     (8U)          /*!< Bit field size in bits for ADC_CLP2_CLP2. */
01756 
01757 /*! @brief Read current value of the ADC_CLP2_CLP2 field. */
01758 #define BR_ADC_CLP2_CLP2(x)  (UNION_READ(hw_adc_clp2_t, HW_ADC_CLP2_ADDR(x), U, B.CLP2))
01759 
01760 /*! @brief Format value for bitfield ADC_CLP2_CLP2. */
01761 #define BF_ADC_CLP2_CLP2(v)  ((uint32_t)((uint32_t)(v) << BP_ADC_CLP2_CLP2) & BM_ADC_CLP2_CLP2)
01762 
01763 /*! @brief Set the CLP2 field to a new value. */
01764 #define BW_ADC_CLP2_CLP2(x, v) (HW_ADC_CLP2_WR(x, (HW_ADC_CLP2_RD(x) & ~BM_ADC_CLP2_CLP2) | BF_ADC_CLP2_CLP2(v)))
01765 /*@}*/
01766 
01767 /*******************************************************************************
01768  * HW_ADC_CLP1 - ADC Plus-Side General Calibration Value Register
01769  ******************************************************************************/
01770 
01771 /*!
01772  * @brief HW_ADC_CLP1 - ADC Plus-Side General Calibration Value Register (RW)
01773  *
01774  * Reset value: 0x00000040U
01775  *
01776  * For more information, see CLPD register description.
01777  */
01778 typedef union _hw_adc_clp1
01779 {
01780     uint32_t U;
01781     struct _hw_adc_clp1_bitfields
01782     {
01783         uint32_t CLP1 : 7;             /*!< [6:0]  */
01784         uint32_t RESERVED0 : 25;       /*!< [31:7]  */
01785     } B;
01786 } hw_adc_clp1_t;
01787 
01788 /*!
01789  * @name Constants and macros for entire ADC_CLP1 register
01790  */
01791 /*@{*/
01792 #define HW_ADC_CLP1_ADDR(x)      ((x) + 0x48U)
01793 
01794 #define HW_ADC_CLP1(x)           (*(__IO hw_adc_clp1_t *) HW_ADC_CLP1_ADDR(x))
01795 #define HW_ADC_CLP1_RD(x)        (ADDRESS_READ(hw_adc_clp1_t, HW_ADC_CLP1_ADDR(x)))
01796 #define HW_ADC_CLP1_WR(x, v)     (ADDRESS_WRITE(hw_adc_clp1_t, HW_ADC_CLP1_ADDR(x), v))
01797 #define HW_ADC_CLP1_SET(x, v)    (HW_ADC_CLP1_WR(x, HW_ADC_CLP1_RD(x) |  (v)))
01798 #define HW_ADC_CLP1_CLR(x, v)    (HW_ADC_CLP1_WR(x, HW_ADC_CLP1_RD(x) & ~(v)))
01799 #define HW_ADC_CLP1_TOG(x, v)    (HW_ADC_CLP1_WR(x, HW_ADC_CLP1_RD(x) ^  (v)))
01800 /*@}*/
01801 
01802 /*
01803  * Constants & macros for individual ADC_CLP1 bitfields
01804  */
01805 
01806 /*!
01807  * @name Register ADC_CLP1, field CLP1[6:0] (RW)
01808  *
01809  * Calibration Value
01810  */
01811 /*@{*/
01812 #define BP_ADC_CLP1_CLP1     (0U)          /*!< Bit position for ADC_CLP1_CLP1. */
01813 #define BM_ADC_CLP1_CLP1     (0x0000007FU) /*!< Bit mask for ADC_CLP1_CLP1. */
01814 #define BS_ADC_CLP1_CLP1     (7U)          /*!< Bit field size in bits for ADC_CLP1_CLP1. */
01815 
01816 /*! @brief Read current value of the ADC_CLP1_CLP1 field. */
01817 #define BR_ADC_CLP1_CLP1(x)  (UNION_READ(hw_adc_clp1_t, HW_ADC_CLP1_ADDR(x), U, B.CLP1))
01818 
01819 /*! @brief Format value for bitfield ADC_CLP1_CLP1. */
01820 #define BF_ADC_CLP1_CLP1(v)  ((uint32_t)((uint32_t)(v) << BP_ADC_CLP1_CLP1) & BM_ADC_CLP1_CLP1)
01821 
01822 /*! @brief Set the CLP1 field to a new value. */
01823 #define BW_ADC_CLP1_CLP1(x, v) (HW_ADC_CLP1_WR(x, (HW_ADC_CLP1_RD(x) & ~BM_ADC_CLP1_CLP1) | BF_ADC_CLP1_CLP1(v)))
01824 /*@}*/
01825 
01826 /*******************************************************************************
01827  * HW_ADC_CLP0 - ADC Plus-Side General Calibration Value Register
01828  ******************************************************************************/
01829 
01830 /*!
01831  * @brief HW_ADC_CLP0 - ADC Plus-Side General Calibration Value Register (RW)
01832  *
01833  * Reset value: 0x00000020U
01834  *
01835  * For more information, see CLPD register description.
01836  */
01837 typedef union _hw_adc_clp0
01838 {
01839     uint32_t U;
01840     struct _hw_adc_clp0_bitfields
01841     {
01842         uint32_t CLP0 : 6;             /*!< [5:0]  */
01843         uint32_t RESERVED0 : 26;       /*!< [31:6]  */
01844     } B;
01845 } hw_adc_clp0_t;
01846 
01847 /*!
01848  * @name Constants and macros for entire ADC_CLP0 register
01849  */
01850 /*@{*/
01851 #define HW_ADC_CLP0_ADDR(x)      ((x) + 0x4CU)
01852 
01853 #define HW_ADC_CLP0(x)           (*(__IO hw_adc_clp0_t *) HW_ADC_CLP0_ADDR(x))
01854 #define HW_ADC_CLP0_RD(x)        (ADDRESS_READ(hw_adc_clp0_t, HW_ADC_CLP0_ADDR(x)))
01855 #define HW_ADC_CLP0_WR(x, v)     (ADDRESS_WRITE(hw_adc_clp0_t, HW_ADC_CLP0_ADDR(x), v))
01856 #define HW_ADC_CLP0_SET(x, v)    (HW_ADC_CLP0_WR(x, HW_ADC_CLP0_RD(x) |  (v)))
01857 #define HW_ADC_CLP0_CLR(x, v)    (HW_ADC_CLP0_WR(x, HW_ADC_CLP0_RD(x) & ~(v)))
01858 #define HW_ADC_CLP0_TOG(x, v)    (HW_ADC_CLP0_WR(x, HW_ADC_CLP0_RD(x) ^  (v)))
01859 /*@}*/
01860 
01861 /*
01862  * Constants & macros for individual ADC_CLP0 bitfields
01863  */
01864 
01865 /*!
01866  * @name Register ADC_CLP0, field CLP0[5:0] (RW)
01867  *
01868  * Calibration Value
01869  */
01870 /*@{*/
01871 #define BP_ADC_CLP0_CLP0     (0U)          /*!< Bit position for ADC_CLP0_CLP0. */
01872 #define BM_ADC_CLP0_CLP0     (0x0000003FU) /*!< Bit mask for ADC_CLP0_CLP0. */
01873 #define BS_ADC_CLP0_CLP0     (6U)          /*!< Bit field size in bits for ADC_CLP0_CLP0. */
01874 
01875 /*! @brief Read current value of the ADC_CLP0_CLP0 field. */
01876 #define BR_ADC_CLP0_CLP0(x)  (UNION_READ(hw_adc_clp0_t, HW_ADC_CLP0_ADDR(x), U, B.CLP0))
01877 
01878 /*! @brief Format value for bitfield ADC_CLP0_CLP0. */
01879 #define BF_ADC_CLP0_CLP0(v)  ((uint32_t)((uint32_t)(v) << BP_ADC_CLP0_CLP0) & BM_ADC_CLP0_CLP0)
01880 
01881 /*! @brief Set the CLP0 field to a new value. */
01882 #define BW_ADC_CLP0_CLP0(x, v) (HW_ADC_CLP0_WR(x, (HW_ADC_CLP0_RD(x) & ~BM_ADC_CLP0_CLP0) | BF_ADC_CLP0_CLP0(v)))
01883 /*@}*/
01884 
01885 /*******************************************************************************
01886  * HW_ADC_CLMD - ADC Minus-Side General Calibration Value Register
01887  ******************************************************************************/
01888 
01889 /*!
01890  * @brief HW_ADC_CLMD - ADC Minus-Side General Calibration Value Register (RW)
01891  *
01892  * Reset value: 0x0000000AU
01893  *
01894  * The Minus-Side General Calibration Value (CLMx) registers contain calibration
01895  * information that is generated by the calibration function. These registers
01896  * contain seven calibration values of varying widths: CLM0[5:0], CLM1[6:0],
01897  * CLM2[7:0], CLM3[8:0], CLM4[9:0], CLMS[5:0], and CLMD[5:0]. CLMx are automatically
01898  * set when the self-calibration sequence is done, that is, CAL is cleared. If
01899  * these registers are written by the user after calibration, the linearity error
01900  * specifications may not be met.
01901  */
01902 typedef union _hw_adc_clmd
01903 {
01904     uint32_t U;
01905     struct _hw_adc_clmd_bitfields
01906     {
01907         uint32_t CLMD : 6;             /*!< [5:0]  */
01908         uint32_t RESERVED0 : 26;       /*!< [31:6]  */
01909     } B;
01910 } hw_adc_clmd_t;
01911 
01912 /*!
01913  * @name Constants and macros for entire ADC_CLMD register
01914  */
01915 /*@{*/
01916 #define HW_ADC_CLMD_ADDR(x)      ((x) + 0x54U)
01917 
01918 #define HW_ADC_CLMD(x)           (*(__IO hw_adc_clmd_t *) HW_ADC_CLMD_ADDR(x))
01919 #define HW_ADC_CLMD_RD(x)        (ADDRESS_READ(hw_adc_clmd_t, HW_ADC_CLMD_ADDR(x)))
01920 #define HW_ADC_CLMD_WR(x, v)     (ADDRESS_WRITE(hw_adc_clmd_t, HW_ADC_CLMD_ADDR(x), v))
01921 #define HW_ADC_CLMD_SET(x, v)    (HW_ADC_CLMD_WR(x, HW_ADC_CLMD_RD(x) |  (v)))
01922 #define HW_ADC_CLMD_CLR(x, v)    (HW_ADC_CLMD_WR(x, HW_ADC_CLMD_RD(x) & ~(v)))
01923 #define HW_ADC_CLMD_TOG(x, v)    (HW_ADC_CLMD_WR(x, HW_ADC_CLMD_RD(x) ^  (v)))
01924 /*@}*/
01925 
01926 /*
01927  * Constants & macros for individual ADC_CLMD bitfields
01928  */
01929 
01930 /*!
01931  * @name Register ADC_CLMD, field CLMD[5:0] (RW)
01932  *
01933  * Calibration Value
01934  */
01935 /*@{*/
01936 #define BP_ADC_CLMD_CLMD     (0U)          /*!< Bit position for ADC_CLMD_CLMD. */
01937 #define BM_ADC_CLMD_CLMD     (0x0000003FU) /*!< Bit mask for ADC_CLMD_CLMD. */
01938 #define BS_ADC_CLMD_CLMD     (6U)          /*!< Bit field size in bits for ADC_CLMD_CLMD. */
01939 
01940 /*! @brief Read current value of the ADC_CLMD_CLMD field. */
01941 #define BR_ADC_CLMD_CLMD(x)  (UNION_READ(hw_adc_clmd_t, HW_ADC_CLMD_ADDR(x), U, B.CLMD))
01942 
01943 /*! @brief Format value for bitfield ADC_CLMD_CLMD. */
01944 #define BF_ADC_CLMD_CLMD(v)  ((uint32_t)((uint32_t)(v) << BP_ADC_CLMD_CLMD) & BM_ADC_CLMD_CLMD)
01945 
01946 /*! @brief Set the CLMD field to a new value. */
01947 #define BW_ADC_CLMD_CLMD(x, v) (HW_ADC_CLMD_WR(x, (HW_ADC_CLMD_RD(x) & ~BM_ADC_CLMD_CLMD) | BF_ADC_CLMD_CLMD(v)))
01948 /*@}*/
01949 
01950 /*******************************************************************************
01951  * HW_ADC_CLMS - ADC Minus-Side General Calibration Value Register
01952  ******************************************************************************/
01953 
01954 /*!
01955  * @brief HW_ADC_CLMS - ADC Minus-Side General Calibration Value Register (RW)
01956  *
01957  * Reset value: 0x00000020U
01958  *
01959  * For more information, see CLMD register description.
01960  */
01961 typedef union _hw_adc_clms
01962 {
01963     uint32_t U;
01964     struct _hw_adc_clms_bitfields
01965     {
01966         uint32_t CLMS : 6;             /*!< [5:0]  */
01967         uint32_t RESERVED0 : 26;       /*!< [31:6]  */
01968     } B;
01969 } hw_adc_clms_t;
01970 
01971 /*!
01972  * @name Constants and macros for entire ADC_CLMS register
01973  */
01974 /*@{*/
01975 #define HW_ADC_CLMS_ADDR(x)      ((x) + 0x58U)
01976 
01977 #define HW_ADC_CLMS(x)           (*(__IO hw_adc_clms_t *) HW_ADC_CLMS_ADDR(x))
01978 #define HW_ADC_CLMS_RD(x)        (ADDRESS_READ(hw_adc_clms_t, HW_ADC_CLMS_ADDR(x)))
01979 #define HW_ADC_CLMS_WR(x, v)     (ADDRESS_WRITE(hw_adc_clms_t, HW_ADC_CLMS_ADDR(x), v))
01980 #define HW_ADC_CLMS_SET(x, v)    (HW_ADC_CLMS_WR(x, HW_ADC_CLMS_RD(x) |  (v)))
01981 #define HW_ADC_CLMS_CLR(x, v)    (HW_ADC_CLMS_WR(x, HW_ADC_CLMS_RD(x) & ~(v)))
01982 #define HW_ADC_CLMS_TOG(x, v)    (HW_ADC_CLMS_WR(x, HW_ADC_CLMS_RD(x) ^  (v)))
01983 /*@}*/
01984 
01985 /*
01986  * Constants & macros for individual ADC_CLMS bitfields
01987  */
01988 
01989 /*!
01990  * @name Register ADC_CLMS, field CLMS[5:0] (RW)
01991  *
01992  * Calibration Value
01993  */
01994 /*@{*/
01995 #define BP_ADC_CLMS_CLMS     (0U)          /*!< Bit position for ADC_CLMS_CLMS. */
01996 #define BM_ADC_CLMS_CLMS     (0x0000003FU) /*!< Bit mask for ADC_CLMS_CLMS. */
01997 #define BS_ADC_CLMS_CLMS     (6U)          /*!< Bit field size in bits for ADC_CLMS_CLMS. */
01998 
01999 /*! @brief Read current value of the ADC_CLMS_CLMS field. */
02000 #define BR_ADC_CLMS_CLMS(x)  (UNION_READ(hw_adc_clms_t, HW_ADC_CLMS_ADDR(x), U, B.CLMS))
02001 
02002 /*! @brief Format value for bitfield ADC_CLMS_CLMS. */
02003 #define BF_ADC_CLMS_CLMS(v)  ((uint32_t)((uint32_t)(v) << BP_ADC_CLMS_CLMS) & BM_ADC_CLMS_CLMS)
02004 
02005 /*! @brief Set the CLMS field to a new value. */
02006 #define BW_ADC_CLMS_CLMS(x, v) (HW_ADC_CLMS_WR(x, (HW_ADC_CLMS_RD(x) & ~BM_ADC_CLMS_CLMS) | BF_ADC_CLMS_CLMS(v)))
02007 /*@}*/
02008 
02009 /*******************************************************************************
02010  * HW_ADC_CLM4 - ADC Minus-Side General Calibration Value Register
02011  ******************************************************************************/
02012 
02013 /*!
02014  * @brief HW_ADC_CLM4 - ADC Minus-Side General Calibration Value Register (RW)
02015  *
02016  * Reset value: 0x00000200U
02017  *
02018  * For more information, see CLMD register description.
02019  */
02020 typedef union _hw_adc_clm4
02021 {
02022     uint32_t U;
02023     struct _hw_adc_clm4_bitfields
02024     {
02025         uint32_t CLM4 : 10;            /*!< [9:0]  */
02026         uint32_t RESERVED0 : 22;       /*!< [31:10]  */
02027     } B;
02028 } hw_adc_clm4_t;
02029 
02030 /*!
02031  * @name Constants and macros for entire ADC_CLM4 register
02032  */
02033 /*@{*/
02034 #define HW_ADC_CLM4_ADDR(x)      ((x) + 0x5CU)
02035 
02036 #define HW_ADC_CLM4(x)           (*(__IO hw_adc_clm4_t *) HW_ADC_CLM4_ADDR(x))
02037 #define HW_ADC_CLM4_RD(x)        (ADDRESS_READ(hw_adc_clm4_t, HW_ADC_CLM4_ADDR(x)))
02038 #define HW_ADC_CLM4_WR(x, v)     (ADDRESS_WRITE(hw_adc_clm4_t, HW_ADC_CLM4_ADDR(x), v))
02039 #define HW_ADC_CLM4_SET(x, v)    (HW_ADC_CLM4_WR(x, HW_ADC_CLM4_RD(x) |  (v)))
02040 #define HW_ADC_CLM4_CLR(x, v)    (HW_ADC_CLM4_WR(x, HW_ADC_CLM4_RD(x) & ~(v)))
02041 #define HW_ADC_CLM4_TOG(x, v)    (HW_ADC_CLM4_WR(x, HW_ADC_CLM4_RD(x) ^  (v)))
02042 /*@}*/
02043 
02044 /*
02045  * Constants & macros for individual ADC_CLM4 bitfields
02046  */
02047 
02048 /*!
02049  * @name Register ADC_CLM4, field CLM4[9:0] (RW)
02050  *
02051  * Calibration Value
02052  */
02053 /*@{*/
02054 #define BP_ADC_CLM4_CLM4     (0U)          /*!< Bit position for ADC_CLM4_CLM4. */
02055 #define BM_ADC_CLM4_CLM4     (0x000003FFU) /*!< Bit mask for ADC_CLM4_CLM4. */
02056 #define BS_ADC_CLM4_CLM4     (10U)         /*!< Bit field size in bits for ADC_CLM4_CLM4. */
02057 
02058 /*! @brief Read current value of the ADC_CLM4_CLM4 field. */
02059 #define BR_ADC_CLM4_CLM4(x)  (UNION_READ(hw_adc_clm4_t, HW_ADC_CLM4_ADDR(x), U, B.CLM4))
02060 
02061 /*! @brief Format value for bitfield ADC_CLM4_CLM4. */
02062 #define BF_ADC_CLM4_CLM4(v)  ((uint32_t)((uint32_t)(v) << BP_ADC_CLM4_CLM4) & BM_ADC_CLM4_CLM4)
02063 
02064 /*! @brief Set the CLM4 field to a new value. */
02065 #define BW_ADC_CLM4_CLM4(x, v) (HW_ADC_CLM4_WR(x, (HW_ADC_CLM4_RD(x) & ~BM_ADC_CLM4_CLM4) | BF_ADC_CLM4_CLM4(v)))
02066 /*@}*/
02067 
02068 /*******************************************************************************
02069  * HW_ADC_CLM3 - ADC Minus-Side General Calibration Value Register
02070  ******************************************************************************/
02071 
02072 /*!
02073  * @brief HW_ADC_CLM3 - ADC Minus-Side General Calibration Value Register (RW)
02074  *
02075  * Reset value: 0x00000100U
02076  *
02077  * For more information, see CLMD register description.
02078  */
02079 typedef union _hw_adc_clm3
02080 {
02081     uint32_t U;
02082     struct _hw_adc_clm3_bitfields
02083     {
02084         uint32_t CLM3 : 9;             /*!< [8:0]  */
02085         uint32_t RESERVED0 : 23;       /*!< [31:9]  */
02086     } B;
02087 } hw_adc_clm3_t;
02088 
02089 /*!
02090  * @name Constants and macros for entire ADC_CLM3 register
02091  */
02092 /*@{*/
02093 #define HW_ADC_CLM3_ADDR(x)      ((x) + 0x60U)
02094 
02095 #define HW_ADC_CLM3(x)           (*(__IO hw_adc_clm3_t *) HW_ADC_CLM3_ADDR(x))
02096 #define HW_ADC_CLM3_RD(x)        (ADDRESS_READ(hw_adc_clm3_t, HW_ADC_CLM3_ADDR(x)))
02097 #define HW_ADC_CLM3_WR(x, v)     (ADDRESS_WRITE(hw_adc_clm3_t, HW_ADC_CLM3_ADDR(x), v))
02098 #define HW_ADC_CLM3_SET(x, v)    (HW_ADC_CLM3_WR(x, HW_ADC_CLM3_RD(x) |  (v)))
02099 #define HW_ADC_CLM3_CLR(x, v)    (HW_ADC_CLM3_WR(x, HW_ADC_CLM3_RD(x) & ~(v)))
02100 #define HW_ADC_CLM3_TOG(x, v)    (HW_ADC_CLM3_WR(x, HW_ADC_CLM3_RD(x) ^  (v)))
02101 /*@}*/
02102 
02103 /*
02104  * Constants & macros for individual ADC_CLM3 bitfields
02105  */
02106 
02107 /*!
02108  * @name Register ADC_CLM3, field CLM3[8:0] (RW)
02109  *
02110  * Calibration Value
02111  */
02112 /*@{*/
02113 #define BP_ADC_CLM3_CLM3     (0U)          /*!< Bit position for ADC_CLM3_CLM3. */
02114 #define BM_ADC_CLM3_CLM3     (0x000001FFU) /*!< Bit mask for ADC_CLM3_CLM3. */
02115 #define BS_ADC_CLM3_CLM3     (9U)          /*!< Bit field size in bits for ADC_CLM3_CLM3. */
02116 
02117 /*! @brief Read current value of the ADC_CLM3_CLM3 field. */
02118 #define BR_ADC_CLM3_CLM3(x)  (UNION_READ(hw_adc_clm3_t, HW_ADC_CLM3_ADDR(x), U, B.CLM3))
02119 
02120 /*! @brief Format value for bitfield ADC_CLM3_CLM3. */
02121 #define BF_ADC_CLM3_CLM3(v)  ((uint32_t)((uint32_t)(v) << BP_ADC_CLM3_CLM3) & BM_ADC_CLM3_CLM3)
02122 
02123 /*! @brief Set the CLM3 field to a new value. */
02124 #define BW_ADC_CLM3_CLM3(x, v) (HW_ADC_CLM3_WR(x, (HW_ADC_CLM3_RD(x) & ~BM_ADC_CLM3_CLM3) | BF_ADC_CLM3_CLM3(v)))
02125 /*@}*/
02126 
02127 /*******************************************************************************
02128  * HW_ADC_CLM2 - ADC Minus-Side General Calibration Value Register
02129  ******************************************************************************/
02130 
02131 /*!
02132  * @brief HW_ADC_CLM2 - ADC Minus-Side General Calibration Value Register (RW)
02133  *
02134  * Reset value: 0x00000080U
02135  *
02136  * For more information, see CLMD register description.
02137  */
02138 typedef union _hw_adc_clm2
02139 {
02140     uint32_t U;
02141     struct _hw_adc_clm2_bitfields
02142     {
02143         uint32_t CLM2 : 8;             /*!< [7:0]  */
02144         uint32_t RESERVED0 : 24;       /*!< [31:8]  */
02145     } B;
02146 } hw_adc_clm2_t;
02147 
02148 /*!
02149  * @name Constants and macros for entire ADC_CLM2 register
02150  */
02151 /*@{*/
02152 #define HW_ADC_CLM2_ADDR(x)      ((x) + 0x64U)
02153 
02154 #define HW_ADC_CLM2(x)           (*(__IO hw_adc_clm2_t *) HW_ADC_CLM2_ADDR(x))
02155 #define HW_ADC_CLM2_RD(x)        (ADDRESS_READ(hw_adc_clm2_t, HW_ADC_CLM2_ADDR(x)))
02156 #define HW_ADC_CLM2_WR(x, v)     (ADDRESS_WRITE(hw_adc_clm2_t, HW_ADC_CLM2_ADDR(x), v))
02157 #define HW_ADC_CLM2_SET(x, v)    (HW_ADC_CLM2_WR(x, HW_ADC_CLM2_RD(x) |  (v)))
02158 #define HW_ADC_CLM2_CLR(x, v)    (HW_ADC_CLM2_WR(x, HW_ADC_CLM2_RD(x) & ~(v)))
02159 #define HW_ADC_CLM2_TOG(x, v)    (HW_ADC_CLM2_WR(x, HW_ADC_CLM2_RD(x) ^  (v)))
02160 /*@}*/
02161 
02162 /*
02163  * Constants & macros for individual ADC_CLM2 bitfields
02164  */
02165 
02166 /*!
02167  * @name Register ADC_CLM2, field CLM2[7:0] (RW)
02168  *
02169  * Calibration Value
02170  */
02171 /*@{*/
02172 #define BP_ADC_CLM2_CLM2     (0U)          /*!< Bit position for ADC_CLM2_CLM2. */
02173 #define BM_ADC_CLM2_CLM2     (0x000000FFU) /*!< Bit mask for ADC_CLM2_CLM2. */
02174 #define BS_ADC_CLM2_CLM2     (8U)          /*!< Bit field size in bits for ADC_CLM2_CLM2. */
02175 
02176 /*! @brief Read current value of the ADC_CLM2_CLM2 field. */
02177 #define BR_ADC_CLM2_CLM2(x)  (UNION_READ(hw_adc_clm2_t, HW_ADC_CLM2_ADDR(x), U, B.CLM2))
02178 
02179 /*! @brief Format value for bitfield ADC_CLM2_CLM2. */
02180 #define BF_ADC_CLM2_CLM2(v)  ((uint32_t)((uint32_t)(v) << BP_ADC_CLM2_CLM2) & BM_ADC_CLM2_CLM2)
02181 
02182 /*! @brief Set the CLM2 field to a new value. */
02183 #define BW_ADC_CLM2_CLM2(x, v) (HW_ADC_CLM2_WR(x, (HW_ADC_CLM2_RD(x) & ~BM_ADC_CLM2_CLM2) | BF_ADC_CLM2_CLM2(v)))
02184 /*@}*/
02185 
02186 /*******************************************************************************
02187  * HW_ADC_CLM1 - ADC Minus-Side General Calibration Value Register
02188  ******************************************************************************/
02189 
02190 /*!
02191  * @brief HW_ADC_CLM1 - ADC Minus-Side General Calibration Value Register (RW)
02192  *
02193  * Reset value: 0x00000040U
02194  *
02195  * For more information, see CLMD register description.
02196  */
02197 typedef union _hw_adc_clm1
02198 {
02199     uint32_t U;
02200     struct _hw_adc_clm1_bitfields
02201     {
02202         uint32_t CLM1 : 7;             /*!< [6:0]  */
02203         uint32_t RESERVED0 : 25;       /*!< [31:7]  */
02204     } B;
02205 } hw_adc_clm1_t;
02206 
02207 /*!
02208  * @name Constants and macros for entire ADC_CLM1 register
02209  */
02210 /*@{*/
02211 #define HW_ADC_CLM1_ADDR(x)      ((x) + 0x68U)
02212 
02213 #define HW_ADC_CLM1(x)           (*(__IO hw_adc_clm1_t *) HW_ADC_CLM1_ADDR(x))
02214 #define HW_ADC_CLM1_RD(x)        (ADDRESS_READ(hw_adc_clm1_t, HW_ADC_CLM1_ADDR(x)))
02215 #define HW_ADC_CLM1_WR(x, v)     (ADDRESS_WRITE(hw_adc_clm1_t, HW_ADC_CLM1_ADDR(x), v))
02216 #define HW_ADC_CLM1_SET(x, v)    (HW_ADC_CLM1_WR(x, HW_ADC_CLM1_RD(x) |  (v)))
02217 #define HW_ADC_CLM1_CLR(x, v)    (HW_ADC_CLM1_WR(x, HW_ADC_CLM1_RD(x) & ~(v)))
02218 #define HW_ADC_CLM1_TOG(x, v)    (HW_ADC_CLM1_WR(x, HW_ADC_CLM1_RD(x) ^  (v)))
02219 /*@}*/
02220 
02221 /*
02222  * Constants & macros for individual ADC_CLM1 bitfields
02223  */
02224 
02225 /*!
02226  * @name Register ADC_CLM1, field CLM1[6:0] (RW)
02227  *
02228  * Calibration Value
02229  */
02230 /*@{*/
02231 #define BP_ADC_CLM1_CLM1     (0U)          /*!< Bit position for ADC_CLM1_CLM1. */
02232 #define BM_ADC_CLM1_CLM1     (0x0000007FU) /*!< Bit mask for ADC_CLM1_CLM1. */
02233 #define BS_ADC_CLM1_CLM1     (7U)          /*!< Bit field size in bits for ADC_CLM1_CLM1. */
02234 
02235 /*! @brief Read current value of the ADC_CLM1_CLM1 field. */
02236 #define BR_ADC_CLM1_CLM1(x)  (UNION_READ(hw_adc_clm1_t, HW_ADC_CLM1_ADDR(x), U, B.CLM1))
02237 
02238 /*! @brief Format value for bitfield ADC_CLM1_CLM1. */
02239 #define BF_ADC_CLM1_CLM1(v)  ((uint32_t)((uint32_t)(v) << BP_ADC_CLM1_CLM1) & BM_ADC_CLM1_CLM1)
02240 
02241 /*! @brief Set the CLM1 field to a new value. */
02242 #define BW_ADC_CLM1_CLM1(x, v) (HW_ADC_CLM1_WR(x, (HW_ADC_CLM1_RD(x) & ~BM_ADC_CLM1_CLM1) | BF_ADC_CLM1_CLM1(v)))
02243 /*@}*/
02244 
02245 /*******************************************************************************
02246  * HW_ADC_CLM0 - ADC Minus-Side General Calibration Value Register
02247  ******************************************************************************/
02248 
02249 /*!
02250  * @brief HW_ADC_CLM0 - ADC Minus-Side General Calibration Value Register (RW)
02251  *
02252  * Reset value: 0x00000020U
02253  *
02254  * For more information, see CLMD register description.
02255  */
02256 typedef union _hw_adc_clm0
02257 {
02258     uint32_t U;
02259     struct _hw_adc_clm0_bitfields
02260     {
02261         uint32_t CLM0 : 6;             /*!< [5:0]  */
02262         uint32_t RESERVED0 : 26;       /*!< [31:6]  */
02263     } B;
02264 } hw_adc_clm0_t;
02265 
02266 /*!
02267  * @name Constants and macros for entire ADC_CLM0 register
02268  */
02269 /*@{*/
02270 #define HW_ADC_CLM0_ADDR(x)      ((x) + 0x6CU)
02271 
02272 #define HW_ADC_CLM0(x)           (*(__IO hw_adc_clm0_t *) HW_ADC_CLM0_ADDR(x))
02273 #define HW_ADC_CLM0_RD(x)        (ADDRESS_READ(hw_adc_clm0_t, HW_ADC_CLM0_ADDR(x)))
02274 #define HW_ADC_CLM0_WR(x, v)     (ADDRESS_WRITE(hw_adc_clm0_t, HW_ADC_CLM0_ADDR(x), v))
02275 #define HW_ADC_CLM0_SET(x, v)    (HW_ADC_CLM0_WR(x, HW_ADC_CLM0_RD(x) |  (v)))
02276 #define HW_ADC_CLM0_CLR(x, v)    (HW_ADC_CLM0_WR(x, HW_ADC_CLM0_RD(x) & ~(v)))
02277 #define HW_ADC_CLM0_TOG(x, v)    (HW_ADC_CLM0_WR(x, HW_ADC_CLM0_RD(x) ^  (v)))
02278 /*@}*/
02279 
02280 /*
02281  * Constants & macros for individual ADC_CLM0 bitfields
02282  */
02283 
02284 /*!
02285  * @name Register ADC_CLM0, field CLM0[5:0] (RW)
02286  *
02287  * Calibration Value
02288  */
02289 /*@{*/
02290 #define BP_ADC_CLM0_CLM0     (0U)          /*!< Bit position for ADC_CLM0_CLM0. */
02291 #define BM_ADC_CLM0_CLM0     (0x0000003FU) /*!< Bit mask for ADC_CLM0_CLM0. */
02292 #define BS_ADC_CLM0_CLM0     (6U)          /*!< Bit field size in bits for ADC_CLM0_CLM0. */
02293 
02294 /*! @brief Read current value of the ADC_CLM0_CLM0 field. */
02295 #define BR_ADC_CLM0_CLM0(x)  (UNION_READ(hw_adc_clm0_t, HW_ADC_CLM0_ADDR(x), U, B.CLM0))
02296 
02297 /*! @brief Format value for bitfield ADC_CLM0_CLM0. */
02298 #define BF_ADC_CLM0_CLM0(v)  ((uint32_t)((uint32_t)(v) << BP_ADC_CLM0_CLM0) & BM_ADC_CLM0_CLM0)
02299 
02300 /*! @brief Set the CLM0 field to a new value. */
02301 #define BW_ADC_CLM0_CLM0(x, v) (HW_ADC_CLM0_WR(x, (HW_ADC_CLM0_RD(x) & ~BM_ADC_CLM0_CLM0) | BF_ADC_CLM0_CLM0(v)))
02302 /*@}*/
02303 
02304 /*******************************************************************************
02305  * hw_adc_t - module struct
02306  ******************************************************************************/
02307 /*!
02308  * @brief All ADC module registers.
02309  */
02310 #pragma pack(1)
02311 typedef struct _hw_adc
02312 {
02313     __IO hw_adc_sc1n_t SC1n [2];            /*!< [0x0] ADC Status and Control Registers 1 */
02314     __IO hw_adc_cfg1_t CFG1 ;               /*!< [0x8] ADC Configuration Register 1 */
02315     __IO hw_adc_cfg2_t CFG2 ;               /*!< [0xC] ADC Configuration Register 2 */
02316     __I hw_adc_rn_t Rn [2];                 /*!< [0x10] ADC Data Result Register */
02317     __IO hw_adc_cv1_t CV1 ;                 /*!< [0x18] Compare Value Registers */
02318     __IO hw_adc_cv2_t CV2 ;                 /*!< [0x1C] Compare Value Registers */
02319     __IO hw_adc_sc2_t SC2 ;                 /*!< [0x20] Status and Control Register 2 */
02320     __IO hw_adc_sc3_t SC3 ;                 /*!< [0x24] Status and Control Register 3 */
02321     __IO hw_adc_ofs_t OFS ;                 /*!< [0x28] ADC Offset Correction Register */
02322     __IO hw_adc_pg_t PG ;                   /*!< [0x2C] ADC Plus-Side Gain Register */
02323     __IO hw_adc_mg_t MG ;                   /*!< [0x30] ADC Minus-Side Gain Register */
02324     __IO hw_adc_clpd_t CLPD ;               /*!< [0x34] ADC Plus-Side General Calibration Value Register */
02325     __IO hw_adc_clps_t CLPS ;               /*!< [0x38] ADC Plus-Side General Calibration Value Register */
02326     __IO hw_adc_clp4_t CLP4 ;               /*!< [0x3C] ADC Plus-Side General Calibration Value Register */
02327     __IO hw_adc_clp3_t CLP3 ;               /*!< [0x40] ADC Plus-Side General Calibration Value Register */
02328     __IO hw_adc_clp2_t CLP2 ;               /*!< [0x44] ADC Plus-Side General Calibration Value Register */
02329     __IO hw_adc_clp1_t CLP1 ;               /*!< [0x48] ADC Plus-Side General Calibration Value Register */
02330     __IO hw_adc_clp0_t CLP0 ;               /*!< [0x4C] ADC Plus-Side General Calibration Value Register */
02331     uint8_t _reserved0[4];
02332     __IO hw_adc_clmd_t CLMD ;               /*!< [0x54] ADC Minus-Side General Calibration Value Register */
02333     __IO hw_adc_clms_t CLMS ;               /*!< [0x58] ADC Minus-Side General Calibration Value Register */
02334     __IO hw_adc_clm4_t CLM4 ;               /*!< [0x5C] ADC Minus-Side General Calibration Value Register */
02335     __IO hw_adc_clm3_t CLM3 ;               /*!< [0x60] ADC Minus-Side General Calibration Value Register */
02336     __IO hw_adc_clm2_t CLM2 ;               /*!< [0x64] ADC Minus-Side General Calibration Value Register */
02337     __IO hw_adc_clm1_t CLM1 ;               /*!< [0x68] ADC Minus-Side General Calibration Value Register */
02338     __IO hw_adc_clm0_t CLM0 ;               /*!< [0x6C] ADC Minus-Side General Calibration Value Register */
02339 } hw_adc_t;
02340 #pragma pack()
02341 
02342 /*! @brief Macro to access all ADC registers. */
02343 /*! @param x ADC module instance base address. */
02344 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
02345  *     use the '&' operator, like <code>&HW_ADC(ADC0_BASE)</code>. */
02346 #define HW_ADC(x)      (*(hw_adc_t *)(x))
02347 
02348 #endif /* __HW_ADC_REGISTERS_H__ */
02349 /* EOF */