Andy K / Mbed 2 deprecated SOWB

Satellite Observers Workbench. NOT yet complete, just published for forum posters to \"cherry pick\" pieces of code as requiered as an example.

Dependencies:   mbed

flash/ssp0.c@0:0a841b89d614, 2010-10-11 (annotated)

Committer:
AjK
Date:
Mon Oct 11 10:34:55 2010 +0000
Revision:
0:0a841b89d614
Totally Alpha quality as this project isn\t completed. Just publishing it as it answers many questions asked in the forums

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AjK 0:0a841b89d614 1 /****************************************************************************
AjK 0:0a841b89d614 2 * Copyright 2010 Andy Kirkham, Stellar Technologies Ltd
AjK 0:0a841b89d614 3 *
AjK 0:0a841b89d614 4 * This file is part of the Satellite Observers Workbench (SOWB).
AjK 0:0a841b89d614 5 *
AjK 0:0a841b89d614 6 * SOWB is free software: you can redistribute it and/or modify
AjK 0:0a841b89d614 7 * it under the terms of the GNU General Public License as published by
AjK 0:0a841b89d614 8 * the Free Software Foundation, either version 3 of the License, or
AjK 0:0a841b89d614 9 * (at your option) any later version.
AjK 0:0a841b89d614 10 *
AjK 0:0a841b89d614 11 * SOWB is distributed in the hope that it will be useful,
AjK 0:0a841b89d614 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
AjK 0:0a841b89d614 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
AjK 0:0a841b89d614 14 * GNU General Public License for more details.
AjK 0:0a841b89d614 15 *
AjK 0:0a841b89d614 16 * You should have received a copy of the GNU General Public License
AjK 0:0a841b89d614 17 * along with SOWB. If not, see <http://www.gnu.org/licenses/>.
AjK 0:0a841b89d614 18 *
AjK 0:0a841b89d614 19 * $Id: main.cpp 5 2010-07-12 20:51:11Z ajk $
AjK 0:0a841b89d614 20 *
AjK 0:0a841b89d614 21 ***************************************************************************/
AjK 0:0a841b89d614 22
AjK 0:0a841b89d614 23 #include "sowb.h"
AjK 0:0a841b89d614 24 #include "debug.h"
AjK 0:0a841b89d614 25 #include "ssp0.h"
AjK 0:0a841b89d614 26
AjK 0:0a841b89d614 27 bool ssp0_in_use;
AjK 0:0a841b89d614 28
AjK 0:0a841b89d614 29 bool SSP0_request(void) {
AjK 0:0a841b89d614 30 if (!ssp0_in_use) {
AjK 0:0a841b89d614 31 ssp0_in_use = true;
AjK 0:0a841b89d614 32 return true;
AjK 0:0a841b89d614 33 }
AjK 0:0a841b89d614 34 return false;
AjK 0:0a841b89d614 35 }
AjK 0:0a841b89d614 36
AjK 0:0a841b89d614 37 void SSP0_release(void) {
AjK 0:0a841b89d614 38 ssp0_in_use = false;
AjK 0:0a841b89d614 39 }
AjK 0:0a841b89d614 40
AjK 0:0a841b89d614 41 /* Declare ISR callbacks. */
AjK 0:0a841b89d614 42 extern int flash_read_ssp0_irq(void);
AjK 0:0a841b89d614 43 extern int flash_write_ssp0_irq(void);
AjK 0:0a841b89d614 44
AjK 0:0a841b89d614 45 /* Function pointer type for the following table. */
AjK 0:0a841b89d614 46 typedef int (*SSP0_callback)(void);
AjK 0:0a841b89d614 47
AjK 0:0a841b89d614 48 /* Define an array of callbacks to make. */
AjK 0:0a841b89d614 49 const SSP0_callback ssp0_callbacks[] = {
AjK 0:0a841b89d614 50 flash_read_ssp0_irq,
AjK 0:0a841b89d614 51 flash_write_ssp0_irq,
AjK 0:0a841b89d614 52 NULL
AjK 0:0a841b89d614 53 };
AjK 0:0a841b89d614 54
AjK 0:0a841b89d614 55 /** SSP0_IRQHandler
AjK 0:0a841b89d614 56 */
AjK 0:0a841b89d614 57 extern "C" void SSP0_IRQHandler(void) __irq {
AjK 0:0a841b89d614 58 for (int i = 0; ssp0_callbacks[i] != NULL; i++) {
AjK 0:0a841b89d614 59 if ((ssp0_callbacks[i])() != 0) {
AjK 0:0a841b89d614 60 break;
AjK 0:0a841b89d614 61 }
AjK 0:0a841b89d614 62 }
AjK 0:0a841b89d614 63 }
AjK 0:0a841b89d614 64
AjK 0:0a841b89d614 65 /** SSP0_init
AjK 0:0a841b89d614 66 */
AjK 0:0a841b89d614 67 void SSP0_init(void) {
AjK 0:0a841b89d614 68
AjK 0:0a841b89d614 69 DEBUG_INIT_START;
AjK 0:0a841b89d614 70
AjK 0:0a841b89d614 71 ssp0_in_use = false;
AjK 0:0a841b89d614 72
AjK 0:0a841b89d614 73 /* The flash device is connected to SSP1 via the Mbed pins.
AjK 0:0a841b89d614 74 So this init is about configuring just the SSP1. */
AjK 0:0a841b89d614 75
AjK 0:0a841b89d614 76 /* Enable the SSP1 peripheral. */
AjK 0:0a841b89d614 77 //LPC_SC->PCONP |= (1UL << 10);
AjK 0:0a841b89d614 78 LPC_SC->PCONP |= (1UL << 21);
AjK 0:0a841b89d614 79
AjK 0:0a841b89d614 80 /* Select the clock required for SSP1. */
AjK 0:0a841b89d614 81 LPC_SC->PCLKSEL1 &= ~(3UL << 10);
AjK 0:0a841b89d614 82 LPC_SC->PCLKSEL1 |= (3UL << 10);
AjK 0:0a841b89d614 83 //LPC_SC->PCLKSEL0 &= ~(3UL << 20);
AjK 0:0a841b89d614 84 //LPC_SC->PCLKSEL0 |= (3UL << 20);
AjK 0:0a841b89d614 85
AjK 0:0a841b89d614 86 /* Select the GPIO pins for the SSP0 functions. */
AjK 0:0a841b89d614 87 /* SCK0 */
AjK 0:0a841b89d614 88 LPC_PINCON->PINSEL0 &= ~(3UL << 30);
AjK 0:0a841b89d614 89 LPC_PINCON->PINSEL0 |= (2UL << 30);
AjK 0:0a841b89d614 90 /* MISO0 */
AjK 0:0a841b89d614 91 LPC_PINCON->PINSEL1 &= ~(3UL << 2);
AjK 0:0a841b89d614 92 LPC_PINCON->PINSEL1 |= (2UL << 2);
AjK 0:0a841b89d614 93 /* MISI0 */
AjK 0:0a841b89d614 94 LPC_PINCON->PINSEL1 &= ~(3UL << 4);
AjK 0:0a841b89d614 95 LPC_PINCON->PINSEL1 |= (2UL << 4);
AjK 0:0a841b89d614 96
AjK 0:0a841b89d614 97 /* Select the GPIO pins for the SSP1 functions. */
AjK 0:0a841b89d614 98 /* SCK1 */
AjK 0:0a841b89d614 99 //LPC_PINCON->PINSEL0 &= ~(3UL << 14);
AjK 0:0a841b89d614 100 //LPC_PINCON->PINSEL0 |= (2UL << 14);
AjK 0:0a841b89d614 101 /* MISO1 */
AjK 0:0a841b89d614 102 //LPC_PINCON->PINSEL0 &= ~(3UL << 16);
AjK 0:0a841b89d614 103 //LPC_PINCON->PINSEL0 |= (2UL << 16);
AjK 0:0a841b89d614 104 /* MOSI1 */
AjK 0:0a841b89d614 105 //LPC_PINCON->PINSEL0 &= ~(3UL << 18);
AjK 0:0a841b89d614 106 //LPC_PINCON->PINSEL0 |= (2UL << 18);
AjK 0:0a841b89d614 107
AjK 0:0a841b89d614 108 /* Note, we don't use SSEL1 in our design, we just use a standard GPIO
AjK 0:0a841b89d614 109 because writing multi-byte data is simpler. */
AjK 0:0a841b89d614 110
AjK 0:0a841b89d614 111 /* Setup the interrupt system. Note however, the SSP1 interrupt
AjK 0:0a841b89d614 112 is only actually activated within the DMA ISR and is self disabling. */
AjK 0:0a841b89d614 113 NVIC_SetVector(SSP0_IRQn, (uint32_t)SSP0_IRQHandler);
AjK 0:0a841b89d614 114 NVIC_EnableIRQ(SSP0_IRQn);
AjK 0:0a841b89d614 115
AjK 0:0a841b89d614 116 /* Setup the control registers for SSP1 */
AjK 0:0a841b89d614 117 LPC_SSP0->IMSC = 0;
AjK 0:0a841b89d614 118 LPC_SSP0->CR0 = 0x7;
AjK 0:0a841b89d614 119 LPC_SSP0->CPSR = FLASH_SSP_INIT_CPSR;
AjK 0:0a841b89d614 120 LPC_SSP0->CR1 = 0x2;
AjK 0:0a841b89d614 121
AjK 0:0a841b89d614 122 DEBUG_INIT_END;
AjK 0:0a841b89d614 123 }
AjK 0:0a841b89d614 124